JPH03195053A - Inverter device - Google Patents
Inverter deviceInfo
- Publication number
- JPH03195053A JPH03195053A JP1335562A JP33556289A JPH03195053A JP H03195053 A JPH03195053 A JP H03195053A JP 1335562 A JP1335562 A JP 1335562A JP 33556289 A JP33556289 A JP 33556289A JP H03195053 A JPH03195053 A JP H03195053A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- power
- ceramic piece
- conductive path
- main circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 239000000919 ceramic Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 9
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 claims description 4
- 239000011889 copper foil Substances 0.000 claims description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 229910052582 BN Inorganic materials 0.000 claims description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 1
- 229910010271 silicon carbide Inorganic materials 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011347 resin Substances 0.000 abstract description 3
- 229920005989 resin Polymers 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 238000007747 plating Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005219 brazing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000007751 thermal spraying Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Inverter Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はインパークの主回路とその主回路を駆動させる
駆動回路とが同一基板上に構成されたインバータ装置に
関し、特にハイパワーのインパーク装置に関Ｃる。Detailed Description of the Invention (a) Field of Industrial Application The present invention relates to an inverter device in which a main circuit of an impark and a drive circuit for driving the main circuit are configured on the same substrate, and particularly relates to a high-power inverter device. Regarding park equipment.
（口〉従来の技術
従来から、パワー用の半導体素子を搭載したパワー用の
集積回路はその動作中に発生する熱放散を考慮していわ
ゆるヒートシンク（銅板）を使用する方式が多用されて
いる。この方式のパワー用の集積回路の中には回路パタ
ーンを一面に形成し、他面に銅よりなる熱伝導層を設け
たアルミナセラミック板を前記ヒートシンク（以後放熱
板と呼称する）に半田付けして一体とする型がある。(Example) Conventional technology Conventionally, power integrated circuits equipped with power semiconductor elements have often used a so-called heat sink (copper plate) in consideration of heat dissipation generated during operation. In this type of power integrated circuit, an alumina ceramic plate with a circuit pattern formed on one side and a thermally conductive layer made of copper on the other side is soldered to the heat sink (hereinafter referred to as a heat sink). There is a type that integrates both.
この型のパワー用集積回路は第４図に示す如く、アルミ
ナセラミックス基板（５１）の−主面に導電性のよい銅
で回路パターン（５２）を形成し、その一部であるパッ
ド部（５２’）にパワー用半導体素子（５３）をろう材
によって固着する。ところで、銅の回路パターン（５２
）は溶射法、メツキ法、メタライズ法、印刷法および蒸
着法の単独又はその組合せで形成するか、あるいは銅板
をろう付けする方法で固定し大電流の回路パターン（５
２〉が形成される。As shown in FIG. 4, this type of power integrated circuit has a circuit pattern (52) made of highly conductive copper formed on the main surface of an alumina ceramic substrate (51), and a pad portion (52) that is a part of the circuit pattern (52) is formed on the main surface of an alumina ceramic substrate (51). '), a power semiconductor element (53) is fixed to it with a brazing material. By the way, the copper circuit pattern (52
) is formed by thermal spraying, plating, metallizing, printing, and vapor deposition methods alone or in combination, or by brazing a copper plate to form a large current circuit pattern (5
2> is formed.
半導体素子（５３）の電極と前記回路パターン（５２）
の一部を構成するパッド部（５２’）を導電性金属細１
１１！（６１）で接続し、前記アルミナセラミックス基
板（５１〉の他面に被着した銅からなる熱伝導層（５４
）と放熱板（５５）とを半田層によって固着していた。Electrodes of the semiconductor element (53) and the circuit pattern (52)
The pad portion (52') constituting a part of the conductive metal thin 1
11! (61), and a thermally conductive layer (54) made of copper adhered to the other surface of the alumina ceramic substrate (51>).
) and the heat sink (55) were fixed together by a solder layer.
斯る放熱板（５５）上には上述したパワー回路が形成さ
れたアルミナセラミックス基板（５１）が複数個固着搭
載され、各アルミナセラミックス基板（５１）上に形成
されたパッド部（５２’）を上述した細線で接続し所定
のパワー回路、例えばインバータ回路のパワ一部分を集
積回路化してパワーモジュールＩＣとして使用されてい
る。A plurality of alumina ceramic substrates (51) on which the above-mentioned power circuits are formed are fixedly mounted on the heat sink (55), and pad portions (52') formed on each alumina ceramic substrate (51) are fixedly mounted on the heat sink (55). A predetermined power circuit, for example, a power portion of an inverter circuit, is connected to the above-mentioned thin wires and integrated into an integrated circuit, which is used as a power module IC.
（ハ）発明が解決しようとする課題
第４図の如き、パワーモジュールＩＣではインバータ装
置のパワ一部分となる主回路のみが構成されているため
に大電流化として見ればその効果は大である。しかしな
がら、第４図のパワーモジュールでは上述した如く、イ
ンバータの主回路のみしか形成されておらずその主回路
を駆動させる駆動回路は別部品での外付となりシステム
として見れば大型となる問題がある。(c) Problems to be Solved by the Invention As shown in FIG. 4, in a power module IC, only the main circuit which is a part of the power of the inverter device is constructed, so the effect is large when viewed from the perspective of increasing the current. However, as mentioned above, in the power module shown in Fig. 4, only the main circuit of the inverter is formed, and the drive circuit that drives the main circuit is a separate external component, resulting in a large system. .
また、第４図の如き、構造ではセラミックス基板を使用
するために大電流用のパターンは形成できるが小信号用
のファインパターンを形成することが困難であるため、
インバータのハイパワー用主回路と駆動回路とを同一基
板上に形成することが不可能であった。Furthermore, since the structure shown in Fig. 4 uses a ceramic substrate, it is possible to form patterns for large currents, but it is difficult to form fine patterns for small signals.
It has been impossible to form the high power main circuit and drive circuit of an inverter on the same substrate.
（ニ）課題を解決するための手段
本発明は上述した課題に鑑みて為されたものであり、金
属基板と前記基板上に貼着され且つ前記基板表面を露出
させる複数の孔が設けられた絶縁薄層と前記絶縁薄層上
に形成された所望形状の導電路と前記孔で露出した前記
基板上に固着された熱抵抗比の小さいセラミックス片と
前記セラミックス片上に固着され前記導電路と接続され
たパワーインバータの主回路となる複数のパワー素子と
前記主回路を駆動させ且つ前記基板上に配置された駆動
回路となる複数の小信号回路素子とを具備したことを特
徴とする。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes a metal substrate and a plurality of holes attached to the substrate and exposing the surface of the substrate. a thin insulating layer, a conductive path of a desired shape formed on the thin insulating layer, a ceramic piece with a low thermal resistance ratio fixed on the substrate exposed through the hole, and a ceramic piece fixed on the ceramic piece and connected to the conductive path. The power inverter is characterized by comprising a plurality of power elements serving as a main circuit of the power inverter, and a plurality of small signal circuit elements serving as a drive circuit for driving the main circuit and disposed on the substrate.
（＊）作用
この様に本発明に依れば、金属基板上に貼着する絶縁樹
脂薄層に基板表面を露出させる孔を設け、その孔で露出
された基板上にセラミックス片を介してインバータの主
回路となるパワー素子を搭載し、他の領域上に主回路を
駆動させる複数の小信号用素子を配置することにより、
パワー素子の熱放散性を極めて向上させることができ且
つ同一基板上に小信号用素子が固着できる。その結果、
ハイパワー用の主回路と駆動回路とを一体化したインバ
ータ装置を提供することができる。(*) Function As described above, according to the present invention, a hole is provided in the thin insulating resin layer adhered to a metal substrate to expose the surface of the substrate, and an inverter is placed on the substrate exposed through the hole through a ceramic piece. By installing a power element that serves as the main circuit of
The heat dissipation properties of the power device can be greatly improved, and small signal devices can be fixed on the same substrate. the result,
It is possible to provide an inverter device that integrates a high-power main circuit and a drive circuit.
（へ）実施例
以下に第１図および第２図に示した実施例に基づいて本
発明の詳細な説明する。(F) EXAMPLE The present invention will be described in detail below based on the example shown in FIGS. 1 and 2.
第１図は本発明のインバータ装置を示す平面図であり、
第２図は第１図のＩ−Ｉ断面図である。FIG. 1 is a plan view showing an inverter device of the present invention,
FIG. 2 is a sectional view taken along line II in FIG.
第１図および第２図に示す如く、本発明のインバータ装
置は、金属基板（１）と、その基板−主面上に貼着され
た複数の孔（２ａ）を有した絶縁薄層（２）と、絶縁薄
層（２）上に形成された所望形状の導電路（３）と、孔
（２ａ）によって露出された基板（１）上に固着された
セラミックス片（４）と、セラミックス片（４）上に固
着されたパワー素子（５）と、導電路（３）上に固着さ
れた複数の小信号素子（６）とから構成されている。As shown in FIGS. 1 and 2, the inverter device of the present invention includes a metal substrate (1) and an insulating thin layer (2a) having a plurality of holes (2a) attached to the main surface of the substrate. ), a conductive path (3) of a desired shape formed on the insulating thin layer (2), a ceramic piece (4) fixed on the substrate (1) exposed by the hole (2a), and a ceramic piece (4) Consists of a power element (5) fixed on the top and a plurality of small signal elements (6) fixed on the conductive path (3).
金属基板（１）として２〜５ｗｎ厚の銅基板が用いられ
る。その銅基板の表面には銅の酸化および機械的強度を
増すために無電解メツキによってニッケルメッキ膜（１
ａ）がコーティングされている。A copper substrate with a thickness of 2 to 5 wn is used as the metal substrate (1). The surface of the copper substrate is coated with a nickel plating film (1 layer) by electroless plating to increase copper oxidation and mechanical strength.
a) is coated.
基板（１）の−主面に貼着される絶縁薄層（２）として
は、例えばエポキシあるいはポリイミド樹脂が用いられ
、その所定位置には複数の孔（２ａ）が設けられている
。孔（２ａ）は基板（１）に貼着される前にプレス等の
手段によってあらかじめ形成される。For example, epoxy or polyimide resin is used as the insulating thin layer (2) attached to the main surface of the substrate (1), and a plurality of holes (2a) are provided at predetermined positions. The holes (2a) are formed in advance by means such as pressing before being attached to the substrate (1).
基板（１）上に絶縁薄層（２）を貼着すると複数の孔（
２ａ）によらて基板（１）の表面のみが露出されること
になる。その孔（２ａ）は基板（１）の略中央部に配置
する様に設けられる。本実施例では三相インバータを用
いているために孔（２ａ）は６個形成されることになる
。When the insulating thin layer (2) is pasted on the substrate (1), a plurality of holes (
2a), only the surface of the substrate (1) is exposed. The hole (2a) is provided so as to be located approximately at the center of the substrate (1). In this embodiment, since a three-phase inverter is used, six holes (2a) are formed.
斯る絶縁薄層（２）上には銅箔より成る所望形状の導電
路（３〉が形成される。ところで、銅箔と絶縁薄層（２
）とは、あらかじめ接着剤で一体化されており、絶縁薄
層（２）を基板（１〉上に貼着する際に銅箔も同時に貼
着される。導電路（３）は第１図から明らかな如く、パ
ワー用の導電路（３ａ）と小信号用の導電路（３ｂ）と
が形成される。パワー用の導電路（３ａ）は孔（２ａ）
間を延在する様に形成され、その延在され基板（１）の
周端辺にはパワー用リード端子が固着されるパワー用パ
ッド（３Ｃ）が形成される。一方、小信号用の導電路（
３ｂ）はパワー用の導電路（３ａ）を挾む様に基板（１
）の両端部の領域に形成され、パワー用パッド（３Ｃ）
の対向辺側に導電路（３ｂ）が延在され小信号用のパッ
ド（３ｄ）が形成される。また、パワー用の導電路（３
ａ）上には大電流を対応とするために表面がＮｉメツキ
処理された鋼板（７）を本実施例では固着している。更
に本実施例で形成される小信号用の導電路（３ｂ）は３
０〜１００μクラスのファインパターンが形成される。A conductive path (3) made of copper foil and having a desired shape is formed on the insulating thin layer (2).
) are integrated with adhesive in advance, and when pasting the insulating thin layer (2) onto the substrate (1), the copper foil is also pasted at the same time.The conductive path (3) is shown in Figure 1. As is clear from the figure, a conductive path (3a) for power and a conductive path (3b) for small signals are formed.The conductive path (3a) for power is connected to the hole (2a).
A power pad (3C) to which a power lead terminal is fixed is formed on the extended peripheral edge of the substrate (1). On the other hand, the conductive path for small signals (
3b) is a substrate (1) sandwiching the power conductive path (3a).
) is formed at both ends of the power pad (3C).
A conductive path (3b) is extended on the side opposite to the side, and a small signal pad (3d) is formed. In addition, a conductive path for power (3
a) In this embodiment, a steel plate (7) whose surface is plated with Ni in order to handle large currents is fixed on top. Furthermore, the conductive path (3b) for small signals formed in this example is 3
A fine pattern of 0 to 100μ class is formed.
ところで、孔（２ａ）によって露出された基板（１）上
には熱抵抗比の小さいセラミックス片（４）を介してパ
ワー素子（５）が基板（１）上に搭載される。Incidentally, a power element (5) is mounted on the substrate (1) exposed through the hole (2a) via a ceramic piece (4) having a small thermal resistance ratio.
熱抵抗比の小さいセラミックス片（４）として、例えば
窒化アルミニウム、窒化ホウ素、ベリリア等の材料があ
るが、本実施例でもつとも一般的である窒化アルミニウ
ムを用いるものとする。第３図はそのセラミックス片（
４）を示す断面図であり、その上下面には酸化銅を介し
て銅板が固着された導体層（４ａ）が形成されている。As the ceramic piece (4) having a low thermal resistance ratio, there are materials such as aluminum nitride, boron nitride, beryllia, etc., but in this embodiment, aluminum nitride, which is the most common, is used. Figure 3 shows the ceramic piece (
4), in which a conductor layer (4a) to which a copper plate is fixed via copper oxide is formed on the upper and lower surfaces thereof.
従って基板（１）上には半田によって固着できることが
可能となる。また、セラミックス片（４）上に固着され
るパワー素子（５）も半田によって固着搭載されること
はいうまでもない。また、上述したセラミックス片（４
）の上下面に形成された導体層（４ａ）の表面には図示
されないがニッケルメッキ膜が形成されている。Therefore, it becomes possible to fix it onto the substrate (1) by soldering. It goes without saying that the power element (5) fixed on the ceramic piece (4) is also fixedly mounted by solder. In addition, the above-mentioned ceramic piece (4
Although not shown, a nickel plating film is formed on the surface of the conductor layer (4a) formed on the upper and lower surfaces of the conductor layer (4a).
セラミックス片（４）上に固着したパワー素子（５）と
パワー用の導電路（３ａ）とはアルミニウム線によって
ボンディング接続しインバータの主回路となる様にブリ
ッジ接続を行う。本実施例ではセラミックス片（４）が
孔（２ａ）によって独立状態であるために、上述した主
回路を構成すべきブリッジ回路を形成するためにセラミ
ックス片（４）とパワー用の導電路（３ａ）とを接続し
てインバータの主回路を形成することができる。The power element (5) fixed on the ceramic piece (4) and the power conductive path (3a) are bonded and connected by aluminum wire, and a bridge connection is made to form the main circuit of the inverter. In this embodiment, since the ceramic piece (4) is in an independent state due to the hole (2a), the ceramic piece (4) and the power conductive path (3a) are used to form a bridge circuit that constitutes the main circuit described above. ) can be connected to form the main circuit of the inverter.
セラミックス片（４）の上下面には上述した如く、導体
層（４ａ）が形成されているため、セラミックス片（４
）上に固着されたパワー素子（５）、例えばパワートラ
ンジスタのコレクタが導体層（４ａ）と共通となり、導
体層（４ａ）とパワー用の導電路（３ａ）とをワイヤ線
等で接続することによりパワーインバータの主回路を構
成することができる。導体層（４ａ）とパワー用の導電
路（３ａ）とはアルミニウム線でボンディング接続きれ
るが、このとき夫々の表面にはニッケルメッキ膜が形成
されているために何ら問題はない。As described above, the conductor layer (4a) is formed on the upper and lower surfaces of the ceramic piece (4).
), the collector of a power element (5), for example a power transistor, fixed on the conductor layer (4a) is in common with the conductor layer (4a), and the conductor layer (4a) and the power conductive path (3a) are connected with a wire or the like. The main circuit of the power inverter can be constructed by the following. The conductor layer (4a) and the power conductive path (3a) can be bonded and connected using aluminum wires, but there is no problem at this time because a nickel plating film is formed on each surface.
一方、絶縁薄層（２）上に形成された小信号用の導電路
（３ｂ）上にはトランジスタ、チップ抵抗、チップコン
デンサー ダイオード等の発熱を有さない複数の小信号
用素子（６）が搭載され、インバータの主回路を駆動す
べき駆動回路および保護回路が構成される。On the other hand, on the small signal conductive path (3b) formed on the insulating thin layer (2), there are a plurality of small signal elements (6) that do not generate heat, such as transistors, chip resistors, chip capacitors, diodes, etc. The drive circuit and protection circuit that drive the main circuit of the inverter are configured.
斯る本発明に依れば、金属基板上に貼着する絶縁樹脂薄
層に基板表面を露出させる孔を設け、その孔で露出され
た基板上に熱抵抗比の小さいセラミックス片を介してイ
ンバータの主回路となるパワー素子を搭載し、他の領域
上に主回路を駆動させる複数の／Ｊ％信号用素子を配置
することにより、パワー素子の熱放散性を極めて向上さ
せることができる。また、同一基板上に／Ｊ＼信号用素
子が固着できるので、その結果ハイパワー用の主回路と
駆動回路とを一体化したインバータ装置を提供すること
ができる。According to the present invention, a hole is provided in a thin insulating resin layer adhered to a metal substrate to expose the surface of the substrate, and an inverter is installed on the substrate exposed through the hole via a ceramic piece having a low thermal resistance ratio. By mounting a power element serving as a main circuit and arranging a plurality of /J% signal elements for driving the main circuit on other areas, the heat dissipation performance of the power element can be greatly improved. Furthermore, since the /J\ signal element can be fixed on the same substrate, it is possible to provide an inverter device in which a high power main circuit and a drive circuit are integrated.
（ト）発明の効果
以上に詳述した如く、本発明に依れば、同一基板上にハ
イパワー用のインバータ主回路と、その主回路を駆動さ
せる駆動回路とを形成することができることにより、極
めて薄型のハイパワー用のインバータ装置を提供するこ
とができる。(G) Effects of the Invention As detailed above, according to the present invention, a high-power inverter main circuit and a drive circuit for driving the main circuit can be formed on the same substrate. An extremely thin high power inverter device can be provided.
また、本発明で用いるセラミックス片上にはパワー素子
のみが固着されているため、安価でしかも同一基板上に
小信号用のファインパターンを形成することができる。Further, since only the power element is fixed on the ceramic piece used in the present invention, it is possible to form a fine pattern for small signals on the same substrate at low cost.
第１図は本発明の実施例を示す平面図、第２図は第１図
のＩ−Ｉ断面図、第３図は本実施例で用いるセラミック
ス片を示す断面図、第４図は従来例を示す要部断面図で
ある。
（１）・・・金属基板、 （２）・・・絶縁薄層、 （
２ａ）・・・孔、 （３）・・・導電路、 （４〉・
・・セラミックス片、（５）・・・パワー素子、 （６
）・・・小信号素子。
：Ｌ 昌 勺 の ４ のFig. 1 is a plan view showing an embodiment of the present invention, Fig. 2 is a sectional view taken along the line II in Fig. 1, Fig. 3 is a sectional view showing a ceramic piece used in this embodiment, and Fig. 4 is a conventional example. FIG. (1)...metal substrate, (2)...insulating thin layer, (
2a)...hole, (3)...conductive path, (4>・
... Ceramic piece, (5) ... Power element, (6
)...Small signal element. : L Chang's 4's
Claims (7)
数の孔が設けられた絶縁薄層と 前記絶縁薄層上に形成された所望形状の導電路と 前記孔で露出した前記基板上に固着された熱抵抗比の小
さいセラミックス片と 前記セラミックス片上に固着され前記導電路と接続され
たパワーインバータの主回路となる複数のパワー素子と 前記主回路を駆動させ且つ前記基板上に配置された駆動
回路となる複数の小信号回路素子とを具備したことを特
徴とするインバータ装置。(1) A metal substrate, an insulating thin layer attached to the substrate and provided with a plurality of holes that expose the surface of the substrate, and a conductive path of a desired shape formed on the insulating thin layer and exposed through the holes. a ceramic piece having a low thermal resistance ratio fixed on the substrate, a plurality of power elements fixed on the ceramic piece and connected to the conductive path and forming a main circuit of a power inverter, and driving the main circuit; An inverter device comprising: a plurality of small signal circuit elements serving as a drive circuit arranged above the inverter device.
数の孔が設けられた絶縁薄層と 前記絶縁薄層上に形成された所望形状の導電路と 前記孔で露出した前記基板上に固着され且つその両面に
導電層が形成された熱抵抗比の小さいセラミックス片と 前記セラミックス片上に固着され前記導電路と接続され
たパワーインバータの主回路となる複数のパワー素子と 前記主回路を駆動させ且つ前記基板上に配置された駆動
回路となる複数の小信号回路素子とを具備し、 前記セラミックス片近傍にパワー用のリード端子が接続
されるパワー用の前記導電路を延在させ、前記延在され
た導電路と前記セラミックス片上の導電層とを接続した
ことを特徴とするインバータ装置。(2) A metal substrate, an insulating thin layer attached to the substrate and provided with a plurality of holes exposing the surface of the substrate, and a conductive path of a desired shape formed on the insulating thin layer and exposed through the holes. a ceramic piece with a low thermal resistance ratio fixed on the substrate and having a conductive layer formed on both sides thereof; and a plurality of power elements fixed on the ceramic piece and connected to the conductive path and forming a main circuit of a power inverter. The conductive path for power includes a plurality of small signal circuit elements that drive the main circuit and serve as a drive circuit arranged on the substrate, and a lead terminal for power is connected near the ceramic piece. An inverter device characterized in that the extended conductive path is connected to a conductive layer on the ceramic piece.
する請求項１または２記載のインバータ装置。(3) The inverter device according to claim 1 or 2, wherein a copper substrate is used as the metal substrate.
窒化ホウ素片、炭化ケイ素片あるいはベリリア片を用い
たことを特徴とする請求項１または２記載のインバータ
装置。(4) an aluminum nitride piece made into the ceramic piece;
3. The inverter device according to claim 1, wherein a piece of boron nitride, a piece of silicon carbide, or a piece of beryllia is used.
ていることを特徴とする請求項４記載のインバータ装置
。(5) The inverter device according to claim 4, wherein conductor layers are formed on both sides of the ceramic piece.
請求項１または２記載のインバータ装置。(6) The inverter device according to claim 1 or 2, wherein copper foil is used as the conductive path.
特徴とする請求項１または２記載のインバータ装置。(7) The inverter device according to claim 1 or 2, wherein the power elements are bridge-connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1335562A JP2735912B2 (en) | 1989-12-25 | 1989-12-25 | Inverter device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1335562A JP2735912B2 (en) | 1989-12-25 | 1989-12-25 | Inverter device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03195053A true JPH03195053A (en) | 1991-08-26 |
| JP2735912B2 JP2735912B2 (en) | 1998-04-02 |
Family
ID=18289969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1335562A Expired - Lifetime JP2735912B2 (en) | 1989-12-25 | 1989-12-25 | Inverter device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2735912B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0679174U (en) * | 1993-04-09 | 1994-11-04 | 東洋電機製造株式会社 | Inverter printed wiring board |
| WO1998010508A1 (en) * | 1996-09-06 | 1998-03-12 | Hitachi, Ltd. | Semiconductor device |
| KR100419051B1 (en) * | 1999-02-25 | 2004-02-19 | 가부시끼가이샤 히다치 세이사꾸쇼 | Semiconductor device |
| JP2010068658A (en) * | 2008-09-11 | 2010-03-25 | Denso Corp | Power converter |
| JP2010193713A (en) * | 2010-05-31 | 2010-09-02 | Hitachi Automotive Systems Ltd | Power converter and moving body including power converter |
| JPWO2013179638A1 (en) * | 2012-05-29 | 2016-01-18 | 日本精工株式会社 | Semiconductor module and manufacturing method thereof |
| WO2016194033A1 (en) * | 2015-05-29 | 2016-12-08 | 新電元工業株式会社 | Semiconductor device and method for manufacturing same |
| JP6577146B1 (en) * | 2018-01-26 | 2019-09-18 | 新電元工業株式会社 | Electronic module |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5278490B2 (en) * | 2011-05-10 | 2013-09-04 | 株式会社デンソー | Power converter |
-
1989
- 1989-12-25 JP JP1335562A patent/JP2735912B2/en not_active Expired - Lifetime
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0679174U (en) * | 1993-04-09 | 1994-11-04 | 東洋電機製造株式会社 | Inverter printed wiring board |
| WO1998010508A1 (en) * | 1996-09-06 | 1998-03-12 | Hitachi, Ltd. | Semiconductor device |
| KR100419051B1 (en) * | 1999-02-25 | 2004-02-19 | 가부시끼가이샤 히다치 세이사꾸쇼 | Semiconductor device |
| JP2010068658A (en) * | 2008-09-11 | 2010-03-25 | Denso Corp | Power converter |
| JP2010193713A (en) * | 2010-05-31 | 2010-09-02 | Hitachi Automotive Systems Ltd | Power converter and moving body including power converter |
| JPWO2013179638A1 (en) * | 2012-05-29 | 2016-01-18 | 日本精工株式会社 | Semiconductor module and manufacturing method thereof |
| US9312234B2 (en) | 2012-05-29 | 2016-04-12 | Nsk Ltd. | Semiconductor module and method for manufacturing the same |
| WO2016194033A1 (en) * | 2015-05-29 | 2016-12-08 | 新電元工業株式会社 | Semiconductor device and method for manufacturing same |
| JP6062565B1 (en) * | 2015-05-29 | 2017-01-18 | 新電元工業株式会社 | Semiconductor device and manufacturing method thereof |
| US9673143B2 (en) | 2015-05-29 | 2017-06-06 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and manufacturing method of the same |
| JP6577146B1 (en) * | 2018-01-26 | 2019-09-18 | 新電元工業株式会社 | Electronic module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2735912B2 (en) | 1998-04-02 |
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