JP2521624Y2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2521624Y2
JP2521624Y2 JP1991039286U JP3928691U JP2521624Y2 JP 2521624 Y2 JP2521624 Y2 JP 2521624Y2 JP 1991039286 U JP1991039286 U JP 1991039286U JP 3928691 U JP3928691 U JP 3928691U JP 2521624 Y2 JP2521624 Y2 JP 2521624Y2
Authority
JP
Japan
Prior art keywords
semiconductor device
metal
metal plate
solder layer
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1991039286U
Other languages
Japanese (ja)
Other versions
JPH0572135U (en
Inventor
直由 尾島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP1991039286U priority Critical patent/JP2521624Y2/en
Publication of JPH0572135U publication Critical patent/JPH0572135U/en
Application granted granted Critical
Publication of JP2521624Y2 publication Critical patent/JP2521624Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】本考案は半導体装置、放熱フィン
やプリント配線板に搭載した半導体装置の構造に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device, a radiation fin or a semiconductor device mounted on a printed wiring board.

【0002】[0002]

【従来の技術】従来、ダイオード、トランジスタ等の半
導体チップを用いて半導体装置を構成する場合、例え
ば、図1の断面構造図に示すように2の金属部材、3の
金属板、1の半導体チップ及び4の接続部材を順次、載
置して、5のはんだ層により相互間を固着している。3
の金属板は支持手段、間隔保持手段、熱疲労防止手段や
放熱手段などに使用され、金属材料としてもモリブデ
ン、タングステン、銅、銀など必要に応じて、選択使用
される。
2. Description of the Related Art Conventionally, in the case of forming a semiconductor device using semiconductor chips such as diodes and transistors, for example, as shown in the sectional structural view of FIG. The connecting members 4 and 4 are sequentially placed and fixed to each other by the solder layer 5. Three
The metal plate is used as a supporting means, a spacing maintaining means, a thermal fatigue preventing means, a heat radiating means, and the like, and as a metal material, molybdenum, tungsten, copper, silver, or the like is selected and used as needed.

【0003】しかしながら、金属板3のろう付け面、す
なわち、半導体チップ1側及び金属部材2側に対向する
面が平坦であるため、次のような欠点がある。
However, since the brazing surface of the metal plate 3, that is, the surface facing the semiconductor chip 1 side and the metal member 2 side is flat, there are the following drawbacks.

【0004】金属板のはんだ付けにおいては、はんだ
のヌレ性をよくするためフラックスを与え、加熱、冷却
により固着しているが、はんだが溶融し、固化するまで
の間にフラックスがはんだ層内に残り、はんだ層内にボ
イド(空洞)を発生し易い。このようなボイドの発生は
はんだ結合を弱め、半導体装置の信頼性を悪化する。
In soldering a metal plate, a flux is applied to improve the wetting property of the solder and is fixed by heating and cooling. The remainder is apt to cause voids (cavities) in the solder layer. The generation of such voids weakens the solder bond and deteriorates the reliability of the semiconductor device.

【0005】長期冷熱サイクルの環境下において、は
んだ層の周辺厚が薄いため、熱緩衝効果が少なく、周辺
部に熱疲労現象によるクラックを発生しやすく熱疲労の
寿命が短い。
In the environment of long-term cooling / heating cycle, since the peripheral thickness of the solder layer is thin, the thermal buffering effect is small, and cracks are easily generated in the peripheral part due to the thermal fatigue phenomenon, and the life of thermal fatigue is short.

【0006】[0006]

【考案の目的】本考案は従来装置の前記欠点を解消し、
ボイドの発生率を低減し、かつ、熱疲労寿命の長い半導
体装置を提供するものである。又、放熱フィンやプリン
ト配線板に搭載した半導体装置をあわせて提供する。
The object of the present invention is to solve the above-mentioned disadvantages of the conventional device,
It is intended to provide a semiconductor device having a reduced occurrence rate of voids and a long thermal fatigue life. Further, the semiconductor device mounted on the heat radiation fin or the printed wiring board is also provided.

【0007】[0007]

【実施例】図2は本考案の実施例の断面構造図であっ
て、図1と同一符号は同一部分を示している。2の金属
部材は金属板及び半導体チップ1が収容できる凹部をも
ったアルミや銅の放熱フィンを構成する。
2 is a cross-sectional structural view of an embodiment of the present invention, in which the same symbols as in FIG. 1 indicate the same parts. The metal member 2 constitutes a heat radiating fin of aluminum or copper having a recess for accommodating the metal plate and the semiconductor chip 1.

【0008】また、金属板3は図3(a)に平面図、
(b)に側面図で示すように、凸状曲面3aを上下両面
に形成している。
The metal plate 3 is shown in a plan view in FIG.
As shown in the side view in (b), convex curved surfaces 3a are formed on both upper and lower surfaces.

【0009】製造においては、金属部材2(放熱フィ
ン)の凹部に第1のはんだチップ、金属板3、第2のは
んだチップ、半導体チップ1、第3のはんだチップ、接
続部材4を積層して収容し、加熱により、第1、第2、
第3のはんだチップを溶融し、その後の固化により、は
んだ層5を形成する。
In the manufacture, the first solder chip, the metal plate 3, the second solder chip, the semiconductor chip 1, the third solder chip, and the connecting member 4 are laminated in the recess of the metal member 2 (radiation fin). By housing and heating, the first, second,
The solder layer 5 is formed by melting the third solder chip and then solidifying it.

【0010】金属板3は上下両面に凸状曲面3aを形成
しているので、はんだの溶融から固化までの間にボイド
の要因となるフラックス等は金属板3の3aの中央部よ
り周辺部にむかって逃げやすくなり、はんだ層の固化後
のボイド発生は著しく低減する。
Since the metal plate 3 has convex curved surfaces 3a formed on both upper and lower surfaces, flux or the like which causes voids during melting and solidification of the solder from the central portion of the metal plate 3 to the peripheral portion. On the other hand, it becomes easier to escape, and the occurrence of voids after solidification of the solder layer is significantly reduced.

【0011】又、金属板3の上下両面のはんだ層5は中
央部に比し周辺部が厚くなっており、(はんだ層5の溶
融時の外周へのひろがり効果によって薄くなる部分を除
く)長時間の冷熱サイクル環境下での熱疲労現象である
はんだ層のクラック発生を図1の従来装置に比し、減少
せしむる。
The peripheral portions of the solder layers 5 on the upper and lower surfaces of the metal plate 3 are thicker than the central portion thereof (excluding the portion which is thinned by the spreading effect to the outer periphery when the solder layer 5 is melted). The occurrence of cracks in the solder layer, which is a thermal fatigue phenomenon under a low temperature thermal cycle environment, is reduced as compared with the conventional device of FIG.

【0012】又、半導体チップ1、金属板3、及び金属
部材2の順で面積を増加させることにより、放熱効果を
良好としている。
Further, the heat dissipation effect is improved by increasing the area of the semiconductor chip 1, the metal plate 3 and the metal member 2 in this order.

【0013】図2では、接続片やヘッダーリード線等の
接続部材4の半導体チップ1との接続部分に凸状曲面4
aを形成することにより、前記せる金属板3の3aと同
様の効果を生ずる。
In FIG. 2, a convex curved surface 4 is formed at a connection portion of the connection member 4 such as a connection piece or a header lead wire with the semiconductor chip 1.
By forming a, the same effect as 3a of the metal plate 3 can be obtained.

【0014】図4は本考案の他の実施例の断面図であっ
て、図1、図2、図4と同一符号は同一部分を示してい
る。2の金属部材はプリント配線板の基板6に配設した
導電層である。プリント配線板は多種多様のものがあ
り、例えばセラミック基板、アルミベース銅張板、ガラ
ス、エポキシ銅張積層板がある。本考案は、いづれのプ
リント配線板にも適用できる。又、7は基板6上に設け
た他の電子部品であり、種々の複合又は混成集積回路装
置を構成する。
FIG. 4 is a sectional view of another embodiment of the present invention, in which the same reference numerals as those in FIGS. 1, 2 and 4 designate the same parts. The second metal member is a conductive layer provided on the substrate 6 of the printed wiring board. There are various types of printed wiring boards, such as ceramic boards, aluminum-based copper clad boards, glass, and epoxy copper clad laminated boards. The present invention can be applied to any printed wiring board. Further, 7 is another electronic component provided on the substrate 6, which constitutes various composite or hybrid integrated circuit devices.

【0015】図4の実施例においても、図2の実施例で
説明したと同様の作用、効果を示す。
The embodiment of FIG. 4 also exhibits the same operation and effect as described in the embodiment of FIG.

【0016】本考案の実施例において、説明した形状、
材料等は本考案の要旨の範囲で変形、変換、付加、削除
等の変更をなし得るものである。例えば、金属板3は
銅、モリブデン、タングステンなど必要に応じて選択し
得る。
In the embodiment of the present invention, the shape described above,
The materials and the like can be modified, changed, added, deleted, and changed within the scope of the present invention. For example, the metal plate 3 can be selected from copper, molybdenum, tungsten, etc. according to need.

【0017】[0017]

【考案の効果】以上、説明したように本考案の半導体装
置は、はんだ層内のボイドを低減し、かつ、はんだ層の
熱疲労性能の向上を可能とし、放熱フィンやプリント配
線板に搭載した半導体装置として有効であり、電装品を
はじめ、高信頼性を要求される各種の電気機器に利用し
て実用上の効果大なるものである。
As described above, the semiconductor device of the present invention is capable of reducing voids in the solder layer and improving the thermal fatigue performance of the solder layer, and is mounted on a radiation fin or a printed wiring board. The semiconductor device is effective as a semiconductor device, and has a great practical effect when used in various electrical devices that require high reliability such as electrical components.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の半導体装置の断面構造図FIG. 1 is a sectional structural view of a conventional semiconductor device.

【図2】本考案の実施例を示す断面構造図FIG. 2 is a sectional view showing an embodiment of the present invention.

【図3】図2に用いる金属板の構造図であり、(a)は
平面図、(b)は側面図
3A and 3B are structural views of the metal plate used in FIG. 2, where FIG. 3A is a plan view and FIG. 3B is a side view.

【図4】本考案の他の実施例を示す断面構造図FIG. 4 is a sectional structural view showing another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 金属部材 3 金属板 3a 金属板の凸状曲面 4 接続部材 4a 接続部材の凸状曲面 5 はんだ層 6 基板 7 他の電子部品 1 Semiconductor Chip 2 Metal Member 3 Metal Plate 3a Convex Curved Surface of Metal Plate 4 Connection Member 4a Convex Curved Surface of Connection Member 5 Solder Layer 6 Board 7 Other Electronic Components

Claims (4)

(57)【実用新案登録請求の範囲】(57) [Scope of utility model registration request] 【請求項1】 凸状曲面を上下両面に形成した金属板の
一面に半導体チップを、又、他面に金属部材をそれぞれ
はんだ層を介して固着し、それらは半導体チップ、金属
板、金属部材の順に面積を増加させ、かつ、前記はんだ
層の厚さを凸状曲面の中央部に比し、周辺部に大なる部
分をもたせることを特徴とする半導体装置。
1. A semiconductor chip is fixed to one surface of a metal plate having convex and curved surfaces formed on the upper and lower surfaces, respectively, and a metal member is fixed to the other surface via a solder layer, which are a semiconductor chip, a metal plate, and a metal member. The semiconductor device is characterized in that the area is increased in the order of, and the thickness of the solder layer is larger in the peripheral portion than in the central portion of the convex curved surface.
【請求項2】 金属部材を金属放熱フィンとした請求項
1の半導体装置。
2. The semiconductor device according to claim 1, wherein the metal member is a metal radiation fin.
【請求項3】 金属部材をプリント配線板上の金属層と
した請求項1の半導体装置。
3. The semiconductor device according to claim 1, wherein the metal member is a metal layer on a printed wiring board.
【請求項4】 金属板とはんだ付けした面と反対側の半
導体チップの面に接続部材の凸状曲面をはんだ付けした
請求項1、請求項2、又は請求項3の半導体装置。
4. The semiconductor device according to claim 1, 2 or 3, wherein a convex curved surface of the connecting member is soldered to the surface of the semiconductor chip opposite to the surface soldered to the metal plate.
JP1991039286U 1991-03-07 1991-03-07 Semiconductor device Expired - Fee Related JP2521624Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1991039286U JP2521624Y2 (en) 1991-03-07 1991-03-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1991039286U JP2521624Y2 (en) 1991-03-07 1991-03-07 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0572135U JPH0572135U (en) 1993-09-28
JP2521624Y2 true JP2521624Y2 (en) 1996-12-25

Family

ID=12548918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1991039286U Expired - Fee Related JP2521624Y2 (en) 1991-03-07 1991-03-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2521624Y2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6504962B2 (en) * 2015-08-04 2019-04-24 三菱電機株式会社 Power semiconductor device
JP2016105508A (en) * 2016-02-29 2016-06-09 株式会社三社電機製作所 Semiconductor device

Also Published As

Publication number Publication date
JPH0572135U (en) 1993-09-28

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