JPH0572135U - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0572135U
JPH0572135U JP039286U JP3928691U JPH0572135U JP H0572135 U JPH0572135 U JP H0572135U JP 039286 U JP039286 U JP 039286U JP 3928691 U JP3928691 U JP 3928691U JP H0572135 U JPH0572135 U JP H0572135U
Authority
JP
Japan
Prior art keywords
semiconductor device
metal plate
metal
solder layer
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP039286U
Other languages
Japanese (ja)
Other versions
JP2521624Y2 (en
Inventor
直由 尾島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP1991039286U priority Critical patent/JP2521624Y2/en
Publication of JPH0572135U publication Critical patent/JPH0572135U/en
Application granted granted Critical
Publication of JP2521624Y2 publication Critical patent/JP2521624Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】 (修正有) 【目的】 本考案は半導体チップ、金属板、金属部材を
固着するはんだ層内のボイド発生率を低減し、熱疲労性
能の向上を図った半導体装置、及び、放熱フィンやプリ
ント配線板と結合した半導体装置を提供するものであ
る。 【構成】 凸状曲面を上下両面に形成した金属板3の一
面に半導体チップ1を、又、他面に金属部材2をそれぞ
れ、はんだ層5を介して固着したもので、はんだ層5の
厚さを凸状曲面3a,4aの中央部に比し、周辺部を大
とする。
(57) [Summary] (Modified) [Objective] The present invention aims to reduce the occurrence rate of voids in a semiconductor chip, a metal plate, and a solder layer for fixing a metal member, and improve the thermal fatigue performance of a semiconductor device. The present invention provides a semiconductor device combined with a radiation fin or a printed wiring board. [Structure] A semiconductor chip 1 is fixed to one surface of a metal plate 3 having convex and curved surfaces formed on the upper and lower surfaces, and a metal member 2 is fixed to the other surface via a solder layer 5, and the thickness of the solder layer 5 is The height is made larger in the peripheral portions than in the central portions of the convex curved surfaces 3a, 4a.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は半導体装置、放熱フィンやプリント配線板に搭載した半導体装置の構造 に関するものである。 The present invention relates to the structure of a semiconductor device, a radiation fin, and a semiconductor device mounted on a printed wiring board.

【0002】[0002]

【従来の技術】[Prior Art]

従来、ダイオード、トランジスタ等の半導体チップを用いて半導体装置を構成す る場合、例えば、図1の断面構造図に示すように2の金属部材、3の金属板、1 の半導体チップ及び4の接続部材を順次、載置して、5のはんだ層により相互間 を固着している。3の金属板は支持手段、間隔保持手段、熱疲労防止手段や放熱 手段などに使用され、金属材料としてもモリブデン、タングステン、銅、銀など 必要に応じて、選択使用される。 Conventionally, when a semiconductor device is configured using semiconductor chips such as diodes and transistors, for example, as shown in the cross-sectional structure diagram of FIG. 1, metal members 2 and metal plates 3 and semiconductor chips 1 and 4 are connected. The members are placed one after another and fixed to each other by 5 solder layers. The metal plate of No. 3 is used for supporting means, spacing maintaining means, thermal fatigue preventing means, heat radiating means, etc. As the metal material, molybdenum, tungsten, copper, silver or the like is selected and used as required.

【0003】 しかしながら、金属板3のろう付け面、すなわち、半導体チップ1側及び金属部 材2側に対向する面が平坦であるため、次のような欠点がある。However, since the brazing surface of the metal plate 3, that is, the surface facing the semiconductor chip 1 side and the metal member 2 side is flat, there are the following drawbacks.

【0004】 金属板のはんだ付けにおいては、はんだのヌレ性をよくするためフラックスを 与え、加熱、冷却により固着しているが、はんだが溶融し、固化するまでの間に フラックスがはんだ層内に残り、はんだ層内にボイド(空洞)を発生し易い。こ のようなボイドの発生ははんだ結合を弱め、半導体装置の信頼性を悪化する。In soldering a metal plate, a flux is applied to improve the wetting property of the solder, and the flux is fixed by heating and cooling. However, until the solder is melted and solidified, the flux is dispersed in the solder layer. Remaining, voids (cavities) are likely to occur in the solder layer. The generation of such voids weakens the solder bond and deteriorates the reliability of the semiconductor device.

【0005】 長期冷熱サイクルの環境下において、はんだ層の周辺厚が薄いため、熱緩衝効 果が少なく、周辺部に熱疲労現象によるクラックを発生しやすく熱疲労の寿命が 短い。Under the environment of long-term cooling / heating cycle, since the peripheral thickness of the solder layer is thin, the thermal buffering effect is small, and cracks are easily generated in the peripheral portion due to the thermal fatigue phenomenon, and the thermal fatigue life is short.

【0006】[0006]

【考案の目的】[The purpose of the device]

本考案は従来装置の前記欠点を解消し、ボイドの発生率を低減し、かつ、熱疲労 寿命の長い半導体装置を提供するものである。又、放熱フィンやプリント配線板 に搭載した半導体装置をあわせて提供する。 The present invention solves the above-mentioned drawbacks of the conventional device, provides a semiconductor device having a reduced occurrence rate of voids and a long thermal fatigue life. We also provide semiconductor devices mounted on heat dissipation fins and printed wiring boards.

【0007】[0007]

【実施例】【Example】

図2は本考案の実施例の断面構造図であって、図1と同一符号は同一部分を示し ている。2の金属部材は金属板及び半導体チップ1が収容できる凹部をもったア ルミや銅の放熱フィンを構成する。 FIG. 2 is a sectional structural view of an embodiment of the present invention, in which the same symbols as in FIG. 1 indicate the same parts. The metal member 2 constitutes an aluminum or copper radiating fin having a recess for accommodating the metal plate and the semiconductor chip 1.

【0008】 また、金属板3は図3(a)に平面図、(b)に側面図で示すように、凸状曲面 3aを上下両面に形成している。Further, as shown in a plan view of FIG. 3A and a side view of FIG. 3B, the metal plate 3 has convex curved surfaces 3 a formed on both upper and lower surfaces.

【0009】 製造においては、金属部材2(放熱フィン)の凹部に第1のはんだチップ、金属 板3、第2のはんだチップ、半導体チップ1、第3のはんだチップ、接続部材4 を積層して収容し、加熱により、第1、第2、第3のはんだチップを溶融し、そ の後の固化により、はんだ層5を形成する。In the manufacture, the first solder chip, the metal plate 3, the second solder chip, the semiconductor chip 1, the third solder chip, and the connecting member 4 are laminated in the concave portion of the metal member 2 (radiation fin). The first, second, and third solder chips are melted by housing and heating, and the solder layer 5 is formed by subsequent solidification.

【0010】 金属板3は上下両面に凸状曲面3aを形成しているので、はんだの溶融から固化 までの間にボイドの要因となるフラックス等は金属板3の3aの中央部より周辺 部にむかって逃げやすくなり、はんだ層の固化後のボイド発生は著しく低減する 。Since the metal plate 3 has convex curved surfaces 3a formed on both upper and lower surfaces, flux or the like which causes voids from the melting to solidification of the solder is generated in the peripheral portion from the central portion of the metal plate 3a. On the other hand, it becomes easier to escape, and the occurrence of voids after solidification of the solder layer is significantly reduced.

【0011】 又、金属板3の上下両面のはんだ層5は中央部に比し周辺部が厚くなっており、 (はんだ層5の溶融時の外周へのひろがり効果によって薄くなる部分を除く)長 時間の冷熱サイクル環境下での熱疲労現象であるはんだ層のクラック発生を図1 の従来装置に比し、減少せしむる。Further, the solder layers 5 on the upper and lower surfaces of the metal plate 3 are thicker in the peripheral portion than in the central portion (excluding the portion which is thinned by the spreading effect to the outer periphery when the solder layer 5 is melted). The occurrence of cracks in the solder layer, which is a phenomenon of thermal fatigue under a long-term thermal cycle environment, is reduced as compared with the conventional device of FIG.

【0012】 又、半導体チップ1、金属板3、及び金属部材2の順で面積を増加させることに より、放熱効果を良好としている。Further, the heat dissipation effect is improved by increasing the area of the semiconductor chip 1, the metal plate 3, and the metal member 2 in this order.

【0013】 図2では、接続片やヘッダーリード線等の接続部材4の半導体チップ1との接続 部分に凸状曲面4aを形成することにより、前記せる金属板3の3aと同様の効 果を生ずる。In FIG. 2, a convex curved surface 4a is formed at a connection portion of the connection member 4 such as a connection piece or a header lead wire with the semiconductor chip 1, so that the same effect as that of the metal plate 3a can be obtained. Occurs.

【0014】 図4は本考案の他の実施例の断面図であって、図1、図2、図4と同一符号は同 一部分を示している。2の金属部材はプリント配線板の基板6に配設した導電層 である。プリント配線板は多種多様のものがあり、例えばセラミック基板、アル ミベース銅張板、ガラス、エポキシ銅張積層板がある。本考案は、いづれのプリ ント配線板にも適用できる。又、7は基板6上に設けた他の電子部品であり、種 々の複合又は混成集積回路装置を構成する。FIG. 4 is a sectional view of another embodiment of the present invention, in which the same reference numerals as those in FIGS. 1, 2 and 4 denote the same parts. The second metal member is a conductive layer disposed on the substrate 6 of the printed wiring board. There are various types of printed wiring boards, such as ceramic substrates, aluminum base copper clad boards, glass, and epoxy copper clad laminates. The present invention can be applied to any printed wiring board. Reference numeral 7 is another electronic component provided on the substrate 6, which constitutes various composite or hybrid integrated circuit devices.

【0015】 図4の実施例においても、図2の実施例で説明したと同様の作用、効果を示す。The embodiment shown in FIG. 4 also exhibits the same operation and effect as described in the embodiment shown in FIG.

【0016】 本考案の実施例において、説明した形状、材料等は本考案の要旨の範囲で変形、 変換、付加、削除等の変更をなし得るものである。例えば、金属板3は銅、モリ ブデン、タングステンなど必要に応じて選択し得る。In the embodiments of the present invention, the shapes, materials and the like described can be modified, changed, added, deleted and changed within the scope of the present invention. For example, the metal plate 3 can be selected from copper, molybdenum, tungsten, etc. according to need.

【0017】[0017]

【考案の効果】[Effect of the device]

以上、説明したように本考案の半導体装置は、はんだ層内のボイドを低減し、か つ、はんだ層の熱疲労性能の向上を可能とし、放熱フィンやプリント配線板に搭 載した半導体装置として有効であり、電装品をはじめ、高信頼性を要求される各 種の電気機器に利用して実用上の効果大なるものである。 As described above, the semiconductor device of the present invention can reduce voids in the solder layer and improve the thermal fatigue performance of the solder layer, and can be used as a semiconductor device mounted on a radiation fin or a printed wiring board. It is effective and has a great practical effect when it is used in electrical equipment and various types of electrical equipment that require high reliability.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の半導体装置の断面構造図FIG. 1 is a cross-sectional structure diagram of a conventional semiconductor device.

【図2】本考案の実施例を示す断面構造図FIG. 2 is a sectional structural view showing an embodiment of the present invention.

【図3】図2に用いる金属板の構造図であり、(a)は
平面図、(b)は側面図
3A and 3B are structural views of the metal plate used in FIG. 2, where FIG. 3A is a plan view and FIG. 3B is a side view.

【図4】本考案の他の実施例を示す断面構造図FIG. 4 is a sectional structural view showing another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 金属部材 3 金属板 3a 金属板の凸状曲面 4 接続部材 4a 接続部材の凸状曲面 5 はんだ層 6 基板 7 他の電子部品 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Metal member 3 Metal plate 3a Convex curved surface of metal plate 4 Connecting member 4a Convex curved surface of connecting member 5 Solder layer 6 Board 7 Other electronic components

Claims (4)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 凸状曲面を上下両面に形成した金属板の
一面に半導体チップを、又、他面に金属部材をそれぞれ
はんだ層を介して固着し、それらは半導体チップ、金属
板、金属部材の順に面積を増加させ、かつ、前記はんだ
層の厚さを凸状曲面の中央部に比し、周辺部に大なる部
分をもたせることを特徴とする半導体装置。
1. A semiconductor chip is fixed to one surface of a metal plate having convex and curved surfaces formed on both upper and lower surfaces, and a metal member is fixed to the other surface via solder layers, which are a semiconductor chip, a metal plate, and a metal member. The semiconductor device is characterized in that the area is increased in this order, and the thickness of the solder layer is larger in the peripheral portion than in the central portion of the convex curved surface.
【請求項2】 金属部材を金属放熱フィンとした請求項
1の半導体装置。
2. The semiconductor device according to claim 1, wherein the metal member is a metal radiation fin.
【請求項3】 金属部材をプリント配線板上の金属層と
した請求項1の半導体装置。
3. The semiconductor device according to claim 1, wherein the metal member is a metal layer on a printed wiring board.
【請求項4】 金属板とはんだ付けした面と反対側の半
導体チップの面に接続部材の凸状曲面をはんだ付けした
請求項1、請求項2、又は請求項3の半導体装置。
4. The semiconductor device according to claim 1, wherein the convex curved surface of the connecting member is soldered to the surface of the semiconductor chip opposite to the surface soldered to the metal plate.
JP1991039286U 1991-03-07 1991-03-07 Semiconductor device Expired - Fee Related JP2521624Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1991039286U JP2521624Y2 (en) 1991-03-07 1991-03-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1991039286U JP2521624Y2 (en) 1991-03-07 1991-03-07 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0572135U true JPH0572135U (en) 1993-09-28
JP2521624Y2 JP2521624Y2 (en) 1996-12-25

Family

ID=12548918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1991039286U Expired - Fee Related JP2521624Y2 (en) 1991-03-07 1991-03-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2521624Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016105508A (en) * 2016-02-29 2016-06-09 株式会社三社電機製作所 Semiconductor device
JP2017034152A (en) * 2015-08-04 2017-02-09 三菱電機株式会社 Power semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017034152A (en) * 2015-08-04 2017-02-09 三菱電機株式会社 Power semiconductor device
JP2016105508A (en) * 2016-02-29 2016-06-09 株式会社三社電機製作所 Semiconductor device

Also Published As

Publication number Publication date
JP2521624Y2 (en) 1996-12-25

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