JP2841945B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2841945B2 JP2841945B2 JP3209677A JP20967791A JP2841945B2 JP 2841945 B2 JP2841945 B2 JP 2841945B2 JP 3209677 A JP3209677 A JP 3209677A JP 20967791 A JP20967791 A JP 20967791A JP 2841945 B2 JP2841945 B2 JP 2841945B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- conductive plate
- pad
- heat
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に係わり、
特に半導体チップの放熱構造に関する。アルミナ等のセ
ラミック基板に形成する導体パターンはその幅が、小さ
くとも100μm であるのに対して、ポリイミド系樹脂よ
りなる多層樹脂基板には、パターン幅が20μm と微細パ
ターンを形成することができる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a heat dissipation structure of a semiconductor chip. A conductor pattern formed on a ceramic substrate such as alumina has a width of at least 100 μm, while a multilayer resin substrate made of a polyimide resin can form a fine pattern with a pattern width of 20 μm.
【０００２】したがって、半導体チップの高密度実装
化，信号の高速化に伴い、近年の半導体装置に用いる回
路基板は、積層印刷配線板或いはセラミック基板を単独
に用いずに、アルミナ等のセラミック基板と、セラミッ
ク基板の表面に形成したポリイミド等の低誘電率樹脂層
と導体パターンとを交互に形成した多層樹脂基板と、よ
りなる複合の回路基板が用いられている。Therefore, with the high-density mounting of semiconductor chips and the increase in the speed of signals, circuit boards used in recent semiconductor devices have been replaced with ceramic substrates made of alumina or the like instead of using laminated printed wiring boards or ceramic substrates alone. A composite circuit board composed of a low-permittivity resin layer made of polyimide or the like formed on the surface of a ceramic substrate and a multilayer resin substrate formed alternately with conductor patterns has been used.
【０００３】[0003]
【従来の技術】図３は従来の半導体装置の要所断面図で
あり、図４は他の従来例の要所断面図である。2. Description of the Related Art FIG. 3 is a sectional view of a principal part of a conventional semiconductor device, and FIG. 4 is a sectional view of a principal part of another conventional example.
【０００４】図３において、半導体チップ５をフェース
アップに搭載する回路基板１は、アルミナ等よりなるセ
ラミック基板２と、セラミック基板２の表面にポリイミ
ド等の低誘電率樹脂層31と導体パターン32とを交互に形
成した多層樹脂基板３とで、構成されている。In FIG. 3, a circuit board 1 on which a semiconductor chip 5 is mounted face up includes a ceramic substrate 2 made of alumina or the like, a low dielectric constant resin layer 31 made of polyimide or the like and a conductor pattern 32 on the surface of the ceramic substrate 2. And the multilayer resin substrate 3 formed alternately.
【０００５】セラミック基板２は１mm〜2mm の厚さで、
内部に厚膜よりなる電源パターン21等が形成され、多層
樹脂基板３は、100 μm 〜150 μm の厚さで、内部に多
層に信号パターン等の薄膜よりなる導体パターン32が形
成されている。The ceramic substrate 2 has a thickness of 1 to 2 mm.
A power supply pattern 21 and the like made of a thick film are formed inside, and the multilayer resin substrate 3 has a thickness of 100 μm to 150 μm, and a conductive pattern 32 made of a thin film such as a signal pattern is formed in multiple layers inside.
【０００６】また、多層樹脂基板３の表面には、角形の
ダイボンディング用パッド６と、ダイボンディング用パ
ッド６の各辺に平行に配列したアウタリードボンディン
グ用のパッド７とが形成されている。On the surface of the multilayer resin substrate 3 are formed square die bonding pads 6 and outer lead bonding pads 7 arranged in parallel with each side of the die bonding pads 6.
【０００７】なお、信号用のパッド７は、ビヤを介し
て、多層樹脂基板３の導体パターン32に接続されてい
る。半導体チップ５は、ダイボンディング用パッド６上
に導電性接着剤を用いてフェースアップにダイボンディ
ングし、半導体チップ５の電極を対応するパッド７に、
テープキャリア（図示省略）のリード或いは金線等のワ
イヤを介してボンディングしている。The signal pad 7 is connected to the conductor pattern 32 of the multilayer resin substrate 3 via a via. The semiconductor chip 5 is face-up die-bonded on the die bonding pad 6 using a conductive adhesive, and the electrodes of the semiconductor chip 5 are connected to the corresponding pads 7.
Bonding is performed via a lead of a tape carrier (not shown) or a wire such as a gold wire.
【０００８】図４においては、セラミック基板２の表面
に、角形のダイボンディング用パッド６を設け、多層樹
脂基板３にはこのダイボンディング用パッド６に対応す
る部分に半導体チップ５の平面視形状に相似でそれより
も大きい角形孔９を設けている。In FIG. 4, a square die bonding pad 6 is provided on the surface of the ceramic substrate 2, and a portion corresponding to the die bonding pad 6 is formed on the multilayer resin substrate 3 in a plan view shape of the semiconductor chip 5. A similar and larger square hole 9 is provided.
【０００９】そして、角形孔９内に半導体チップ５を挿
入して、ダイボンディング用パッド６上に導電性接着剤
を用いてフェースアップにダイボンディングし、一方、
半導体チップ５の電極は、多層樹脂基板３の表面の角形
孔９の周辺に配列したパッド７に接続している。Then, the semiconductor chip 5 is inserted into the square hole 9 and die-bonded face-up on the die bonding pad 6 using a conductive adhesive.
The electrodes of the semiconductor chip 5 are connected to pads 7 arranged around the rectangular holes 9 on the surface of the multilayer resin substrate 3.
【００１０】一方、ポリイミド樹脂の樹脂層は熱伝導率
が 0.2Ｗ／ｍ・Ｋと非常に小さいが、アルミナの熱伝導
率は、20Ｗ／ｍ・Ｋと大きい。したがって、図４に図示
したものは、上述のようにセラミック基板上に直接半導
体チップ５をダイボンディングすることで、半導体チッ
プ５の熱をセラミック基板２に伝達させ、セラミック基
板２の底面より発散することで、半導体チップの放熱性
の向上をはかったもので、図３に示したものよりも放熱
性が良い。On the other hand, the polyimide resin layer has a very low thermal conductivity of 0.2 W / m · K, whereas the alumina has a high thermal conductivity of 20 W / m · K. Therefore, in the device shown in FIG. 4, the heat of the semiconductor chip 5 is transmitted to the ceramic substrate 2 by die bonding the semiconductor chip 5 directly on the ceramic substrate as described above, and the heat is radiated from the bottom surface of the ceramic substrate 2. Thus, the heat dissipation of the semiconductor chip is improved, and the heat dissipation is better than that shown in FIG.
【００１１】また、図４に示すセラミック基板２の電源
パターン21はビヤ22を介して、ダイボンディング用パッ
ド６に接続している。即ち、半導体チップ５に背面電位
を供給する回路基板である。A power supply pattern 21 of the ceramic substrate 2 shown in FIG. 4 is connected to a die bonding pad 6 via a via 22. That is, it is a circuit board that supplies the back potential to the semiconductor chip 5.
【００１２】[0012]
【発明が解決しようとする課題】ところで前者、即ち多
層樹脂基板に半導体チップをダイボンディングしたもの
は、高密度実装化，信号の高速化には最適であるが、前
述のようにポリイミド樹脂の熱伝導率が極端に小さいの
で、半導体チップの放熱性が悪いという問題点があっ
た。The former, ie, a semiconductor chip die-bonded to a multi-layer resin substrate is most suitable for high-density packaging and high-speed signal transmission. Since the conductivity is extremely small, there is a problem that the heat dissipation of the semiconductor chip is poor.
【００１３】一方後者、即ち、多層樹脂基板に角形孔を
設け、半導体チップをセラミック基板にダイボンディン
グしたものは、ある程度の放熱性の改善はみられるもの
の、セラミック基板の裏面が金属ケース等に密着してい
ないと、その放熱効果はあまり期待できない。On the other hand, in the latter case, that is, in the case where a square hole is formed in a multilayer resin substrate and a semiconductor chip is die-bonded to a ceramic substrate, the heat dissipation is improved to some extent, but the back surface of the ceramic substrate is closely attached to a metal case or the like. Otherwise, the heat radiation effect cannot be expected much.
【００１４】また、後者は、多層樹脂基板に角形孔を設
けたことにより、多層樹脂基板の配線領域が減少すると
いう問題点があった。本発明はこのような点に鑑みて創
作されたもので、高密度実装化，信号の高速化が推進さ
れ、且つ半導体チップの放熱性が良好な半導体装置を、
提供することを目的としている。Further, the latter has a problem that the wiring area of the multilayer resin substrate is reduced by providing the rectangular holes in the multilayer resin substrate. The present invention has been made in view of the above points, and a semiconductor device having high density mounting, high signal speed, and good heat dissipation of a semiconductor chip has been developed.
It is intended to provide.
【００１５】[0015]
【課題を解決するための手段】上記の目的を達成するた
めに本発明は、図１に例示したように、半導体チップ５
をフェースアップに搭載する回路基板１は、セラミック
基板２と、セラミック基板２の表面にポリイミド樹脂等
の低誘電率樹脂層31と導体パターン32とを交互に形成し
た多層樹脂基板３との複合の基板構成とする。In order to achieve the above-mentioned object, the present invention relates to a semiconductor chip, as shown in FIG.
Is mounted on a ceramic substrate 2 and a multilayer resin substrate 3 in which low dielectric constant resin layers 31 such as polyimide resin and conductive patterns 32 are alternately formed on the surface of the ceramic substrate 2. Substrate configuration.
【００１６】中央角形部8Aの周辺を枠形に取り囲む短冊
形の窓8Bを有する角形の熱伝導板用パッド８と、窓8B内
に配列したアウタリードボンディング用のパッド７と
を、多層樹脂基板３の表面に形成する。A square heat conduction plate pad 8 having a rectangular window 8B surrounding the central square portion 8A in a frame shape and an outer lead bonding pad 7 arranged in the window 8B are formed by a multilayer resin substrate. 3 is formed on the surface.
【００１７】また、熱伝導板用パッド８の窓8Bにほぼ等
しい形状の短冊形の窓41を有する角形の熱伝導板40を、
熱伝導板用パッド８上に貼着する。そして、熱伝導板40
の中央角形部40A 上に半導体チップ５をダイボンディン
グし、周辺部に枠形の放熱体50を搭載した構成とする。A rectangular heat conductive plate 40 having a rectangular window 41 having a shape substantially equal to the window 8B of the heat conductive plate pad 8 is provided.
It is stuck on the heat conductive plate pad 8. And heat conduction plate 40
The semiconductor chip 5 is die-bonded on the central square portion 40A, and a frame-shaped radiator 50 is mounted on the peripheral portion.
【００１８】また、多層樹脂基板３の表面に形成した熱
伝導板用パッド８の中央角形部8Aを、ビヤ22を介してセ
ラミック基板２内に設けた電源パターン21に接続した構
成とする。Further, the central rectangular portion 8A of the heat conductive plate pad 8 formed on the surface of the multilayer resin substrate 3 is connected to a power supply pattern 21 provided in the ceramic substrate 2 via a via 22.
【００１９】一方、図２に例示したように、前述の放熱
体50に代わり、半導体チップ５を封止する箱形のケース
60を、熱伝導板40の周辺部に搭載した構成とする。On the other hand, as illustrated in FIG. 2, a box-shaped case for sealing the semiconductor chip 5 is used instead of the heat radiator 50 described above.
60 is mounted on the periphery of the heat conductive plate 40.
【００２０】[0020]
【作用】上述のように多層樹脂基板の表面に、アウタリ
ードボンディング用のパッドを配列する窓を有する熱伝
導板用パッドを設け、この上に熱伝導板を貼着し、さら
にこの熱伝導板の中央角形部に半導体チップをダイボン
ディングするとともに、周辺部に枠形の放熱体を搭載し
ている。As described above, a pad for a heat conductive plate having a window for arranging pads for outer lead bonding is provided on the surface of the multilayer resin substrate, and the heat conductive plate is adhered on the pad. The semiconductor chip is die-bonded to the central square portion of the substrate, and a frame-shaped radiator is mounted at the peripheral portion.
【００２１】したがって、半導体チップの熱は熱伝導板
を介して、放熱面積が大きい放熱体に伝達され、放熱体
から空気中に放出されるので半導体チップの放熱性が著
しく向上する。Therefore, the heat of the semiconductor chip is transmitted to the heat radiator having a large heat radiating area through the heat conductive plate and is released from the heat radiator into the air, so that the heat radiating property of the semiconductor chip is remarkably improved.
【００２２】一方、熱伝導板に窓を設け、多層樹脂基板
の表面に並列したパッドが裸出するようにしているの
で、半導体チップの電極とパッドとをボンディングする
のに何らの支障がない。On the other hand, since windows are provided in the heat conductive plate so that the pads arranged in parallel on the surface of the multilayer resin substrate are exposed, there is no problem in bonding the electrodes of the semiconductor chip to the pads.
【００２３】また、セラミック基板の表面の全面に多層
樹脂基板を形成し、その多層樹脂基板に信号パターン等
の導体パターンを形成しているので、配線領域が広く、
且つ高密度実装化，信号の高速化に適している。Further, since a multilayer resin substrate is formed on the entire surface of the ceramic substrate and a conductor pattern such as a signal pattern is formed on the multilayer resin substrate, the wiring area is large.
It is suitable for high-density mounting and high-speed signal transmission.
【００２４】また、セラミック基板の厚膜の電源パター
ンと熱伝導板用パッドとをビヤで接続することで、電圧
降下することなく十分の背面電圧を半導体チップに供給
することができる。Further, by connecting the thick power supply pattern of the ceramic substrate to the pad for the heat conductive plate with a via, a sufficient back voltage can be supplied to the semiconductor chip without voltage drop.
【００２５】さらにまた、放熱体を箱形のケースとし
て、半導体チップの封止ケースを兼ねることにより、半
導体チップを樹脂封止する等の必要がなくなり半導体装
置がそれだけ低コストとなる。Furthermore, since the heat radiator is a box-shaped case and also serves as a semiconductor chip sealing case, it is not necessary to seal the semiconductor chip with a resin or the like, thereby reducing the cost of the semiconductor device.
【００２６】[0026]
【実施例】以下図を参照しながら、本発明を具体的に説
明する。なお、全図を通じて同一符号は同一対象物を示
す。BRIEF DESCRIPTION OF THE DRAWINGS FIG. The same reference numerals indicate the same objects throughout the drawings.
【００２７】図１は本発明の実施例の図で、(A) は断面
図、(B) は熱伝導板の平面図、図２は本発明の他の実施
例の断面図である。図１において、半導体チップ５をフ
ェースアップに搭載する回路基板１は、アルミナ等より
なる１mm〜2mm の厚のセラミック基板２と、セラミック
基板２の表面にポリイミド等の低誘電率樹脂層31と導体
パターン32とを交互に形成した100μm 〜150 μm の厚
の多層樹脂基板３と、よりなる複合構成の基板である。FIG. 1 is a view of an embodiment of the present invention, in which (A) is a sectional view, (B) is a plan view of a heat conducting plate, and FIG. 2 is a sectional view of another embodiment of the present invention. In FIG. 1, a circuit board 1 on which a semiconductor chip 5 is mounted face-up includes a ceramic substrate 2 made of alumina or the like and having a thickness of 1 mm to 2 mm, a low dielectric constant resin layer 31 of polyimide or the like on the surface of the ceramic substrate 2 and a conductor. This is a substrate having a composite structure including a multilayer resin substrate 3 having a thickness of 100 μm to 150 μm in which patterns 32 are alternately formed.
【００２８】セラミック基板２には、厚膜よりなる電源
パターン21等が形成され、多層樹脂基板３には、信号パ
ターン等の薄膜よりなる導体パターン32が多層に形成さ
れている。A power supply pattern 21 and the like made of a thick film are formed on the ceramic substrate 2, and a conductor pattern 32 made of a thin film such as a signal pattern is formed on the multilayer resin substrate 3 in multiple layers.
【００２９】多層樹脂基板３の表面には、中央角形部8A
の周辺を枠形に取り囲む短冊形の窓8Bを有する角形の熱
伝導板用パッド８と、窓8B内に配列したアウタリードボ
ンディング用のパッド７とを、形成している。On the surface of the multilayer resin substrate 3, a central square portion 8A
A rectangular heat conduction plate pad 8 having a rectangular window 8B surrounding the periphery of the frame 8 in a frame shape, and an outer lead bonding pad 7 arranged in the window 8B are formed.
【００３０】また、セラミック基板２の電源パターン21
は多層樹脂基板３を貫通する所望数のビヤ22（図では１
個のみ表示している）を設けて、熱伝導板用パッド８の
中央角形部8Aに接続し、熱伝導板用パッド８の中央角形
部8A，後述する熱伝導板40の中央角形部40A を経て、半
導体チップ５に背面電圧を供給するようにしている。The power supply pattern 21 of the ceramic substrate 2
Is a desired number of vias 22 penetrating the multilayer resin substrate 3 (1 in FIG.
Are connected to the central square portion 8A of the heat conductive plate pad 8, and the central rectangular portion 8A of the heat conductive plate pad 8 and the central square portion 40A of the heat conductive plate 40 described later are connected. After that, the back voltage is supplied to the semiconductor chip 5.
【００３１】信号用のパッド７は、ビヤを介して、多層
樹脂基板３の導体パターン32に接続されている。40は、
厚さが 0.4ｍｍ前後の銅箔よりなる熱伝導板である。熱
伝導板40は熱伝導板用パッド８の外形にほぼ等しい角形
で、熱伝導板用パッド８の窓8Bに対応した位置に、短冊
形の窓41を有する。The signal pad 7 is connected to the conductor pattern 32 of the multilayer resin substrate 3 via a via. 40 is
This is a heat conductive plate made of copper foil with a thickness of about 0.4 mm. The heat conductive plate 40 has a rectangular shape substantially equal to the outer shape of the heat conductive plate pad 8, and has a rectangular window 41 at a position corresponding to the window 8B of the heat conductive plate pad 8.
【００３２】この熱伝導板用パッド８の表面に導電性接
着剤を塗布し、熱伝導板40を位置合わせし、熱伝導板40
を熱伝導板用パッド８に重畳して貼着している。半導体
チップ５は、熱伝導板40の表面の中央角形部40A 上に半
田付け等して、フェースアップにダイボンディングし、
半導体チップ５の電極を窓41内に裸出したパッド７に、
テープキャリア（図示省略）のリード或いは金線等のワ
イヤを介してボンディングしている。A conductive adhesive is applied to the surface of the heat conductive plate pad 8, and the heat conductive plate 40 is aligned.
Is superimposed on and adhered to the heat conduction plate pad 8. The semiconductor chip 5 is die-bonded face-up by soldering or the like on the central square portion 40A on the surface of the heat conductive plate 40,
The electrode of the semiconductor chip 5 is exposed to the pad 7 exposed in the window 41.
Bonding is performed via a lead of a tape carrier (not shown) or a wire such as a gold wire.
【００３３】50は、平面視形状が熱伝導板用パッド８の
外形寸法にほぼ等しい枠形で、それぞれの枠壁の上方に
多数の放熱用のフィン51を設けた、アルミニウム等より
なる放熱体である。Reference numeral 50 denotes a frame having a shape in plan view substantially equal to the outer dimensions of the pad 8 for the heat conductive plate, and a heat radiator made of aluminum or the like, provided with a large number of fins 51 for heat radiation above each frame wall. It is.
【００３４】放熱体50は、熱伝導板40の表面の周縁部
に、半田付けする等して搭載されている。なお、図示省
略したが、放熱体50内に樹脂を充填して半導体チップ５
を樹脂封止している。The radiator 50 is mounted on the peripheral portion of the surface of the heat conductive plate 40 by soldering or the like. Although not shown, the semiconductor chip 5 is filled with resin in the radiator 50.
Is sealed with resin.
【００３５】上述のように構成されているので、半導体
チップ５の熱はセラミック等に較べて熱伝導率が非常に
大きい金属よりなる熱伝導板40を介して、放熱フィンを
有する枠形の放熱体50に伝達され、空気中に放出され
る。Since the semiconductor chip 5 is constructed as described above, the heat of the semiconductor chip 5 is transmitted through the heat conductive plate 40 made of a metal having a much higher thermal conductivity than that of ceramics or the like, thereby forming a frame-shaped heat radiating fin having radiating fins. Transmitted to the body 50 and released into the air.
【００３６】また、信号パターンである導体パターン32
が、ポリイミド等の低誘電率樹脂層31内に微小幅に形成
されているので、本発明の半導体装置は、高密度実装
化，信号の高速化が推進される。The conductor pattern 32 which is a signal pattern
However, since the semiconductor device of the present invention is formed with a very small width in the low dielectric constant resin layer 31 of polyimide or the like, high-density mounting and high-speed signal are promoted.
【００３７】さらにまた、アルミナ等のセラミック基板
２内に厚膜の電源パターン21が形成され、ビヤ22を介し
て熱伝導板用パッド８の中央角形部8Aに接続されている
ので、十分の背面電圧を半導体チップに供給することが
できる。Further, since a thick-film power supply pattern 21 is formed in the ceramic substrate 2 made of alumina or the like and is connected to the central square portion 8A of the heat conduction plate pad 8 via the via 22, a sufficient back surface is provided. Voltage can be supplied to the semiconductor chip.
【００３８】図２において、60は、平面視形状が熱伝導
板用パッド８の外形寸法にほぼ等しい下部が開口した箱
形で、その上部の底板の表面に多数の放熱用のフィン61
を設けた、アルミニウム等よりなるケースである。In FIG. 2, reference numeral 60 denotes a box-like shape having a bottom view that is substantially equal to the outer dimensions of the pad 8 for a heat conduction plate, and a large number of radiating fins 61 are provided on the surface of the upper bottom plate.
And a case made of aluminum or the like.
【００３９】ケース60は、熱伝導板40の周縁部に、その
開口端面を半田付けする等して搭載されて、半導体チッ
プ５を気密に封止している。上述のように構成された半
導体装置は、半導体チップを樹脂封止する等の必要がな
くなり半導体装置がそれだけ低コストとなるばかりでな
く、放熱体を箱形のケースとすることにより表面積が広
くて、冷却効果がさらに向上する。The case 60 is mounted on the peripheral portion of the heat conductive plate 40 by soldering the opening end face thereof or the like, and hermetically seals the semiconductor chip 5. The semiconductor device configured as described above eliminates the necessity of sealing the semiconductor chip with a resin, etc., so that the semiconductor device is not only low in cost but also has a large surface area by using a box-shaped radiator. The cooling effect is further improved.
【００４０】[0040]
【発明の効果】以上説明したように本発明は、半導体チ
ップを搭載する回路基板を、セラミック基板と多層樹脂
基板との複合構造とし、多層樹脂基板３の表面に熱伝導
板用パッド，アウタリードボンディング用のパッドを設
け、熱伝導板用パッド上に熱伝導板を貼着し、熱伝導板
の中央部に半導体チップをダイボンディングし、その外
側に放熱体を固着したもので、半導体チップの放熱性が
非常に良好であるばかりでなく、導体パターンの配線領
域が広く、且つ高密度実装化，信号の高速化が推進され
るという、実用上で優れた効果を有する。As described above, according to the present invention, a circuit board on which a semiconductor chip is mounted has a composite structure of a ceramic board and a multilayer resin board, and a pad for a heat conductive plate and outer leads are provided on the surface of the multilayer resin board 3. A bonding pad is provided, a heat conductive plate is attached on the heat conductive plate pad, a semiconductor chip is die-bonded to a central portion of the heat conductive plate, and a radiator is fixed outside the semiconductor chip. Not only is the heat radiation very good, but the wiring area of the conductor pattern is wide, and high-density mounting and high-speed signal are promoted.
【００４１】また、セラミック基板の厚膜の電源パター
ンとダイボンディング用パッドとをビヤで接続すること
で、電圧降下することなく十分の背面電圧を半導体チッ
プに供給することができる。Further, by connecting the thick power supply pattern of the ceramic substrate and the die bonding pad with vias, a sufficient back voltage can be supplied to the semiconductor chip without voltage drop.
【００４２】さらにまた、放熱体を箱形のケースとする
ことで、半導体チップの封止ケースを兼ねることによ
り、半導体チップを樹脂封止する等の必要がなくなり半
導体装置がそれだけ低コストとなる。Further, since the heat radiator is formed as a box-shaped case, it also serves as a sealing case for the semiconductor chip, thereby eliminating the necessity of sealing the semiconductor chip with a resin or the like, thereby reducing the cost of the semiconductor device.
【図面の簡単な説明】[Brief description of the drawings]
【図１】 本発明の実施例の図で、 (A) は断面図 (B) は熱伝導板の平面図FIG. 1 is a view of an embodiment of the present invention, wherein (A) is a cross-sectional view and (B) is a plan view of a heat conducting plate.
【図２】 本発明の他の実施例の断面図FIG. 2 is a sectional view of another embodiment of the present invention.
【図３】 従来例の要所断面図FIG. 3 is a cross-sectional view of a main part of a conventional example.
【図４】 他の従来例の要所断面図FIG. 4 is a cross-sectional view of a main part of another conventional example.
１ 回路基板、 ２ セラミッ
ク基板、３ 多層樹脂基板、 ５
半導体チップ、６ ダイボンディング用パッド、７ パ
ッド、８ 熱伝導板用パッド、 8A,40A
中央角形部、8B,41 窓、 ９
角形孔、21 電源パターン、 31
低誘電率樹脂層、32 導体パターン、
40 熱伝導板、41 窓、 50
放熱体、51,61 フィン、 60
ケース、1 circuit board, 2 ceramic board, 3 multilayer resin board, 5
Semiconductor chip, 6 die bonding pad, 7 pad, 8 heat conduction plate pad, 8A, 40A
Central square, 8B, 41 windows, 9
Square hole, 21 Power pattern, 31
Low dielectric constant resin layer, 32 conductor pattern,
40 heat conduction plate, 41 windows, 50
Heat sink, 51,61 fins, 60
Case,
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平５−21959（ＪＰ，Ａ) 特開 昭61−148847（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/12 H01L 23/36 H01L 23/40────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-5-21959 (JP, A) JP-A-61-148847 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 23/12 H01L 23/36 H01L 23/40
Claims (3)
載する回路基板(1)は、セラミック基板(2) と、該セラ
ミック基板(2)の表面に低誘電率樹脂層(31)と導体パタ
ーン(32)とを交互に形成した多層樹脂基板(3) とで構成
され、 中央角形部(8A)の周辺を枠形に取り囲む短冊形の窓(8B)
を有する角形の熱伝導板用パッド(8) と、該窓(8B)内に
配列したアウタリードボンディング用のパッド(7) と
が、該多層樹脂基板(3) の表面に形成され、 該熱伝導板用パッド(8) の窓(8B)に対応した個所に短冊
形の窓(41)を有する角形の熱伝導板(40)が、該熱伝導板
用パッド(8) 上に貼着され、 該熱伝導板(40)の中央角形部(40A) 上に半導体チップ
(5) がダイボンディングされ、周辺部に枠形の放熱体(5
0)が搭載されたことを特徴とする半導体装置。A circuit board (1) on which a semiconductor chip (5) is mounted face-up includes a ceramic substrate (2), a low dielectric resin layer (31) and a conductive pattern on the surface of the ceramic substrate (2). (32) and a multilayer resin substrate (3) alternately formed, and a rectangular window (8B) surrounding the central square part (8A) in a frame shape
And a pad for outer lead bonding (7) arranged in the window (8B) are formed on the surface of the multilayer resin substrate (3). A rectangular heat conductive plate (40) having a strip-shaped window (41) at a position corresponding to the window (8B) of the conductive plate pad (8) is stuck on the heat conductive plate pad (8). A semiconductor chip on the central square portion (40A) of the heat conducting plate (40)
(5) is die-bonded, and a frame-shaped radiator (5
(0) is a semiconductor device.
伝導板用パッド(8)の中央角形部(8A)が、ビヤ(22)を介
してセラミック基板(2) 内に設けた電源パターン(21)
に、接続されたことを特徴とする請求項１記載の半導体
装置。2. A central square portion (8A) of a heat conductive plate pad (8) formed on the surface of a multilayer resin substrate (3) is provided in a ceramic substrate (2) via a via (22). Power supply pattern (21)
2. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the semiconductor device.
半導体チップ(5) を封止する箱形のケース(60)であるこ
とを特徴とする半導体装置。3. The radiator according to claim 1 or 2,
A semiconductor device comprising a box-shaped case (60) for sealing a semiconductor chip (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3209677A JP2841945B2 (en) | 1991-08-22 | 1991-08-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3209677A JP2841945B2 (en) | 1991-08-22 | 1991-08-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0555398A JPH0555398A (en) | 1993-03-05 |
| JP2841945B2 true JP2841945B2 (en) | 1998-12-24 |
Family
ID=16576788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3209677A Expired - Lifetime JP2841945B2 (en) | 1991-08-22 | 1991-08-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2841945B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06334113A (en) * | 1993-05-21 | 1994-12-02 | Sony Corp | Multichip module |
| CN208753094U (en) * | 2016-03-02 | 2019-04-16 | 株式会社村田制作所 | Modular unit and multilager base plate |
| CN208862743U (en) * | 2016-04-13 | 2019-05-14 | 株式会社村田制作所 | Inductor module |
| CN116314050B (en) * | 2023-05-22 | 2023-07-18 | 东莞市华越半导体技术股份有限公司 | Multi-chip packaging module and method |
-
1991
- 1991-08-22 JP JP3209677A patent/JP2841945B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0555398A (en) | 1993-03-05 |
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Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980922 |