JPH04124860A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH04124860A JPH04124860A JP2245329A JP24532990A JPH04124860A JP H04124860 A JPH04124860 A JP H04124860A JP 2245329 A JP2245329 A JP 2245329A JP 24532990 A JP24532990 A JP 24532990A JP H04124860 A JPH04124860 A JP H04124860A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- island
- board
- lead frame
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims description 19
- 230000017525 heat dissipation Effects 0.000 claims description 15
- 239000011347 resin Substances 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
本発明は、リードフレームで端子を形成した半導体パッ
ケージに関するものである。The present invention relates to a semiconductor package in which terminals are formed using a lead frame.
ＱＦＰＲ？ＳＯＰなどの半導体パッケージは、パッケー
ジ基板に半導体を実装すると共にパッケージ基板にリー
ドフレームの端子を接続し、そして半導体やパッケージ
基板、端子の基部を樹脂で封止することによって作成さ
れている。QFPR? A semiconductor package such as an SOP is produced by mounting a semiconductor on a package substrate, connecting terminals of a lead frame to the package substrate, and sealing the semiconductor, the package substrate, and the base of the terminal with resin.
【発明が解決しようとする課１１！］
しかし集積密度を高く形成した半導体のチップでは発熱
量が高くなっており、このような半導体パッケージに半
導体を実装すると熱がこもって半導体に劣化が発生し易
くなる等の問題があり、発熱量の高い半導体を実装する
ことができないものであった。
本発明は上記の点に鑑みて為されたものであり、発熱量
の高い半導体を実装することができる半導体パッケージ
を提供することを目的とするものである。
【８題を解決するための手段】
本発明に係る半導体パッケージは、半導体１を実装した
パッケージ基板２をリードフレーム３のアイランド部４
の片面に取着し、このアイランド部４の他方の片面に放
熱用プレート５を取着して成ることを特徴とするもので
ある。[Lesson 11 that the invention attempts to solve! ] However, semiconductor chips formed with high integration density generate a high amount of heat, and when a semiconductor is mounted in such a semiconductor package, there are problems such as heat buildup and deterioration of the semiconductor. This made it impossible to mount semiconductors with high temperatures. The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor package that can mount a semiconductor that generates a high amount of heat. [Means for Solving Problem 8] A semiconductor package according to the present invention has a package substrate 2 on which a semiconductor 1 is mounted on an island portion of a lead frame 3.
A heat dissipation plate 5 is attached to one side of the island portion 4, and a heat dissipation plate 5 is attached to the other side of the island portion 4.
本発明にあっては、半導体１を実装したパッケージ基板
２を片面に取着したアイランド部４の他方の片面に放熱
用プレート５を取着するようにしているために、半導体
ｌの発熱は放熱用プレート５から放熱させることができ
、半導体パッケージに熱がこもることを防ぐことができ
る。In the present invention, since the heat dissipation plate 5 is attached to the other side of the island section 4 on which the package substrate 2 on which the semiconductor 1 is mounted is attached on one side, the heat generated by the semiconductor 1 is dissipated. Heat can be radiated from the storage plate 5, and heat can be prevented from accumulating in the semiconductor package.
以下本発明を実施例によって詳述する。
第１図の実施例ではパッケージ基板２として多層プリン
ト配線板を用いるようにしである。すなわち、外層の回
路８ａを設けた外層配線板２ａと内層の回路８ｂを設け
た内層配線板２ｂとを積層することによって作成される
多層プリント配線板を用いてパッケージ基板２を作成す
るようにしてあり、パッケージ基板２の中央部には上下
に貫通して開口するキャビティ１０が座ぐり加工等で設
けである。内層の回路１ｂのうちこのキャビティ１０の
周縁部の部分をインナーリード部１１ｂとして露出させ
てあり、またパッケージ基板２の外周端部の部分をアウ
ターリード部１２ｂとして露出させである。一方、リー
ドフレーム３は金属薄板をプレス加工等することによっ
て作成されるものであり、両側に複数本づつ配置される
端子６６と、この端子６．６間に配置されるアイランド
部４とがリードフレーム３の一部として形成しである。
上記パッケージ基板２はこのリードフレーム３のアイラ
ンド部４の片面に接着等して接合することによって取り
付けである。このようにパッケージ基板２をアイランド
部４に取り付けることによってパッケージ基板２に形成
したキャビティｌＯの底部はアイランド部４によって形
成されることになり、ＩＣチップ等の半導体１はアイラ
ンド部４の表面においてキャビティ１０内に搭載される
。そしてこの半導体１と回路８ａ ８ｂのキャビティ
１０側の端部に形成されるインナーリード部１１ａ、１
１ｂとの間に金線等のワイヤー１３をボンディングして
半導体１を各回路８ａ、８ｂに接続する。またパッケー
ジ基板２の周端部において各回路８ａ、８ｂに形成され
るアウターリード部１２ａ、１２ｂとリードフレーム３
の各端子６の基端との間に金線等のワイヤー１３をボン
ディングして各端子６を各回路８ａ、８ｂに接続する。
このようにして回１８ａ、８ｂを介して半導体１と端子
６とを電気的に接続することができる。
また、アイランド部４のパッケージ基板２を接合した面
と反対側の面には放熱用プレート５が接着等して取着し
である。この放熱用プレート５は半導体１を搭載した部
分に対応して取着されるものであり、銅板など熱伝導率
の高いものを用いるのが好ましい、放熱用プレート５の
材質は勿論これに限定されるものではないが、リードフ
レーム３や封止用のモールド樹脂１４と熱膨張係数が同
一もしくは同等のものを用いるのが好ましい。
上記のようにリードフレーム３にパッケージ基板２や放
熱用プレート５を取り付けた後に、パッケージ基板２と
アイランド部４と端子６の基部をモールド成形して樹脂
１４で封止し、そしてアイランド部４や端子６をリード
フレーム３のフレームから切り離すことによって、半導
体パッケージを作成することができる。このとき、第１
図に示すように放熱用プレート５の表面は樹脂１４に埋
入されず露出されるようにしてあり、放熱用プレート５
の露出表面に金属製等の放熱フィン１５が取り付けであ
る。
このようにして第１図のように作成される半導体パッケ
ージにあって、半導体１がら発熱された熱はリードフレ
ーム３のアイランド部４がら放熱用プレート５に伝達さ
れ、放熱フィン１５を介して半導体パッケージの外部に
放熱される。ここで、第１図の実施例のように、半導体
１をリードフレーム３のアイランド部４に直接搭載する
ようにすれば、半導体１の発熱は直接アイランド部４が
ら放熱用プレート５へと伝達させることができるために
、放熱効果を高く得ることができるものである。The present invention will be explained in detail below with reference to Examples. In the embodiment shown in FIG. 1, a multilayer printed wiring board is used as the package substrate 2. That is, the package board 2 is created using a multilayer printed wiring board created by laminating an outer layer wiring board 2a provided with an outer layer circuit 8a and an inner layer wiring board 2b provided with an inner layer circuit 8b. A cavity 10 is provided in the center of the package substrate 2 by counterboring or the like and opening vertically through the package substrate 2. Of the inner layer circuit 1b, the peripheral edge portion of the cavity 10 is exposed as an inner lead portion 11b, and the outer peripheral edge portion of the package substrate 2 is exposed as an outer lead portion 12b. On the other hand, the lead frame 3 is made by pressing a thin metal plate, and has a plurality of terminals 66 arranged on both sides and an island portion 4 arranged between the terminals 6.6. It is formed as part of the frame 3. The package substrate 2 is attached to one side of the island portion 4 of the lead frame 3 by bonding or the like. By attaching the package substrate 2 to the island portion 4 in this way, the bottom of the cavity 10 formed in the package substrate 2 is formed by the island portion 4, and the semiconductor 1 such as an IC chip is placed in the cavity on the surface of the island portion 4. It will be installed within 10. Inner lead portions 11a and 1 formed at the end of the semiconductor 1 and the circuits 8a and 8b on the cavity 10 side.
The semiconductor 1 is connected to each circuit 8a, 8b by bonding a wire 13 such as a gold wire between the semiconductor 1 and the semiconductor 1b. Further, outer lead portions 12a and 12b formed in each circuit 8a and 8b at the peripheral end of the package substrate 2 and the lead frame 3
A wire 13 such as a gold wire is bonded between the base end of each terminal 6 to connect each terminal 6 to each circuit 8a, 8b. In this way, the semiconductor 1 and the terminal 6 can be electrically connected via the circuits 18a and 8b. Further, a heat dissipation plate 5 is attached to the surface of the island portion 4 opposite to the surface to which the package substrate 2 is bonded, by means of adhesive or the like. This heat dissipation plate 5 is attached to the part where the semiconductor 1 is mounted, and it is preferable to use a material with high thermal conductivity such as a copper plate, but the material of the heat dissipation plate 5 is of course not limited to this. It is preferable to use a material having the same or equivalent coefficient of thermal expansion as the lead frame 3 and the mold resin 14 for sealing. After attaching the package substrate 2 and the heat dissipation plate 5 to the lead frame 3 as described above, the package substrate 2, the island portion 4 and the base of the terminal 6 are molded and sealed with resin 14. By separating the terminals 6 from the frame of the lead frame 3, a semiconductor package can be created. At this time, the first
As shown in the figure, the surface of the heat dissipation plate 5 is not embedded in the resin 14 but is exposed.
A heat dissipation fin 15 made of metal or the like is attached to the exposed surface. In the semiconductor package thus produced as shown in FIG. Heat is dissipated to the outside of the package. Here, if the semiconductor 1 is mounted directly on the island portion 4 of the lead frame 3 as in the embodiment shown in FIG. Therefore, it is possible to obtain a high heat dissipation effect.
上述のように本発明にあっては、半導体を実装したパッ
ケージ基板をリードフレームのアイランド部の片面に取
着し、このアイランド部の他方の片面に放熱用プレート
を取着しであるので、半導体から発熱された熱はリード
フレームのアイランド部を介して放熱用プレートに伝達
され、放熱用プレートから放熱させることができるもの
であって、半導体パッケージに熱がこもることを防ぐこ
とがてきるものであり１発熱量の高い半導体を実装する
ことが可能になるものである。As described above, in the present invention, the package substrate on which the semiconductor is mounted is attached to one side of the island portion of the lead frame, and the heat dissipation plate is attached to the other side of the island portion. The heat generated from the lead frame is transferred to the heat dissipation plate via the island part of the lead frame, and the heat is radiated from the heat dissipation plate, which prevents heat from accumulating in the semiconductor package. This makes it possible to mount semiconductors with a high calorific value.
第１図は本発明の一実施例の断面図であり、１は半導体
、２はパッケージ基板、３はリードフレーム、４はアイ
ランド部、５は放熱用プレートである。FIG. 1 is a sectional view of an embodiment of the present invention, in which 1 is a semiconductor, 2 is a package substrate, 3 is a lead frame, 4 is an island portion, and 5 is a heat dissipation plate.
Claims (1)
ムのアイランド部の片面に取着し、このアイランド部の
他方の片面に放熱用プレートを取着して成ることを特徴
とする半導体パッケージ。(1) A semiconductor package characterized in that a package substrate on which a semiconductor is mounted is attached to one side of an island portion of a lead frame, and a heat dissipation plate is attached to the other side of the island portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2245329A JPH06103722B2 (en) | 1990-09-14 | 1990-09-14 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2245329A JPH06103722B2 (en) | 1990-09-14 | 1990-09-14 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04124860A true JPH04124860A (en) | 1992-04-24 |
| JPH06103722B2 JPH06103722B2 (en) | 1994-12-14 |
Family
ID=17132045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2245329A Expired - Lifetime JPH06103722B2 (en) | 1990-09-14 | 1990-09-14 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06103722B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06151641A (en) * | 1992-11-05 | 1994-05-31 | Toshiba Corp | Semiconductor device |
| JPH08162558A (en) * | 1994-12-07 | 1996-06-21 | Fujitsu Ltd | Semiconductor device |
| KR100765604B1 (en) * | 2004-11-26 | 2007-10-09 | 산요덴키가부시키가이샤 | Circuit device and manufacturing method thereof |
-
1990
- 1990-09-14 JP JP2245329A patent/JPH06103722B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06151641A (en) * | 1992-11-05 | 1994-05-31 | Toshiba Corp | Semiconductor device |
| JPH08162558A (en) * | 1994-12-07 | 1996-06-21 | Fujitsu Ltd | Semiconductor device |
| KR100765604B1 (en) * | 2004-11-26 | 2007-10-09 | 산요덴키가부시키가이샤 | Circuit device and manufacturing method thereof |
| US7529093B2 (en) | 2004-11-26 | 2009-05-05 | Sanyo Electric Co., Ltd. | Circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06103722B2 (en) | 1994-12-14 |
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