JPH104167A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH104167A JPH104167A JP15681696A JP15681696A JPH104167A JP H104167 A JPH104167 A JP H104167A JP 15681696 A JP15681696 A JP 15681696A JP 15681696 A JP15681696 A JP 15681696A JP H104167 A JPH104167 A JP H104167A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- copper plate
- thin
- metal
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えば電力用の半
導体素子を搭載し、金属細線による接続がなされて構成
される半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounted with, for example, a power semiconductor element and connected by thin metal wires.
【０００２】[0002]
【従来の技術】周知の通り、半導体装置を製造する過程
で、例えばＤＢＣ（Ｄｉｒｅｃｔ Ｂｏｎｄｉｎｇ Ｃ
ｏｐｐｅｒ Ｉｎｓｕｌａｔｅｄ Ｂｏａｒｄ）の窒化
アルミニウム（ＡｌＮ）製の絶縁基板の表面に被着され
た所定パターンの銅板に、金やアルミニウム等の金属細
線によるボンディングを行おうとした場合、銅板の表面
が酸化していると超音波ボンディングが難しくなる。こ
のため、半導体素子をＤＢＣ表面の銅板の所定位置に半
田接続（ダイ・ボンディング）により搭載させる際、半
田接続の雰囲気を還元雰囲気にして銅板の酸化を防止す
るようにしたり、あるいは、ＤＢＣ表面の銅板の全表面
にニッケルめっき等のめっき処理を施し、ダイ・ボンデ
ィングの際に銅板の金属細線をボンディングする領域が
酸化し、超音波ボンディングが行えなくなるのを防止す
るようにしている。2. Description of the Related Art As is well known, in the process of manufacturing a semiconductor device, for example, DBC (Direct Bonding C) is used.
When an attempt is made to bond a copper plate having a predetermined pattern adhered to the surface of an insulating substrate made of aluminum (Board Insulated Board) aluminum nitride (AlN) using a thin metal wire such as gold or aluminum, the surface of the copper plate is oxidized. And ultrasonic bonding becomes difficult. For this reason, when the semiconductor element is mounted on a predetermined position of the copper plate on the DBC surface by solder connection (die bonding), the atmosphere of the solder connection is changed to a reducing atmosphere to prevent oxidation of the copper plate, or A plating process such as nickel plating is applied to the entire surface of the copper plate to prevent the region where the thin metal wire of the copper plate is bonded from being oxidized at the time of die bonding to prevent ultrasonic bonding from being performed.
【０００３】こうした従来の技術を図５に示す断面図及
び図６にケースを取り外して示す斜視図により説明す
る。図５及び図６において、１は半導体装置であり、２
は放熱板を構成する金属ベースであり、３は金属ベース
２の上面に半田４によって固着されたＤＢＣであり、Ｄ
ＢＣ３はセラミック板５の両面に銅板６ａ，６ｂが被着
されている。またＤＢＣ３の上面側の銅板６ａは複数の
半導体素子７や外部への引き出しを行う電極端子８をそ
れぞれ接続するようにパターニングされている。[0005] Such a conventional technique will be described with reference to a sectional view shown in FIG. 5 and a perspective view of FIG. 6 with a case removed. 5 and 6, reference numeral 1 denotes a semiconductor device;
Is a metal base constituting a heat sink, 3 is a DBC fixed on the upper surface of the metal base 2 by solder 4, and D
The BC3 has ceramic plates 5 with copper plates 6a and 6b attached to both surfaces. The copper plate 6a on the upper surface side of the DBC 3 is patterned so as to connect the plurality of semiconductor elements 7 and the electrode terminals 8 for leading out to the outside.
【０００４】そしてパターニングされた銅板６ａへの半
導体素子７の搭載、すなわちダイ・ボンディング及び電
極端子８の接続が、還元雰囲気中での半田９によって行
われている。また半導体素子７と他の半導体素子７が接
続された銅板６ａ、あるいは半導体素子７と電極端子８
が接続された銅板６ａとは、超音波ボンディングによっ
て金属細線１０を固着することで接続されている。な
お、１１は銅板６ａ表面の超音波ボンディング部分であ
り、１２は金属ベース２の上面に固着された半導体素子
７等を搭載するＤＢＣ３を覆うケースである。The mounting of the semiconductor element 7 on the patterned copper plate 6a, that is, the die bonding and the connection of the electrode terminals 8 are performed by the solder 9 in a reducing atmosphere. Also, a copper plate 6a to which the semiconductor element 7 and another semiconductor element 7 are connected, or the semiconductor element 7 and the electrode terminal 8
Is connected to the copper plate 6a to which the thin metal wire 10 is fixed by ultrasonic bonding. Reference numeral 11 denotes an ultrasonic bonding portion on the surface of the copper plate 6a, and reference numeral 12 denotes a case that covers the DBC 3 on which the semiconductor element 7 and the like fixed to the upper surface of the metal base 2 are mounted.
【０００５】しかし、このような還元雰囲気を用いた銅
板６ａの酸化防止対策を行って構成したものでも、また
上記のような還元雰囲気を用いずにＤＢＣ３の半導体素
子７等を搭載する側の銅板６ａの表面全面に、図示しな
いがニッケルめっき等のめっき処理を施したものでも、
半導体素子７のダイ・ボンディングの際等にダイ・ボン
ディング部分の半田９が、銅板６ａの金属細線１０のボ
ンディング領域に流れ出し、これによって超音波ボンデ
ィングが行えなくなったりする場合が生じる。このた
め、またダイ・ボンディングの際等にボンディング領域
に半田９が流れ出したりしないよう半田流れ防止の対策
をしなければならなかった。[0005] However, even in the case where the countermeasure for preventing oxidation of the copper plate 6a using such a reducing atmosphere is taken, the copper plate on the side on which the semiconductor element 7 and the like of the DBC 3 are mounted without using the above reducing atmosphere is used. Although not shown, even though the entire surface of 6a is plated with nickel or the like,
At the time of die bonding of the semiconductor element 7 or the like, the solder 9 at the die bonding portion flows into the bonding region of the thin metal wire 10 of the copper plate 6a, which may cause a case where ultrasonic bonding cannot be performed. For this reason, it is necessary to take measures to prevent the solder from flowing so that the solder 9 does not flow into the bonding area at the time of die bonding or the like.
【０００６】[0006]
【発明が解決しようとする課題】上記のように従来は金
属細線を超音波ボンディングするＤＢＣ表面の銅板のボ
ンディング領域が酸化されるのを防止するため、ダイ・
ボンディングを還元雰囲気中で行ったり、ＤＢＣ表面の
銅板の全表面にニッケルめっき等を施したり、またダイ
・ボンディングの際のボンディング領域への半田流れ防
止の対策を行わなければならなかった。このような状況
に鑑みて本発明はなされたもので、ダイ・ボンディング
の際の酸化防止が不要になり、またダイ・ボンディング
の際の半田流れ防止の対策が不要となることによって簡
単に製造することができる製造性の良好な半導体装置を
提供することを目的とするものである。As described above, in order to prevent the bonding region of the copper plate on the surface of the DBC where ultrasonic bonding of a thin metal wire is conventionally performed from being oxidized, a die is used.
Bonding must be performed in a reducing atmosphere, nickel plating or the like must be applied to the entire surface of the copper plate on the DBC surface, and measures must be taken to prevent the flow of solder to the bonding region during die bonding. The present invention has been made in view of such circumstances, and it is easy to manufacture by eliminating the need for preventing oxidation during die bonding and eliminating the need for measures for preventing solder flow during die bonding. It is an object of the present invention to provide a semiconductor device with good manufacturability that can be manufactured.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置は、
金属ベース上に固着された絶縁基板と、この絶縁基板の
上面に被着された導体薄板をパターニングすることによ
って形成された複数の導体パターン部と、この導体パタ
ーン部の少なくとも１つに半田付けにより固定され載置
された半導体素子と、導体パターン部に半田付けにより
固着された所定のめっき処理が施された金属端子片と、
この金属端子片と半導体素子とにボンディングされた金
属細線とを備えてなることを特徴とするものであり、さ
らに、金属端子片に施されためっき処理が、ニッケルめ
っきあるいは金めっきであることを特徴とするものであ
り、さらに、金属端子片と半導体素子への金属細線のボ
ンディングが、超音波ボンディングによって行われてい
ることを特徴とするものであり、また、金属ベース上に
固着された絶縁基板と、この絶縁基板の上面に被着され
た導体薄板をパターニングすることによって形成された
複数の導体パターン部と、この導体パターン部の少なく
とも１つに半田付けにより固定されて載置された半導体
素子と、導体パターン部の他の少なくとも１つに半田付
けにより固着された導体薄板によって所定回路パターン
が形成された回路基板片と、この回路基板片の回路パタ
ーンと半導体素子とにボンディングされた金属細線とを
備えてなることを特徴とするものであり、さらに、回路
基板片が、ガラスエポキシ樹脂板あるいはフェノール樹
脂板の表面に銅薄板によりなる回路パターンが形成され
たものであることを特徴とするものであり、さらに、回
路基板片の回路パターンと半導体素子への金属細線のボ
ンディングが、超音波ボンディングによって行われてい
ることを特徴とするものであり、さらに、導体パターン
部が、銅板により形成されていることを特徴とするもの
であり、さらに、導体パターン部が、全表面に半田層が
形成されていることを特徴とするものである。According to the present invention, there is provided a semiconductor device comprising:
An insulating substrate fixed on a metal base, a plurality of conductive pattern portions formed by patterning a conductive thin plate adhered on the upper surface of the insulating substrate, and soldering to at least one of the conductive pattern portions; A fixed and mounted semiconductor element, and a metal terminal piece subjected to a predetermined plating process fixed to the conductor pattern portion by soldering,
The metal terminal piece and a thin metal wire bonded to the semiconductor element are provided, and the plating process performed on the metal terminal piece is nickel plating or gold plating. In addition, the bonding of the metal terminal strip and the thin metal wire to the semiconductor element is performed by ultrasonic bonding, and the insulation is fixed on the metal base. A substrate, a plurality of conductor pattern portions formed by patterning a conductor thin plate adhered to the upper surface of the insulating substrate, and a semiconductor fixed and mounted on at least one of the conductor pattern portions by soldering A circuit in which a predetermined circuit pattern is formed by an element and a conductive thin plate fixed to at least one other of the conductive pattern portions by soldering And a circuit board piece, a circuit pattern of the circuit board piece, and a thin metal wire bonded to the semiconductor element. The circuit board piece further comprises a glass epoxy resin plate or a phenol resin plate. A circuit pattern made of a copper thin plate is formed on the surface of the substrate, and further, the bonding of the circuit pattern of the circuit board piece and the thin metal wire to the semiconductor element is performed by ultrasonic bonding. Further, the conductor pattern portion is formed of a copper plate, and further, the conductor pattern portion, a solder layer is formed on the entire surface It is characterized by the following.
【０００８】[0008]
【発明の実施の形態】以下、本発明の実施の形態を図面
を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【０００９】先ず、第１の実施形態を図１及び図２によ
り説明する。図１は断面図であり、図２はケースを取り
外して示す斜視図である。図１及び図２において、２１
は半導体装置であり、これは銅製の厚板により形成され
た放熱板として機能する金属ベース２２の上面に、ＤＢ
Ｃ（Ｄｉｒｅｃｔ Ｂｏｎｄｉｎｇ ＣｏｐｐｅｒＩｎ
ｓｕｌａｔｅｄ Ｂｏａｒｄ）２３が半田層２４によっ
て固着されて構成されており、金属ベース２２の上面に
はＤＢＣ２３の上方を覆うように合成樹脂製ケース２５
が設けられている。ＤＢＣ２３は、例えば窒化アルミニ
ウム（ＡｌＮ）製絶縁基板等のセラミック板２６の両面
に薄板状の銅板２７ａ，２７ｂが被着されており、上面
側の銅板２７ａについては、所定のパターンを有するよ
うにＤＢＣ２３を金属ベース２２に固着させる前に予め
パターニングされて、複数の導体パターン部を形成して
いる。また下面側の銅板２７ｂ表面の半田層２４は予め
設けられていて、この半田層２４を金属ベース２２の上
面との間に介在させることによってＤＢＣ２３の金属ベ
ース２２への固着がなされる。First, a first embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional view, and FIG. 2 is a perspective view showing a case removed. In FIG. 1 and FIG.
Is a semiconductor device, which has a DB on the upper surface of a metal base 22 functioning as a heat sink formed of a thick copper plate.
C (Direct Bonding CopperIn
A metal case 22 is formed on the upper surface of the metal base 22 so as to cover the upper part of the DBC 23.
Is provided. In the DBC 23, thin copper plates 27a and 27b are adhered to both sides of a ceramic plate 26 such as an aluminum nitride (AlN) insulating substrate or the like, and the upper side copper plate 27a has a predetermined pattern so as to have a predetermined pattern. Are fixed in advance to the metal base 22 to form a plurality of conductor pattern portions. The solder layer 24 on the surface of the copper plate 27b on the lower surface side is provided in advance, and the DBC 23 is fixed to the metal base 22 by interposing the solder layer 24 between the upper surface of the metal base 22 and the solder layer 24.
【００１０】また、ＤＢＣ２３の所定のパターンをなす
銅板２７ａの所定部分には、その上面に半導体素子２８
が半田層２９によるダイ・ボンディングよって搭載され
ており、半導体素子２８が搭載されていない他の所定部
分には、ケース２５から外部への引き出しを行うための
電極端子３０等が同じく半田２９層によって固着されて
いる。さらに、銅板２７ａの半導体素子２８が搭載され
たり、あるいは電極端子３０等が固着されているものの
上面には、ニッケル（Ｎｉ）めっきによる表面処理がな
された銅板製の金属端子片３１が、同様に半田層２９に
よって固着されている。On a predetermined portion of the copper plate 27a forming a predetermined pattern of the DBC 23, a semiconductor element 28
Are mounted by die bonding using a solder layer 29, and electrode terminals 30 and the like for leading out from the case 25 to the outside are similarly provided on the other predetermined portion where the semiconductor element 28 is not mounted by the solder 29 layer. It is fixed. Further, on the upper surface of the copper plate 27a on which the semiconductor element 28 is mounted or the electrode terminal 30 or the like is fixed, a metal terminal piece 31 made of a copper plate which has been subjected to a surface treatment by nickel (Ni) plating is similarly provided. It is fixed by a solder layer 29.
【００１１】そしてＤＢＣ２３の上面側の銅板２７ａ表
面の半田層２９は、下面側の銅板２７ｂ表面の半田層２
４と同様に、パターニングされた銅板２７ａの表面の一
部あるいは全面に、予め半田めっき等を行うことによっ
て設けられていて、半導体素子２８や電極端子３０、金
属端子片３１を固着させる際、特に半田を供給すること
なく各々の固着を行うことができるようになっている。The solder layer 29 on the surface of the copper plate 27a on the upper surface of the DBC 23 is the same as the solder layer 2 on the surface of the copper plate 27b on the lower surface.
Similarly to 4, when the semiconductor element 28, the electrode terminal 30, and the metal terminal strip 31 are fixed to a part or the entire surface of the patterned copper plate 27a by performing solder plating or the like in advance, Each of them can be fixed without supplying solder.
【００１２】また、半導体素子２８の端子と、これに対
応する金属端子片３１のニッケルめっき面とは、両者に
それぞれ金属細線３２を超音波ボンディングによって固
着することで両者間が接続されている。なお、３３は金
属端子片３１上の超音波ボンディング部分であり、３４
は電極端子３０に導通するよう接続されケース２５外へ
引き出された外部電極である。Further, the terminals of the semiconductor element 28 and the corresponding nickel-plated surfaces of the metal terminal strips 31 are connected to each other by fixing fine metal wires 32 to each of them by ultrasonic bonding. Reference numeral 33 denotes an ultrasonic bonding portion on the metal terminal strip 31;
Are external electrodes that are connected to the electrode terminals 30 so as to conduct, and are drawn out of the case 25.
【００１３】このような構成のものでは、金属ベース２
２の上面にＤＢＣ２３を半田層２４により固着し、この
ＤＢＣ２３の所定パターンを有する銅板２７ａに半田層
２９によって半導体素子２８を搭載させたり、あるいは
電極端子３０、金属端子片３１等を固着させたりする
際、銅板２７ａの酸化防止対策として半田接続時の雰囲
気を還元雰囲気にするようなこともなく、また、特に銅
板２７ａの上面に対する半田流れ防止の対策も行うこと
なく搭載や固着が実行される。そして搭載された半導体
素子２８の端子と対応する金属端子片３１の上面に、金
属細線３２が超音波ボンディングによって固着され、半
導体素子２８の端子と金属端子片３１とが導通するよう
接続される。この金属細線３２の超音波ボンディングに
よる固着を行う際、金属端子片３１の表面がニッケルめ
っき面となっていることにより、超音波ボンディング部
分３３は良好な固着が行われたものとなる。In such a configuration, the metal base 2
The DBC 23 is fixed on the upper surface of the second 2 by a solder layer 24, and the semiconductor element 28 is mounted on the copper plate 27a having a predetermined pattern of the DBC 23 by the solder layer 29, or the electrode terminals 30, the metal terminal strips 31 and the like are fixed. At this time, as a countermeasure against oxidation of the copper plate 27a, mounting and fixing are performed without setting the atmosphere at the time of solder connection to a reducing atmosphere, and without taking measures to prevent the flow of solder particularly on the upper surface of the copper plate 27a. Then, a thin metal wire 32 is fixed to the upper surface of the metal terminal strip 31 corresponding to the terminal of the mounted semiconductor element 28 by ultrasonic bonding, and the terminal of the semiconductor element 28 and the metal terminal strip 31 are connected so as to conduct. When the thin metal wires 32 are fixed by ultrasonic bonding, the surface of the metal terminal strip 31 is a nickel-plated surface, so that the ultrasonic bonding portion 33 is properly fixed.
【００１４】この結果、還元雰囲気にしたり、ＤＢＣの
絶縁基板表面に被着されパターニングされている銅板の
表面全面に、ニッケルめっき等のめっき処理を施すとい
った酸化防止対策を行わなくても、また超音波ボンディ
ングを行おうとする部分への半田流れ防止の対策を行わ
なくても、金属細線３２の超音波ボンディングによる固
着を行うことができ、半導体素子２８の端子と対応する
金属端子片３１とを金属細線３２によって容易かつ簡単
に接続することができる。さらに、予め銅板２７ａに半
田層２９を設けておくことにより、銅板２７ａの酸化が
防止され、また半導体素子２８や金属端子片３１等の固
着を簡単に行うことができる。As a result, it is possible to achieve a super-high temperature atmosphere without taking a countermeasure against oxidation such as a reducing atmosphere or a plating treatment such as nickel plating on the entire surface of the copper plate which is adhered and patterned on the surface of the insulating substrate of DBC. The metal thin wire 32 can be fixed by ultrasonic bonding without taking measures to prevent the solder from flowing to the portion where the sonic bonding is to be performed, and the terminal of the semiconductor element 28 and the corresponding metal terminal piece 31 are connected to the metal. The connection can be made easily and easily by the thin wire 32. Further, by providing the solder layer 29 on the copper plate 27a in advance, the oxidation of the copper plate 27a is prevented, and the semiconductor element 28 and the metal terminal strips 31 can be easily fixed.
【００１５】なお、上記のものではニッケルめっきを施
した銅板製の金属端子片３１を用いたが、ニッケル板製
や、鉄やその他の金属板にニッケルめっきを施したもの
を金属端子片３１として用いてもよく、またニッケルめ
っきの代わりに半田付けの雰囲気温度程度の温度では酸
化膜が形成され難く、かつめっき表面に超音波ボンディ
ングが可能なめっき処理、例えば金（Ａｕ）めっき等を
用いてもよい。In the above-mentioned case, the metal terminal piece 31 made of a nickel-plated copper plate is used. However, a nickel-plated or iron-plated metal plate made of iron or another metal plate is used as the metal terminal piece 31. A plating process, such as gold (Au) plating, in which an oxide film is hardly formed at a temperature around the soldering ambient temperature and which allows ultrasonic bonding to the plating surface, instead of nickel plating, may be used. Is also good.
【００１６】次に、第２の実施形態を図３により説明す
る。図３はケースを取り外して示す要部の斜視図であ
る。図３において、４１は半導体装置であり、これは銅
製の金属ベース２２の上面にＤＢＣ２３が図示しない半
田層によって固着され、金属ベース２２の上面に図示し
ない合成樹脂製ケースを設けて構成されている。ＤＢＣ
２３は、絶縁基板であるセラミック板２６の上面にパタ
ーニングされた薄板状の銅板２７ａが被着されており、
また下面にも図示しない薄板状の銅板が被着され、その
表面にはＤＢＣ２３を金属ベース２２に固着する際の半
田層が予め設けられている。上面側の銅板２７ａについ
ては、予め所定のパターンを有するようパターニングさ
れて複数の導体パターン部を形成している。Next, a second embodiment will be described with reference to FIG. FIG. 3 is a perspective view of a main part with the case removed. In FIG. 3, reference numeral 41 denotes a semiconductor device, which is configured by fixing a DBC 23 on an upper surface of a copper metal base 22 by a solder layer (not shown) and providing a synthetic resin case (not shown) on the upper surface of the metal base 22. . DBC
Reference numeral 23 denotes a thin copper plate 27a patterned on the upper surface of a ceramic plate 26 as an insulating substrate,
Also, a thin copper plate (not shown) is attached to the lower surface, and a solder layer for fixing the DBC 23 to the metal base 22 is provided on the surface thereof in advance. The copper plate 27a on the upper surface side is patterned to have a predetermined pattern in advance to form a plurality of conductor pattern portions.
【００１７】一方、ＤＢＣ２３の所定のパターンをなす
銅板２７ａの所定部分には、その上面に半導体素子２８
が半田層２９によるダイ・ボンディングよって搭載され
ており、半導体素子２８が搭載されていない他の所定部
分には、ケースから外部への引き出しを行うための電極
端子３０や回路基板片４２が、半田層２９によって固着
されている。回路基板片４２はガラスエポキシ樹脂板４
３を基板として形成されたプリント配線板で、その上面
には所定回路パターンとなるようパターニングされた導
体薄板の薄銅板４４が被着されている。そして薄銅板４
４により形成された所定回路パターンのボンディングパ
ッド４５には、その表面に金メッキが施されており、ま
た薄銅板４４による所定回路パターンの他の部分４６に
は、薄銅板４４の対応部位とＤＢＣ２３の銅板２７ａと
が導通するようスルーホール４７が設けられている。な
お、４８は薄銅板４４の所定位置に搭載された実装部品
である。On the other hand, on a predetermined portion of the copper plate 27a forming a predetermined pattern of the DBC 23, a semiconductor element 28
Are mounted by die bonding using a solder layer 29, and electrode terminals 30 and circuit board pieces 42 for drawing out from the case to the outside are mounted on other predetermined portions where the semiconductor element 28 is not mounted. Secured by layer 29. The circuit board piece 42 is a glass epoxy resin plate 4
A printed wiring board 3 is formed as a substrate, and a thin copper plate 44 of a conductive thin plate patterned so as to have a predetermined circuit pattern is adhered on the upper surface thereof. And thin copper plate 4
The surface of the bonding pad 45 of the predetermined circuit pattern formed by 4 is gold-plated, and the other portion 46 of the predetermined circuit pattern by the thin copper plate 44 has a portion corresponding to the thin copper plate 44 and the DBC 23. A through hole 47 is provided so as to be electrically connected to the copper plate 27a. Reference numeral 48 denotes a mounted component mounted at a predetermined position on the thin copper plate 44.
【００１８】そして、半導体素子２８の端子とこれに対
応する回路基板片４２のボンディングパッド４５とは、
両者にそれぞれ金属細線３２を超音波ボンディングによ
って固着することで両者間が接続されている。また、銅
板２７ａ表面の半田層２９は、パターニングされた銅板
２７ａの表面の一部あるいは全面に、予め半田めっき等
を行うことによって設けられており、半導体素子２８や
電極端子３０、回路基板片４２を固着させる際、特に半
田を供給することなく各々の固着を行うことができるよ
うになっている。The terminals of the semiconductor element 28 and the corresponding bonding pads 45 of the circuit board piece 42 are
The two are connected by fixing the fine metal wires 32 to each of them by ultrasonic bonding. The solder layer 29 on the surface of the copper plate 27a is provided by previously performing a solder plating or the like on a part or the entire surface of the patterned copper plate 27a, and the semiconductor element 28, the electrode terminals 30, and the circuit board pieces 42 are provided. Can be fixed without supplying solder in particular.
【００１９】このような構成のものでは、金属ベース２
２の上面に半田層により固着されたＤＢＣ２３の所定パ
ターンを有する銅板２７ａに半田層２９によって半導体
素子２８を搭載させたり、あるいは電極端子３０、回路
基板片４２等を固着させたりする際、銅板２７ａの酸化
防止対策として半田接続時の雰囲気を還元雰囲気にする
ようなこともなく、また、特に銅板２７ａの上面に対す
る半田流れ防止の対策も行うことなく搭載や固着が実行
される。そして搭載された半導体素子２８の端子と回路
基板片４２の対応するボンディングパッド４５に、金属
細線３２が超音波ボンディングによって固着され、半導
体素子２８の端子と回路基板片４２のボンディングパッ
ド４５とが導通するよう接続される。この金属細線３２
の超音波ボンディングによる固着を行う際、回路基板片
４２のボンディングパッド４５が金めっき面となってい
ることにより、超音波ボンディング部分は良好な固着が
行われたものとなる。With such a structure, the metal base 2
When the semiconductor element 28 is mounted by the solder layer 29 on the copper plate 27a having a predetermined pattern of the DBC 23 fixed on the upper surface of the solder by the solder layer, or when the electrode terminals 30, the circuit board pieces 42, and the like are fixed, the copper plate 27a As a countermeasure against oxidation, mounting and fixing are performed without setting the atmosphere at the time of solder connection to a reducing atmosphere, and without taking measures to prevent solder flow, particularly on the upper surface of the copper plate 27a. Then, the thin metal wires 32 are fixed to the terminals of the mounted semiconductor element 28 and the corresponding bonding pads 45 of the circuit board piece 42 by ultrasonic bonding, and the terminals of the semiconductor element 28 and the bonding pads 45 of the circuit board piece 42 are electrically connected. To be connected. This thin metal wire 32
When performing the bonding by ultrasonic bonding, the bonding pad 45 of the circuit board piece 42 has a gold-plated surface, so that the ultrasonic bonding portion has good bonding.
【００２０】この結果、第１の実施形態と同様に、還元
雰囲気にしたり、ＤＢＣ表面の銅板の表面全面にニッケ
ルめっき等のめっき処理を施すといった酸化防止対策を
行わなくても、また超音波ボンディングを行おうとする
部分への半田流れ防止の対策を行わなくても、金属細線
３２の超音波ボンディングによる固着を行うことがで
き、半導体素子２８の端子と対応する回路基板片４２の
ボンディングパッド４５とを金属細線３２によって容易
かつ簡単に接続することができる。さらに、予め銅板２
７ａに半田層２９を設けておくことにより、銅板２７ａ
の酸化が防止され、また半導体素子２８や回路基板片４
２等の固着を簡単に行うことができる。As a result, in the same manner as in the first embodiment, the ultrasonic bonding can be performed without taking measures against oxidation such as reducing atmosphere or plating the entire surface of the copper plate on the DBC surface with nickel plating or the like. The bonding of the thin metal wires 32 by ultrasonic bonding can be performed without taking measures to prevent the flow of solder to the portion where the soldering is to be performed, and the bonding pads 45 of the circuit board piece 42 corresponding to the terminals of the semiconductor element 28 and the terminals of the semiconductor elements 28 Can be easily and easily connected by the thin metal wire 32. Furthermore, the copper plate 2
By providing the solder layer 29 on the copper plate 27a,
Of the semiconductor element 28 and the circuit board piece 4
2 can be easily fixed.
【００２１】次に、第３の実施形態を図４により説明す
る。図４はケースを取り外して示す要部の斜視図であ
る。図４において、５１は半導体装置であり、これは銅
製の金属ベース２２の上面にＤＢＣ２３が図示しない半
田層によって固着され、金属ベース２２の上面に図示し
ない合成樹脂製ケースを設けて構成されている。ＤＢＣ
２３は、絶縁基板であるセラミック板２６の上面に薄板
状の銅板２７ａが被着されており、また下面にも図示し
ない薄板状の銅板が被着され、その表面にはＤＢＣ２３
を金属ベース２２に固着する際の半田層が予め設けられ
ている。上面側の銅板２７ａについては、予め所定のパ
ターンを有するようパターニングされて複数の導体パタ
ーン部を形成している。Next, a third embodiment will be described with reference to FIG. FIG. 4 is a perspective view of a main part with the case removed. In FIG. 4, reference numeral 51 denotes a semiconductor device. The semiconductor device 51 includes a DBC 23 fixed to the upper surface of a copper metal base 22 by a solder layer (not shown), and a synthetic resin case (not shown) provided on the upper surface of the metal base 22. . DBC
23, a thin copper plate 27a is attached on the upper surface of a ceramic plate 26, which is an insulating substrate, and a thin copper plate (not shown) is also attached on the lower surface.
A solder layer is provided in advance when fixing to the metal base 22. The copper plate 27a on the upper surface side is patterned to have a predetermined pattern in advance to form a plurality of conductor pattern portions.
【００２２】一方、ＤＢＣ２３の所定のパターンをなす
銅板２７ａの所定部分には、その上面に半導体素子２８
が半田層２９によるダイ・ボンディングよって搭載され
ており、半導体素子２８が搭載されていない他の所定部
分には回路基板片５２が、半田層２９によって固着され
ている。回路基板片５２はガラスエポキシ樹脂板４３を
基板として形成されたプリント配線板で、その上面には
所定回路パターンとなるようパターニングされた導体薄
板の薄銅板５３が被着されている。そして薄銅板５３に
より形成された所定回路パターンの電極用パッド５４に
は、その表面に半田めっきが施されていて、ケースから
外部への引き出しを行うための電極端子３０が固着され
ている。また、薄銅板５３により形成された所定回路パ
ターンのボンディングパッド４５には、その表面に金メ
ッキが施されている。On the other hand, on a predetermined portion of the copper plate 27a forming a predetermined pattern of the DBC 23, a semiconductor element 28
Are mounted by die bonding using a solder layer 29, and a circuit board piece 52 is fixed to the other predetermined portion where the semiconductor element 28 is not mounted by the solder layer 29. The circuit board piece 52 is a printed wiring board formed using the glass epoxy resin plate 43 as a substrate, and a thin copper plate 53 of a conductive thin plate patterned to have a predetermined circuit pattern is adhered on the upper surface thereof. The surface of the electrode pad 54 of a predetermined circuit pattern formed by the thin copper plate 53 is solder-plated, and the electrode terminal 30 for drawing out from the case to the outside is fixed. The surface of the bonding pad 45 of a predetermined circuit pattern formed by the thin copper plate 53 is plated with gold.
【００２３】そして、半導体素子２８の端子とこれに対
応する回路基板片５２のボンディングパッド４５とは、
両者にそれぞれ金属細線３２を超音波ボンディングによ
って固着することで両者間が接続されている。また、銅
板２７ａ表面の半田層２９は、パターニングされた銅板
２７ａの表面の一部あるいは全面に、予め半田めっき等
を行うことによって設けられており、半導体素子２８や
回路基板片５２を固着させる際、特に半田を供給するこ
となく各々の固着を行うことができるようになってい
る。The terminals of the semiconductor element 28 and the corresponding bonding pads 45 of the circuit board piece 52 are
The two are connected by fixing the fine metal wires 32 to each of them by ultrasonic bonding. In addition, the solder layer 29 on the surface of the copper plate 27a is provided by previously performing solder plating or the like on a part or the entire surface of the patterned copper plate 27a, so that the semiconductor element 28 and the circuit board piece 52 are fixed. In particular, they can be fixed without supplying solder.
【００２４】このような構成のものでは、金属ベース２
２の上面に半田層により固着されたＤＢＣ２３の所定パ
ターンを有する銅板２７ａに半田層２９によって半導体
素子２８を搭載させたり、あるいは電極端子３０、回路
基板片５２等を固着させたりする際、銅板２７ａの酸化
防止対策として半田接続時の雰囲気を還元雰囲気にする
ようなこともなく、また、特に銅板２７ａの上面に対す
る半田流れ防止の対策も行うことなく搭載や固着が実行
される。そして搭載された半導体素子２８の端子と回路
基板片５２の対応するボンディングパッド４５に、金属
細線３２が超音波ボンディングによって固着され、半導
体素子２８の端子と回路基板片５２のボンディングパッ
ド４５とが導通するよう接続される。この金属細線３２
の超音波ボンディングによる固着を行う際、回路基板片
５２のボンディングパッド４５が金めっき面となってい
ることにより、超音波ボンディング部分は良好な固着が
行われたものとなる。In such a configuration, the metal base 2
When the semiconductor element 28 is mounted by the solder layer 29 on the copper plate 27a having a predetermined pattern of the DBC 23 fixed on the upper surface of the substrate 2 by the solder layer, or when the electrode terminals 30, the circuit board pieces 52, and the like are fixed, the copper plate 27a As a countermeasure against oxidation, mounting and fixing are performed without setting the atmosphere at the time of solder connection to a reducing atmosphere, and without taking measures to prevent solder flow, particularly on the upper surface of the copper plate 27a. Then, the thin metal wire 32 is fixed to the terminal of the mounted semiconductor element 28 and the corresponding bonding pad 45 of the circuit board piece 52 by ultrasonic bonding, and the terminal of the semiconductor element 28 and the bonding pad 45 of the circuit board piece 52 are electrically connected. To be connected. This thin metal wire 32
When performing the bonding by ultrasonic bonding, the bonding pad 45 of the circuit board piece 52 is a gold plated surface, so that the ultrasonic bonding portion is well bonded.
【００２５】この結果、第１の実施形態と同様に、還元
雰囲気にしたり、ＤＢＣ表面の銅板の表面全面にニッケ
ルめっき等のめっき処理を施すといった酸化防止対策を
行わなくても、また超音波ボンディングを行おうとする
部分への半田流れ防止の対策を行わなくても、金属細線
３２の超音波ボンディングによる固着を行うことがで
き、半導体素子２８の端子と対応する回路基板片５２の
ボンディングパッド４５とを金属細線３２によって容易
かつ簡単に接続することができる。さらに、予め銅板２
７ａに半田層２９を設けておくことにより、銅板２７ａ
の酸化が防止され、また半導体素子２８や回路基板片５
２等の固着を簡単に行うことができる。As a result, similarly to the first embodiment, it is possible to use an ultrasonic bonding without taking measures to prevent oxidation such as a reducing atmosphere or plating treatment such as nickel plating on the entire surface of the copper plate on the DBC surface. The bonding of the thin metal wires 32 by ultrasonic bonding can be performed without taking measures to prevent the flow of solder to the portion where the soldering is to be performed. Can be easily and easily connected by the thin metal wire 32. Furthermore, the copper plate 2
By providing the solder layer 29 on the copper plate 27a,
Of the semiconductor element 28 and the circuit board piece 5 are prevented.
2 can be easily fixed.
【００２６】なお、上記の第２及び第３の実施形態では
回路基板片４２，５２のボンディングパッド４５に金め
っきを施しているが、半田付けの雰囲気温度程度の温度
では酸化膜が形成され難く、かつめっき表面に超音波ボ
ンディングが可能なめっき処理、例えばニッケルめっき
等を用いてもよい。また回路基板片４２，５２の基板を
ガラスエポキシ樹脂板４３としたが、基板にフェノール
樹脂板を用い、その上面に導体薄板の薄銅板４４，５３
を被着し、これを所定回路パターンとなるようパターニ
ングするようにしたものでもよい。Although the bonding pads 45 of the circuit board pieces 42 and 52 are plated with gold in the second and third embodiments, an oxide film is not easily formed at a temperature around the soldering ambient temperature. Alternatively, a plating process capable of performing ultrasonic bonding on the plating surface, for example, nickel plating may be used. Although the circuit board pieces 42 and 52 are made of a glass epoxy resin plate 43, a phenol resin plate is used as the substrate, and thin copper plates 44 and 53 of conductive thin plates are formed on the upper surface thereof.
May be applied, and this may be patterned into a predetermined circuit pattern.
【００２７】[0027]
【発明の効果】以上の説明から明らかなように、本発明
によればダイ・ボンディング等の際の酸化防止が不要に
なり、また半田流れ防止の対策が不要となって製造工程
の自由度が増し簡単に製造することができ、製造性が良
好になる等の効果を奏する。As is apparent from the above description, according to the present invention, it is not necessary to prevent oxidation at the time of die bonding or the like, and it is not necessary to take measures for preventing solder flow, thereby increasing the flexibility of the manufacturing process. It can be manufactured more easily and has effects such as improved manufacturability.
【図１】本発明の第１の実施形態を示す断面図である。FIG. 1 is a cross-sectional view illustrating a first embodiment of the present invention.
【図２】本発明の第１の実施形態におけるケースを取り
外して示す斜視図である。FIG. 2 is a perspective view of the first embodiment of the present invention with a case removed.
【図３】本発明の第２の実施形態におけるケースを取り
外した要部の斜視図である。FIG. 3 is a perspective view of a main part with a case removed in a second embodiment of the present invention.
【図４】本発明の第３の実施形態におけるケースを取り
外した要部の斜視図である。FIG. 4 is a perspective view of a main part with a case removed in a third embodiment of the present invention.
【図５】従来例を示す断面図である。FIG. 5 is a sectional view showing a conventional example.
【図６】従来例におけるケースを取り外して示す斜視図
である。FIG. 6 is a perspective view showing a conventional example with a case removed.
２２…金属ベース ２３…ＤＢＣ ２４，２９…半田層 ２７ａ，２７ｂ…銅板 ２８…半導体素子 ３１…金属端子片 ３２…金属細線 ３３…超音波ボンディング部分 ４２，５２…回路基板片 ４５…ボンディングパッド Reference Signs List 22 metal base 23 DBC 24, 29 solder layer 27a, 27b copper plate 28 semiconductor element 31 metal terminal piece 32 thin metal wire 33 ultrasonic bonding portion 42, 52 circuit board piece 45 bonding pad
Claims (8)
この絶縁基板の上面に被着された導体薄板をパターニン
グすることによって形成された複数の導体パターン部
と、この導体パターン部の少なくとも１つに半田付けに
より固定され載置された半導体素子と、前記導体パター
ン部に半田付けにより固着された所定のめっき処理が施
された金属端子片と、この金属端子片と前記半導体素子
とにボンディングされた金属細線とを備えてなることを
特徴とする半導体装置。An insulating substrate fixed on a metal base;
A plurality of conductor pattern portions formed by patterning a conductor thin plate adhered to the upper surface of the insulating substrate; a semiconductor element fixed and mounted on at least one of the conductor pattern portions by soldering; A semiconductor device comprising: a metal terminal piece fixed to a conductor pattern portion by soldering and subjected to a predetermined plating process; and a thin metal wire bonded to the metal terminal piece and the semiconductor element. .
ッケルめっきあるいは金めっきであることを特徴とする
請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the plating applied to the metal terminal piece is nickel plating or gold plating.
ボンディングが、超音波ボンディングによって行われて
いることを特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the bonding of the thin metal wire to the metal terminal piece and the semiconductor element is performed by ultrasonic bonding.
この絶縁基板の上面に被着された導体薄板をパターニン
グすることによって形成された複数の導体パターン部
と、この導体パターン部の少なくとも１つに半田付けに
より固定されて載置された半導体素子と、前記導体パタ
ーン部の他の少なくとも１つに半田付けにより固着され
た導体薄板によって所定回路パターンが形成された回路
基板片と、この回路基板片の前記回路パターンと前記半
導体素子とにボンディングされた金属細線とを備えてな
ることを特徴とする半導体装置。4. An insulating substrate fixed on a metal base,
A plurality of conductor pattern portions formed by patterning a conductor thin plate adhered to the upper surface of the insulating substrate; a semiconductor element fixed and mounted on at least one of the conductor pattern portions by soldering; A circuit board piece having a predetermined circuit pattern formed by a conductive thin plate fixed to at least one other of the conductor pattern portions by soldering, and a metal bonded to the circuit pattern and the semiconductor element of the circuit board piece A semiconductor device comprising a thin wire.
るいはフェノール樹脂板の表面に銅薄板によりなる回路
パターンが形成されたものであることを特徴とする請求
項４記載の半導体装置。5. The semiconductor device according to claim 4, wherein the circuit board piece is formed by forming a circuit pattern of a thin copper plate on a surface of a glass epoxy resin plate or a phenol resin plate.
への金属細線のボンディングが、超音波ボンディングに
よって行われていることを特徴とする請求項４記載の半
導体装置。6. The semiconductor device according to claim 4, wherein the bonding of the thin metal wire to the circuit pattern of the circuit board piece and the semiconductor element is performed by ultrasonic bonding.
ていることを特徴とする請求項１あるいは請求項４記載
の半導体装置。7. The semiconductor device according to claim 1, wherein the conductor pattern portion is formed of a copper plate.
成されていることを特徴とする請求項１あるいは請求項
４記載の半導体装置。8. The semiconductor device according to claim 1, wherein the conductor pattern portion has a solder layer formed on the entire surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15681696A JPH104167A (en) | 1996-06-18 | 1996-06-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15681696A JPH104167A (en) | 1996-06-18 | 1996-06-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH104167A true JPH104167A (en) | 1998-01-06 |
Family
ID=15635969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15681696A Pending JPH104167A (en) | 1996-06-18 | 1996-06-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH104167A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003031767A (en) * | 2001-07-18 | 2003-01-31 | Fuji Electric Co Ltd | Semiconductor device |
| JP2009064635A (en) * | 2007-09-05 | 2009-03-26 | Toyota Industries Corp | Terminal, and fixing method of terminal |
| CN116936485A (en) * | 2020-10-14 | 2023-10-24 | 罗姆股份有限公司 | Semiconductor module |
| US11955451B2 (en) | 2020-10-14 | 2024-04-09 | Rohm Co., Ltd. | Semiconductor module |
| US11961790B2 (en) | 2020-10-14 | 2024-04-16 | Rohm Co., Ltd. | Semiconductor module |
| EP2546869B1 (en) * | 2010-12-03 | 2024-08-28 | Fuji Electric Co., Ltd. | Semiconductor device with wire members acting as stems against flow of bonding material and corresponding manufacturing process |
-
1996
- 1996-06-18 JP JP15681696A patent/JPH104167A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003031767A (en) * | 2001-07-18 | 2003-01-31 | Fuji Electric Co Ltd | Semiconductor device |
| JP2009064635A (en) * | 2007-09-05 | 2009-03-26 | Toyota Industries Corp | Terminal, and fixing method of terminal |
| EP2546869B1 (en) * | 2010-12-03 | 2024-08-28 | Fuji Electric Co., Ltd. | Semiconductor device with wire members acting as stems against flow of bonding material and corresponding manufacturing process |
| CN116936485A (en) * | 2020-10-14 | 2023-10-24 | 罗姆股份有限公司 | Semiconductor module |
| US11955451B2 (en) | 2020-10-14 | 2024-04-09 | Rohm Co., Ltd. | Semiconductor module |
| US11955414B2 (en) | 2020-10-14 | 2024-04-09 | Rohm Co., Ltd. | Semiconductor module |
| US11955452B2 (en) | 2020-10-14 | 2024-04-09 | Rohm Co., Ltd. | Semiconductor module |
| US11955413B2 (en) | 2020-10-14 | 2024-04-09 | Rohm Co., Ltd. | Semiconductor module |
| US11961790B2 (en) | 2020-10-14 | 2024-04-16 | Rohm Co., Ltd. | Semiconductor module |
| US12057426B2 (en) | 2020-10-14 | 2024-08-06 | Rohm Co., Ltd. | Semiconductor module |
| US12068230B2 (en) | 2020-10-14 | 2024-08-20 | Rohm Co., Ltd. | Semiconductor module |
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