JP2007027654A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that improves its effective area rate. <P>SOLUTION: The semiconductor device has a semiconductor substrate having a first area where an active element is provided at a specified position on the semiconductor substrate, and a second area for external connection which is disposed around the first area and provided on the semiconductor substrate; a plating film which is electrically connected to an electrode of the active element and provided so that the reverse surface of the second area is a mount surface; an insulating adhesive resin layer covering the top surface of the first area and the surface of the second area in one body; and a wiring line which is provided on the top surface of the insulating adhesive resin layer, and electrically connects the electrode of the active element to an electrode disposed on the top surface of the second area. Consequently, the need for a metallic lead terminal connected to an external electrode and a sealing mold for protection is eliminated and the outward appearance size can be made extremely small. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

      The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved mounting effective area ratio expressed by a ratio between a chip area of the semiconductor device and a mounting area where the semiconductor device is mounted on a mounting substrate such as a printed circuit board.

  In general, a semiconductor device in which a transistor element is formed on a silicon substrate is mainly configured as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.

  As shown in FIG. 5, the transistor element formed on the silicon substrate 11 has a base region formed by, for example, diffusing a P-type impurity such as boron into the N-type epitaxial layer 12 serving as a collector region in the N-type silicon substrate 11. 13 is formed, and an emitter region 14 is formed by diffusing N-type impurities such as phosphorus in the base region 13. An insulating film 15 having openings for exposing portions of the base region 13 and the emitter region 14 is formed on the surface of the silicon substrate 11, and a metal such as aluminum is deposited on the exposed base region 13 and emitter region 14. Then, the base electrode 16 and the emitter electrode 17 are formed. In the transistor having such a configuration, the silicon substrate serves as the collector electrode 18.

  As described above, the silicon substrate 1 on which the transistor element is formed is fixedly mounted on an island 2 such as a copper-based heat sink via a brazing material 5 such as solder, as shown in FIG. A base electrode and an emitter electrode of the transistor element are electrically connected to the lead terminals 3 arranged in the periphery by wires by wire bonding. The lead terminal connected to the collector electrode is formed integrally with the island, and after being electrically connected by mounting the silicon substrate on the island, transfer molding with a thermosetting resin 4 such as epoxy resin, A semiconductor device having a three-terminal structure in which a silicon substrate and a part of a lead terminal are completely covered and protected is provided.

  A resin-molded semiconductor device is usually mounted on a mounting substrate such as a glass epoxy substrate, and is electrically connected to other semiconductor devices and circuit elements mounted on the mounting substrate to perform a predetermined circuit operation. Treated as a part.

  FIG. 7 shows a cross-sectional view when a semiconductor device is mounted on a mounting substrate. 20 is a semiconductor device, 21 and 23 are base or emitter electrode lead terminals, 22 is a collector lead terminal, and 30 is a mounting substrate. It is.

  A mounting area where the semiconductor device 20 is mounted on the mounting substrate 30 is represented by a region surrounded by lead terminals 21, 22, and 23 and conductive pads connected to the lead terminals. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, and most of the mounting area is taken by the mold resin and the lead terminal as compared with the area of the semiconductor chip that actually has a function.

  Here, it is confirmed that the effective area ratio is extremely low in the resin-molded semiconductor device when the effective area ratio is considered as the ratio between the actually functioning semiconductor chip area and the mounting area. The low effective area ratio means that when the semiconductor device 20 is connected to other circuit elements on the mounting substrate 30, most of the mounting area becomes a dead space that is not directly related to a functioning semiconductor chip. If the effective area ratio is small, the dead space is increased on the mounting substrate 30 as described above, which hinders high-density downsizing of the mounting substrate 30.

  This problem is particularly noticeable in a semiconductor device having a small package size. For example, the maximum size of a semiconductor chip mounted on the outer shape of the SC-75A, which is an EIAJ standard, is 0.40 mm × 0.40 mm as shown in FIG. When this semiconductor chip is connected to a metal lead terminal with a wire and resin-molded, the overall size of the semiconductor device is 1.6 mm × 1.6 mm. The chip area of this semiconductor device is 0.16 mm, and the mounting area for mounting the semiconductor device is 2.56 mm, assuming that it is almost the same as the area of the semiconductor device. Therefore, the effective area ratio of this semiconductor device is about 6.25. Therefore, most of the mounting area is a dead space not directly related to the area of the functioning semiconductor chip.

  This problem regarding the effective area ratio is particularly noticeable in a semiconductor device having a very small package size and a large chip size as described above, but the semiconductor chip is wire-connected with a metal lead terminal, resin-molded, and resin-encapsulated. A similar problem arises in the case of a type semiconductor device.

  Mounting boards used in recent electronic devices, for example, portable information processing devices such as personal computers and electronic notebooks, 8 mm video cameras, mobile phones, cameras, liquid crystal televisions, etc. The mounting substrate used is also in the trend of high density and miniaturization.

  However, in the above-described prior art resin-encapsulated semiconductor device, as described above, since the mounting area for mounting the semiconductor device has a large dead space, there is a limit to downsizing of the mounting substrate, and downsizing of the mounting substrate. Was one of the obstacles.

  By the way, there is JP-A-3-248551 as a prior art for improving the effective area ratio. This prior art will be briefly described with reference to FIG. In this prior art, lead terminals 41, 42, and 43 connected to the base, emitter, and collector electrodes of the semiconductor chip 40 are provided in order to minimize the mounting area when the resin mold type semiconductor device is mounted on a mounting substrate or the like. It is described that the lead terminals 41, 42, 43 are formed so as to be flush with the side surface of the resin mold 44 without being led out from the side surface of the resin mold 44.

  According to this configuration, the mounting area can be reduced by an amount that does not lead out the leading end portions of the lead terminals 41, 42, and 43, and the effective area ratio can be slightly improved, but the size of the dead space is greatly improved. Not.

  In order to improve the effective area ratio, it is necessary to make the semiconductor chip area and mounting area of the semiconductor device substantially the same. In the resin mold type semiconductor device, as in this prior art, the tip of the lead terminal Even if the part is not derived, it is difficult to improve the effective area ratio due to the presence of the mold resin.

  Further, in the above semiconductor device, the lead terminal to be connected to the semiconductor chip and the mold resin are indispensable, and therefore, a process of wire connection process between the semiconductor chip and the lead terminal and an injection molding process of the mold resin are required. There is a problem that the cost and the manufacturing process are complicated, and the manufacturing cost cannot be reduced.

  In order to maximize the effective area ratio, as described above, by mounting the semiconductor chip directly on the mounting substrate, the area of the semiconductor chip and the mounting area are almost the same, and the effective area ratio is maximized.

  As one prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-6-338504, a flip chip in which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 is used as a mounting substrate. A technique for 47 face down bonding is known (see FIG. 9). In this prior art, a gate (base) electrode, a source (emitter) electrode, and a drain (collector) electrode are usually formed on the same main surface of a silicon substrate such as a MOSFET, and a current or voltage path is formed in a horizontal direction. It is mainly used for horizontal semiconductor devices that generate a relatively small amount of heat.

  However, in a vertical semiconductor device such as a transistor device where a silicon substrate is one of the electrodes and each electrode is formed on a different surface and the current path flows in the vertical direction, the above-described flip chip technology is not used. Have difficulty.

  As another prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in Japanese Patent Laid-Open No. 7-38334, a semiconductor chip 53 is formed on a conductive pattern 52 formed on a mounting substrate 51. A technique for bonding and connecting electrodes of the conductive pattern 52 and the semiconductor chip 53 arranged around the semiconductor chip 53 with a wire 54 is known (see FIG. 10). This prior art can be used for a semiconductor chip such as a transistor having a vertical structure in which the above-described silicon substrate constitutes one electrode.

  Since the wire 54 that connects the semiconductor chip 53 and the conductive pattern 52 disposed around the semiconductor chip 53 is usually a gold fine wire, the peel strength (tensile force) of the bonding joint that is bonded to the gold fine wire is increased. Therefore, it is preferable to perform bonding in a heated atmosphere of about 200 ° C. to 300 ° C. However, when die-bonding a semiconductor chip on an insulating resin-based mounting substrate, the mounting substrate is distorted when heated to the above temperature, and chip capacitors, chip resistors, etc. mounted on the mounting substrate Since the solder for fixing the other circuit elements melts, the wire bonding connection is performed at a heating temperature of about 100 ° C. to 150 ° C., and thus there is a problem that the peel strength of the bonding joint is lowered. .

  In this prior art, since the die-bonded semiconductor chip is usually covered and protected with a thermosetting resin such as an epoxy resin, the reduction in peel strength is caused by the shrinkage during the thermosetting of the epoxy resin and the joint part is peeled off. There is a problem that.

  The present invention has been made in view of the above-described circumstances, and the present invention does not require a lead terminal connected to a semiconductor chip and a mold resin, and a semiconductor chip area and a mounting area mounted on a mounting substrate. The effective area ratio, which is a ratio of the above, is maximally improved, and a semiconductor device with a reduced dead space of a mounting area is provided.

The present invention employs the following configuration in order to solve the above problems.
First, a semiconductor device in which the back surface of the semiconductor substrate is a mounting surface, and a metal lead terminal used for electrical connection with the outside and a protective mold are unnecessary,
A semiconductor substrate comprising: a first region in which an active element is provided at a predetermined position of the semiconductor substrate; and a second region for external connection provided in a semiconductor substrate located around the first region. When,
A plating film that is electrically connected to the electrode of the active element and is provided to make the back surface of the second region the mounting surface;
An insulating adhesive resin layer integrally covering the surface of the first region and the surface of the second region;
The problem is solved by having a wiring provided on the surface of the insulating adhesive resin layer and electrically connecting the electrode of the active element and the electrode located on the surface of the second region.
Second, the problem is solved by providing a resin on the surface of the insulating adhesive resin layer provided with the wiring so as to cover and protect the wiring.
Third, a plurality of the plating films are provided so as to sandwich the first region, and the plurality of plating films are arranged on the same plane.
As a result, unlike the conventional semiconductor device, a metal lead terminal connected to the external electrode and a protective sealing mold are unnecessary, and the external dimensions of the semiconductor device can be significantly reduced.

Adopting the above structure eliminates the need for metal lead terminals and protective sealing molds that connect to external electrodes, as in conventional semiconductor devices, and significantly reduces the external dimensions of semiconductor devices. Can do.

  Hereinafter, embodiments of the semiconductor device of the present invention will be described.

  As shown in FIG. 1, the semiconductor device of the present invention includes a semiconductor substrate 60, an active element formation region 61 in which an active element is formed, and one electrode of the active element formed in the active element formation region 61. One external connection electrode 62 for external connection, and other external connection electrodes 63 and 64 that are electrically separated from the active element formation region 61 and use a part of the substrate 60 as an external electrode of another electrode of the active element. And a connecting means 65 for connecting the other electrode of the active element and the other external connection electrodes 63 and 64.

  The semiconductor substrate 60 is an N + type single crystal silicon substrate, and an N − type epitaxial layer 66 is formed on the substrate 60 by an epitaxial growth technique. In a predetermined region of the semiconductor substrate 60, active elements such as power MOSs and transistors are formed, and an active element forming region 61 and external connection electrode regions 63A and 64A which are connected to the electrodes of the active elements and become external connection electrodes 63 and 64 are provided. ing.

  The active element described above is formed in the active element formation region 61. Here, a transistor having an N− type epitaxial layer as a collector region 66A is formed. A photoresist is formed on the active element formation region 61, and P-type impurities such as boron (B) are selectively thermally diffused into the region exposed by the photoresist to form an island-shaped base region 71 having a predetermined depth. Is formed.

  After the base region 71 is formed, a photoresist is formed again on the active element forming region 61, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively thermally diffused in the base region 71 exposed by the photoresist. Thus, the emitter region 72 of the transistor is formed. When the emitter region 72 is formed, an N + type diffusion region 73 for a ring-shaped guard ring surrounding the base region 71 may be formed.

  An insulating film 74 such as a silicon oxide film or a silicon nitride film having a base contact hole exposing the surface of the base region 71 and an emitter contact hole exposing the surface of the emitter region 72 is formed on the surface of the semiconductor substrate 60. When the guard ring diffusion region 73 is formed, the guard ring contact hole exposing the surface of the diffusion region 73 is formed. The insulating film 74 is also formed on the electrode regions 63A and 64A serving as external connection electrodes, and external connection contact holes are formed to expose the surfaces of the electrode regions 63A and 64A.

  On the base region 71, the emitter region 72, the electrode regions 63A and 64A, and the guard ring diffusion region 73 exposed by the base contact hole, the emitter contact hole, the external connection contact hole and the guard ring contact hole, aluminum or the like is selectively formed. A base electrode 75, an emitter electrode 76, and a connection electrode 77 deposited with the above metal material are formed.

  The active element formation region 61 and the external connection electrode regions 63A and 64A can be formed in a predetermined arbitrary region of the semiconductor substrate 60. In this embodiment, as shown in FIG. An element formation region 61 is formed, and external connection electrode regions 63A and 64A are formed so as to have a triangle shape with the region 61 interposed therebetween.

  A silicon-based, epoxy-based or polyimide-based insulating adhesive resin layer 78 is formed on the surface of the semiconductor substrate 60 having the active element forming region 61 where the transistors are formed and the external connection electrode regions 63A, 64A. The connection means 65 formed on the resin layer 78 electrically connects the transistor base electrode 75 and emitter electrode 76 to the external connection electrode regions 63A and 64A.

  As described above, the resin layer 78 insulates the connection means 65 for connecting the base electrode 71 and the emitter electrode 72 of the transistor and the external connection electrode regions 63A and 64A from the substrate, and connects to the active element formation region 61. When the electrode regions 63A, 64A are electrically separated, both the regions 61, 63A, 64A are formed to be integrally supported without being completely divided. The resin layer 78 only needs to have adhesiveness and insulation, and for example, a polyimide resin is used.

  The surface of the substrate 60 is coated with, for example, a polyimide resin having a thickness of 2 to 50 μm by a spinner and baked for a predetermined time, and then the surface is polished to form a flattened resin layer. The base layer 71 of the transistor formed in the active element formation region 61, the emitter electrode 72, and the resin layer 78 on the connection electrode 77 formed in the external connection electrode regions 63A and 64A are selectively removed scientifically or mechanically. The contact holes thus formed are formed, and the surfaces of the base electrode 71, the emitter electrode 72, and the connection electrodes 663 and 64 are exposed.

  The exposed base electrode 71 and the connection electrode 64, and the emitter electrode 72 and the connection electrode 63 are electrically connected by connection means 65 made of a metal film such as aluminum or copper. For example, the connection means 65 forms a resist mask patterned in the pattern shape of the connection means 65 for connecting the contact hole and each electrode on the resin layer 78 in which the contact hole is formed, and the resist mask is formed on the resist mask. If a metal such as aluminum is deposited and the resist mask is removed, the connection means 65 having a predetermined pattern shape is selectively formed on the resin layer 78, and the base electrode 71, the connection electrode 64, and the emitter electrode 72 are connected. The electrode 63 is electrically connected. The resin layer 78 on which the connecting means 65 is formed is covered with a silicon-based, epoxy-based, or polyimide-based adhesive resin 79 to protect the connecting means 65 from the outside.

  The active element formation region 61 and the external connection electrode regions 63A and 64A formed on the same substrate 1 are electrically separated from each other by the slit holes 80 formed from the back side of the substrate 60. 63A and 64A become the external connection electrodes 62, 63 and 64 of the transistor.

  That is, the substrate 60 in the active element formation region 61 is the external connection electrode 62 for the collector electrode of the transistor, the substrate 60 in the one external connection electrode region 64A is the external connection electrode 64 for the base electrode of the transistor, and other external connection electrodes. The substrate 60 in the connection electrode region 63A becomes the external connection electrode 63 for the emitter electrode of the transistor. The same semiconductor substrate 60 is used, and the external connection electrodes 62, 63, 64 of each electrode of the transistor are formed on the same plane. Will be formed.

  As described above, the slit hole 80 for electrically separating the external connection electrodes 62, 63, 64 is formed so as to reach the resin layer 78 from the back surface side of the semiconductor substrate 60. For example, an ion beam, a laser, etc. Is formed by a chemical method using dry etching, wet etching, or a mechanical method using a dicing blade by a dicing apparatus. The slit hole 80 can be formed by any of the above methods.

  What is important here is that if the depth of the slit hole 80 becomes shallow, the electrical connection between the external connection electrodes 62, 63, 64 is not sufficiently performed, and a short circuit failure occurs. The front end portion (bottom portion) of the slit hole 80 is formed so as to be within the resin layer 78 by about 2 μ to 6 μ so that 63 and 64 are completely electrically separated. The external connection electrodes 62, 63, 64 are completely separated and partitioned by the slit hole 80, but are supported and fixed on the same plane by the resin layer 78. In addition, a plating layer such as solder plating is formed on the surface of the substrate 60 to be the external connection electrodes 62, 63, 64, so that the solder connection with the conductive pattern formed on the mounting substrate is improved.

  A semiconductor device in which a slit hole 80 is provided in a semiconductor substrate 60 and the external connection electrodes 62, 63, 64 of the transistor are electrically separated includes a ceramic substrate, a glass epoxy substrate, a phenol substrate, and a metal substrate subjected to insulation treatment. It is fixedly mounted on a pad of a conductive pattern formed on a mounting substrate such as. A solder layer in which solder cream is pre-printed is formed on the pad, and the semiconductor device can be fixedly mounted on the pad of the mounting substrate by melting the solder and mounting the semiconductor device of the present invention. . Although not shown, this fixed mounting process can be performed in the same process as the mounting process of other circuit elements to be mounted by solder such as chip capacitors and chip resistors mounted on the mounting substrate.

  Further, when the semiconductor device of the present invention is mounted on the mounting board, the external connection electrodes 62, 63, 64 are separated by the interval of the slit holes 80, so that the solder to be fixed to the mounting board is disposed adjacently. The external connection electrodes 62, 63, 64 are not short-circuited.

  By the way, as shown in FIG. 2, in the semiconductor device of the present embodiment, for example, an active element active element forming region 61 having substantially the same function as the semiconductor device described in the conventional example is 0.5 mm × 0.5 mm in size, In the semiconductor device in which the connection electrode regions 63A and 64A serving as the emitter electrodes are 0.3 mm × 0.2 mm in size and the width of the slit hole 80 is 0.1 mm, the effective area ratio is as follows. That is, the element area is 0.25 mm, and the area of the semiconductor device as the mounting area is 1.28 mm, so that the effective area ratio is about 19.53%.

  Since the effective area ratio of the semiconductor device having the chip size of 0.40 mm × 0.40 mm described in the conventional example is 6.25% as described above, the effective area ratio of the semiconductor device of the present invention is about 3.12 times. It becomes large, the dead space of the mounting area mounted on the mounting substrate can be reduced, and it can contribute to the miniaturization of the mounting substrate.

  In the present embodiment, the external connection electrodes 62, 63, and 64 are arranged so as to form a triangle in consideration of the ease of connection with the mounting board. However, if the external connection electrodes 62, 63, and 64 are arranged on a straight line, The unused area on the semiconductor substrate 1 can be eliminated, and the effective area ratio can be further improved.

  As described above, according to the present invention, a portion of the semiconductor substrate 60 that is electrically isolated from the active element formation region 61 in which the transistor having the semiconductor substrate 60 as the external connection electrode 62 for the collector electrode is formed on the semiconductor substrate 60. Are used as the base electrode 75 of the transistor and the external connection electrodes 63 and 64 for the emitter electrode 76, so that a metal lead terminal connected to the external electrode and a protective sealing mold are provided as in the conventional semiconductor device. It becomes unnecessary, the external dimensions of the semiconductor device can be remarkably reduced, and the effective area ratio can be increased.

  In the present embodiment, the transistor is formed in the active element formation region 61. However, the transistor is not limited to this as long as it is a vertical type or a horizontal type device with a relatively small amount of heat generation. Needless to say, the invention can be applied.

  By the way, in the above embodiment, the connection means 65 forms the metal wiring pattern on the resin layer 78. However, in addition to the metal wiring, the connection electrode 77 of the base electrode 75 and the external connection electrode 64 is shown in FIG. The emitter electrode 76 and the connection electrode 77 of the external connection electrode 63 may be connected by wire bonding using a wire 91 such as aluminum or gold. After the connection with the wire line 91, an insulating resin 92 such as epoxy or polyimide resin is formed on the surface, and the wire line 91 is protected.

  In the embodiment of FIG. 3, the base electrode 75 and the connection electrode 77 of the external connection electrode 64 are connected by the wire wire 91, and the emitter electrode 76 and the connection electrode 77 of the external connection electrode 63 are connected. After covering protection, a slit hole 80 is formed in the substrate 60 to separate the external connection electrodes 62, 63, 64 of the transistor. In this embodiment, since the base electrode 75 and the connection electrode 77 of the external connection electrode 64 and the emitter electrode 76 and the connection electrode 77 of the external connection electrode 63 can be connected by bonding, the process can be simplified.

  As described in detail above, according to the semiconductor device of the present invention, an active element forming region in which a transistor having the semiconductor substrate 1 as an external connection electrode for an emitter electrode is formed on the semiconductor substrate 1, and the active element forming region. A portion of the semiconductor substrate 1 that is electrically isolated from the semiconductor substrate 1 is used as an external connection electrode for a transistor base electrode and an emitter electrode, so that a metal lead terminal connected to the external electrode can be protected as in a conventional semiconductor device. It is possible to provide a semiconductor device that does not require a sealing mold for use. As a result, the external dimensions of the semiconductor device can be significantly reduced, unnecessary dead space when mounted on the mounting substrate can be eliminated, and the mounting substrate can be greatly reduced in size.

  Further, in the semiconductor device of the present invention, as described above, the metal lead terminal for external connection and the resin sealing mold are unnecessary, and therefore the manufacturing cost of the semiconductor device can be significantly reduced.

Sectional drawing which shows the semiconductor device of this invention. The figure which shows the back surface of the semiconductor device of this invention. Sectional drawing which shows the semiconductor device of this invention. Sectional drawing which shows the conventional semiconductor device. Sectional drawing of a general transistor. Sectional drawing which mounted the conventional semiconductor device on the mounting substrate. The top view of the conventional semiconductor device. The top view of the conventional semiconductor device. The figure which shows the conventional semiconductor device. The figure which shows the conventional semiconductor device.

Claims (3)

It is a semiconductor device in which the back surface of the semiconductor substrate is a mounting surface, and metal lead terminals used for electrical connection with the outside and a protective mold are unnecessary.
A semiconductor substrate comprising: a first region in which an active element is provided at a predetermined position of the semiconductor substrate; and a second region for external connection provided in a semiconductor substrate located around the first region. When,
A plating film that is electrically connected to the electrode of the active element and is provided to make the back surface of the second region the mounting surface;
An insulating adhesive resin layer integrally covering the surface of the first region and the surface of the second region;
A semiconductor device comprising a wiring provided on a surface of the insulating adhesive resin layer and electrically connecting an electrode of the active element and an electrode positioned on the surface of the second region. The semiconductor device according to claim 1, wherein a resin is provided on a surface of the insulating adhesive resin layer provided with the wiring so as to cover and protect the wiring. The semiconductor device according to claim 1, wherein a plurality of the plating films are provided so as to sandwich the first region, and the plurality of plating films are arranged on the same plane.