JP3639390B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP3639390B2
JP3639390B2 JP27494396A JP27494396A JP3639390B2 JP 3639390 B2 JP3639390 B2 JP 3639390B2 JP 27494396 A JP27494396 A JP 27494396A JP 27494396 A JP27494396 A JP 27494396A JP 3639390 B2 JP3639390 B2 JP 3639390B2
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semiconductor
semiconductor device
semiconductor chip
chips
substrate
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JPH10125855A (en
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治雄 兵藤
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/181—Encapsulation

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Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置に関し、特に、半導体装置のチップ面積と、半導体装置をプリント基板等の実装基板上に実装する実装面積との比率で表す実装有効面積率を向上させた半導体装置に関する。
【０００２】
【従来の技術】
一般的にシリコン基板上にトランジスタ素子が形成された半導体装置は、図９に示すような構成が主に用いられる。１はシリコン基板、２はシリコン基板１が実装される放熱板等のアイランド、３はリード端子、及び４は封止用の樹脂モールドである。
【０００３】
シリコン基板１１に形成されるトランジスタ素子は、図３に示すように、例えば、Ｎ型シリコン基板１１にコレクタ領域となるＮ型のエピタキシャル層１２にボロン等のＰ型の不純物を拡散してベース領域１３が形成され、そのベース領域１３内にリン等のＮ型の不純物を拡散してエミッタ領域１４が形成される。シリコン基板１１の表面にベース領域１３、エミッタ領域１４の一部を露出させる開口部を有した絶縁膜１５が形成され、その露出されたベース領域１３、エミッタ領域１４上にアルミニウム等の金属が蒸着されベース電極１６、エミッタ電極１７が形成される。このような構成のトランジスタではシリコン基板がコレクタ電極１８となる。
【０００４】
上記のように、トランジスタ素子が形成されたシリコン基板１は、図９に示すように、銅ベースの放熱板等のアイランド２に半田等のろう材５を介して固着実装され、シリコン基板１の周辺に配置されたリード端子３にトランジスタ素子のベース電極、エミッタ電極とがそれぞれワイヤーボンディングによってワイヤーで電気的に接続されている。コレクタ電極に接続されるリード端子はアイランドと一体に形成されており、シリコン基板をアイランド上に実装することで電気的に接続された後、エポキシ樹脂等の熱硬化型樹脂４によりトランスファーモールドによって、シリコン基板とリード端子の一部を完全に被覆保護し、３端子構造の半導体装置が提供される。
【０００５】
【発明が解決しようとする課題】
樹脂モールドされた半導体装置は、通常、ガラスエポキシ基板等の実装基板に実装され、実装基板上に実装された他の半導体装置、回路素子と電気的に接続され所定の回路動作を行うための一部品として取り扱われる。
図１０は、実装基板上に半導体装置を実装したときの断面図を示し、２０は半導体装置、２１、２３はベース又はエミッタ電極用のリード端子、２２はコレクタ用のリード端子、３０は実装基板である。
【０００６】
実装基板３０上に半導体装置２０が実装される実装面積は、リード端子２１、２２、２３とそのリード端子と接続される導電パッドで囲まれた領域によって表される。実装面積は半導体装置２０内のシリコン基板（半導体チップ）面積に比べ大きく、実際に機能を持つ半導体チップの面積に比べ実装面積の殆どはモールド樹脂、リード端子によって取られている。
【０００７】
ここで、実際に機能を持つ半導体チップ面積と実装面積との比率を有効面積率として考慮すると、樹脂モールドされた半導体装置では有効面積率が極めて低いことが確認されている。有効面積率が低いことは、半導体装置２０を実装基板３０上の他の回路素子と接続使用とする場合に、実装面積の殆どが機能を有する半導体チップとは直接関係のないデッドスペースとなる。有効面積率が小さいと上記したように、実装基板３０上でデットスペースが大きくなり、実装基板３０の高密度小型化の妨げとなる。
【０００８】
特に、この問題はパッケージサイズが小さい半導体装置に顕著に現れる。例えば、ＥＩＡＪ規格であるＳＣ−７５Ａ外形に搭載される半導体チップの最大サイズは、図１１に示すように、０．４０mm×０．４０mmが最大である。この半導体チップを金属リード端子とワイヤーで接続し、樹脂モールドすると半導体装置の全体のサイズは、１．６mm×１．６mmとなる。この半導体装置のチップ面積は０．１６mmで、半導体装置を実装する実装面積は半導体装置の面積とほぼ同様として考えて、２．５６mmであるため、この半導体装置の有効面積率は約６．２５％となり、実装面積の殆どが機能を持つ半導体チップ面積と直接関係のないデットスペースとなっている。
【０００９】
この有効面積率に関する問題は、特に、上記したようにパッケージサイズが極めて小さく、チップサイズが大きい半導体装置において顕著に現れるが、半導体チップを金属リード端子でワイヤー接続し、樹脂モールドする、樹脂封止型の半導体装置であれば同様に問題となる。
近年の電子機器、例えば、パーソナルコンピュータ、電子手帳等の携帯情報処理装置、８ｍｍビデオカメラ、携帯電話、カメラ、液晶テレビ等において用いられる実装基板は、電子機器本体の小型化に伴い、その内部に使用される実装基板も高密度小型化の傾向にある。
【００１０】
しかし、上記の先行技術の樹脂封止型の半導体装置では、上述したように、半導体装置を実装する実装面積にデットスペースが大きいため、実装基板の小型化に限界があり、実装基板の小型化の妨げの一つの要因となっていた。
ところで、有効面積率を向上させる先行技術として特開平３−２４８５５１号公報がある。この先行技術について、図１２にもとずいて簡単に説明する。この先行技術は、樹脂モールド型半導体装置を実装基板等に実装したときの実装面積をできるだけ小さくするために、半導体チップ４０のベース、エミッタ、及びコレクタ電極と接続するリード端子４１、４２、４３を樹脂モールド４４の側面より外側に導出させず、リード端子４１、４２、４３を樹脂モールド４４側面と同一面となるように形成することが記載されている。
【００１１】
この構成によれば、リード端子４１、４２、４３の先端部分が導出しない分だけ実装面積を小さくすることができ、有効面積率を若干向上させることはできる。
しかし、上記の半導体装置では、半導体チップと接続されるリード端子の先端部分は樹脂モールド４４の底面部のコーナー部で折り曲げ加工されるために、その折り曲げ工程時の応力に十分耐えられる構造することから、樹脂モールド内に埋め込まれた各リード端子の長さを十分にしなければならず、結果的に樹脂モールドサイズが実装する半導体チップサイズに比べて大きくなり有効面積率の低下には至らない。さらに、半導体チップと接続される各リード端子を必要とし、材料コスト面及び製造工程が煩雑となり、製造コストを低減できない課題がある。
【００１２】
有効面積率を最大限大きくするには、上記したように、半導体チップを直接実装基板上に実装することにより、半導体チップ面積と実装面積とがほぼ同一となり有効面積率が最大となる。
半導体チップを実装基板等の基板上に実装する一つの先行技術として、例えば、特開平６−３３８５０４号公報に示すように、半導体チップ４５上に複数のバンプ電極４６を形成したフリップチップを実装基板４７上にフェイスダウンボンディングする技術が知られている（図１３参照）。この先行技術は、通常、ＭＯＳＦＥＴ等、シリコン基板の同一主面にゲート（ベース）電極、ソース（エミッタ）電極、ドレイン（コレクタ）電極が形成され、電流或いは電圧のパスが横方向に形成される比較的発熱量の少ない横型の半導体装置に主に用いられる。
【００１３】
しかし、トランジスタデバイス等のようにシリコン基板が電極の一つとなり、各電極が異なる面に形成され電流のパスが縦方向に流れる縦型の半導体装置では、上記のフリップチップ技術を使用することは困難である。
半導体チップを実装基板等の基板上に実装する他の先行技術として、例えば、特開平７−３８３３４号公報に示すように、実装基板５１上に形成された導電パターン５２上に半導体チップ５３をダイボンディングし、半導体チップ５３周辺に配置された導電パターン５２と半導体チップ５３との電極をワイヤ５４で接続する技術が知られている（図１４参照）。この先行技術では、先に述べたシリコン基板が一つの電極を構成した縦型構造のトランジスタ等の半導体チップに用いることはできる。
【００１４】
半導体チップ５３とその周辺に配置された導電パターン５２とを接続するワイヤ５４は通常、金細線が用いられることから、金細線とボンディング接続されるボンディング接合部のピール強度（引張力）を大きくするために、約２００℃〜３００℃の加熱雰囲気中でボンディングを行うことが好ましい。しかし、絶縁樹脂系の実装基板上に半導体チップをダイボンディングする場合には、上記した温度まで加熱すると実装基板に歪みが生じること、及び、実装基板上に実装されたチップコンデンサ、チップ抵抗等の他の回路素子を固着する半田が溶融するために、加熱温度を約１００℃〜１５０℃程度にしてワイヤボンディング接続が行われているため、ボンディング接合部のピール強度が低下する問題がある。
【００１５】
この先行技術では、通常、ダイボンディングされた半導体チップはエポキシ樹脂等の封止用樹脂で被覆保護されるために、ピール強度の低下はエポキシ樹脂の熱硬化時の収縮等によって接合部が剥離されるという問題がある。
本発明は、上述した事情に鑑みて成されたものであり、本発明は、トランジスタ、集積回路が形成された半導体チップを内蔵した複合型の半導体装置の各半導体チップの入出力用の外部接続電極を同一平面上に配置し、各半導体チップの面積と実装基板上に実装される単一の半導体装置の実装面積との比率である有効面積率を最大限向上させ、実装面積のデットスペース最小限小さくした複合型の半導体装置を提供する。
【００１６】
【課題を解決するための手段】
本発明は、上記の課題を解決するために以下の構成及び製造法を採用した。
即ち、本発明の半導体装置は、半導体基板内にトランジスタが形成された第１の半導体チップ及び、集積回路が形成された第２の半導体チップと、前記第１及び第２の半導体チップ表面に設けられ電極パッドと電気的に接続される複数の外部接続手段とを有し、前記第１及び第２の半導体チップは隣接配置されると共に電気的接続が行われ、且つその近傍に配置された前記外部接続手段と電気的接続が行われ、前記外部接続手段及び前記第１及び第２の半導体チップの一主面を露出させて封止用樹脂で固定されたことを特徴としている。
【００１７】
ここで、複数の前記外部接続手段及び前記第１及び第２の半導体チップの一主面は同一平面上に配置されることを特徴としている。
上述したように、本発明の半導体装置によれば、トランジスタが形成された第１の半導体チップと集積回路が形成された第２の半導体チップとを隣接配置し、その各半導体チップの近傍に配置された複数の外部接続手段と第１及び第２の半導体チップとの電気的接続を行い、配線基板等の実装基板上に実装固着するための外部電極となる第１及び第２の半導体チップ及び複数の外部接続手段の一主面を露出させる用に封止用樹脂で固定することにより、従来の半導体装置のように、半導体チップをマウントする外部電極接続用の金属製のリード端子を不要とし、且つ、前記リード端子及び半導体チップの表面電極と接続する他のリード端子が封止モールド樹脂から導出しないために、複数の半導体チップを内蔵した複合型の半導体装置であってもその外観寸法を著しく小型化にすることができる。
【００１８】
【発明の実施の形態】
以下に、本発明の半導体装置の実施形態について説明する。
本発明の半導体装置は、図１に示すように、トランジスタが形成された第１の半導体チップ６１と、集積回路が形成された第２の半導体チップ８１と、半導体チップ６１、８１の表面電極と電気的接続が行われる複数の外部接続手段６２、８２、８３、８４、８５と、第１及び第２の半導体チップ６１、８１と外部接続手段６２、８２、８３、８４、８５とを固定する封止用樹脂１１０とから構成される。
【００１９】
第１の半導体チップ６１はトランジスタが形成されており、例えば、図３に示すように、Ｎ+型の単結晶シリコン基板１１上にエピタキシャル成長技術によりN-型のエピタキシャル層１２が形成され、その半導体基板１１にＮＰＮトランジスタ等の能動素子が形成される。一方、第２の半導体チップ８１には、集積回路が形成されている。
【００２０】
本発明は、特に、第１及び第２の半導体チップ６１、８１の表面及び裏面側に外部接続電極を有する、いわゆる、縦型構造のデバイスに適合する。図３は、先に説明した一般的なＮＰＮトランジスタの断面図であり、例えば、N-型のエピタキシャル層１２をコレクタ領域としたトランジスタを形成したもので、半導体基板１１上にホトレジストを形成し、ホトレジストによって露出された領域にボロン（Ｂ）等のＰ型の不純物を選択的に熱拡散して所定の深さを有した島状のベース領域１３が形成される。
【００２１】
ベース領域１３形成後、半導体基板１１上に再度ホトレジストを形成し、ホトレジストによって露出されたベース領域１３内にリン（Ｐ）、アンチモン（Ｓｂ）等のＮ型の不純物を選択的に熱拡散してトランジスタのエミッタ領域１４が形成される。このエミッタ領域１４を形成する際に、ベース領域１３を囲むリング状のガードリング用のＮ+型の拡散領域を形成しておく場合もある。
【００２２】
半導体基板１１の表面には、ベース領域１３表面を露出するベースコンタクト孔及びエミッタ領域表面を露出するエミッタコンタクト孔を有するシリコン酸化膜、或いはシリコン窒化膜等の絶縁膜１５が形成される。
ベースコンタクト孔、及びエミッタコンタクト孔によって露出されたベース領域１３、エミッタ領域１４上には、選択的にアルミニウム等の金属材料で蒸着されたベース電極１６、エミッタ電極１７及びそれら電極の外部接続用パッド（図示しない）が形成される。半導体基板１１の裏面には、金属メッキ処理が行われ、コレクタ電極１８として用いられる。
【００２３】
第２の半導体チップ８１は、例えば、単結晶のＰ型半導体基板が用いられ、バイポーラＩＣ、ＭＯＳＩＣ等の集積回路が形成される。例えば、図４に示すように、Ｐ型半導体基板に所定形状のフォトマスクを形成し、アンチモン等のＮ型の高濃度不純物を拡散して島状のＮ+型の埋め込みコレクタ領域１０１が形成される。フォトマスクを除去した後、基板１００上にエピタキシャル成長技術によりN-型のエピタキシャル層１０２が形成される。
【００２４】
エピタキシャル層１０２上にアイソレーション拡散領域を露出するマスクを形成し、かかる、アイソレーション拡散領域にボロン等のＰ+型の不純物を拡散してアイソレーション拡散領域１０３が形成される。このアイソレーション拡散領域１０３によりトランジスタの活性領域となるＮ型領域はＰ型の不純物で囲まれる。
【００２５】
エピタキシャル層１０２にホトレジストを形成し、ホトレジストによって露出された領域にボロン（Ｂ）等のＰ型の不純物を選択的に熱拡散して所定の深さを有した島状のベース領域１０４が形成される。
ベース領域１０４形成後、エピタキシャル層１０２上に再度ホトレジストを形成し、ホトレジストによって露出されたベース領域１０４内及びコレクタ領域内にリン（Ｐ）、アンチモン（Ｓｂ）等のＮ型の不純物を選択的に熱拡散してトランジスタのエミッタ領域１０５及びコレクタコンタクト拡散領域１０６が形成される。
【００２６】
ベース領域１０４表面を露出するベースコンタクト孔、エミッタ領域１０５表面を露出するエミッタコンタクト孔及びコレクタコンタクト拡散領域表面を露出するコレクタコンタクト孔を有するシリコン酸化膜、或いはシリコン窒化膜等の絶縁膜１０７が形成される。
ベースコンタクト孔、エミッタコンタクト孔、コレクタコンタクト孔によって露出されたベース領域１０４、エミッタ領域１０６、コレクタコンタクト領域１０７には、選択的にアルミニウム等の金属材料で蒸着されたベース電極１０７、エミッタ電極１０８、コレクタ電極１０９が形成される。
【００２７】
本発明の特徴とするところは、第１及び第２の半導体チップ６１、８１の表面側に設けられた外部接続用電極パッド（ベース電極、エミッタ電極等）を複数のの外部接続手段６２、８２、８３、８４、８５を介して封止用樹脂１１０より導出することなく各半導体チップ６１、８１裏面の外部接続用電極（コレクタ電極、アース電極）と同一面側に配置し、封止用樹脂サイズを最小限、コンパクトにして有効面積率を向上させるところにある。
【００２８】
外部接続手段６２、８２、８３、８４、８５は、第１及び第２の半導体チップ６１、８１表面に設けられたベース、エミッタ等の複数の外部接続用電極パッド数と対応するように各半導体チップ６１、８１の周辺近傍に配置される（図２参照）。外部接続手段６２、８２、８３、８４、８５と第１及び第２の半導体チップ６１、８１のベース、エミッタ用等の電極パッドとは、金又はアルミニウム等の金属細線からなるワイヤにより電気的接続が成され、第１及び第２の半導体チップ６１、８１はこのワイヤによって電気的に接続された状態となる。例えば、図２に示すように、外部接続電極８２には、ワイヤで第１の半導体チップ６１のベース電極と接続し、さらに、第２の半導体チップ８１の電極と接続することで、両半導体チップ６１、８１の接続がなされる。この実施形態では、外部接続電極を介して両チップの接続を行っていが、直接ワイヤで接続できることは説明するまでもない。
【００２９】
外部接続手段６２、８２、８３、８４、８５は銅、インバー、テルル等の金属片又はシリコン材料から成るシリコンチップ等の導電材料から構成されるものであれば特に限定されるものではない。本実施形態では、作業性及びコスト面を考慮し、シリコンチップが用いられている。ワイヤで電気的に接続がなされた半導体チップ６１、８１と外部接続用シリコンチップ６２、８２、８３、８４、８５とはエポキシ樹脂等の熱硬化性の封止用樹脂１１０で固定される。この時、コレクタ電極及びアース電極となる第１及び第２の半導体チップ６１、８１の裏面と、入出力用の電極となる各外部接続用シリコンチップ６２、８２、８３、８４、８５の裏面とは同一平面上に配置される。
【００３０】
上述したように、本発明では、従来の半導体装置のように、半導体チップをマウントする外部電極接続用の金属製のリード端子を不要とし、且つ、そのリード端子及び半導体チップの表面電極と接続する他のリード端子が封止モールド樹脂から導出しないために、半導体装置の外観寸法を著しく小型化にすることができる。さらに述べれば、本発明では単一の半導体装置内にトランジスタが形成された第１の半導体チップ６１と集積回路が形成された第２の半導体チップ８１とを内蔵し、その半導体チップ６１、８１の裏面側を実装基板上に直接接続すること、及び各半導体チップ６１、８１の表面電極と接続される各外部接続手段をシリコンチップ６２、８２、８３、８４、８５とする構造としたので、半導体チップ６１、８１と接続する金属製のリード端子を不要とすることができる。
【００３１】
以下の本発明の半導体装置の製造方法について説明する。
先ず、図５に示すように、支持基板７０の一主面上にポリイミド樹脂等の絶縁樹脂層７１上に複数の第１及び第２の半導体チップ６１、８１及び複数のシリコンチップ６２、８２、８３、８４、８５を規則的に配置する。第１及び第２の半導体チップ６１、８１は、例えば、図６に示すように、支持基板７０のｎ行及びｎ行＋偶数番目の行方向にトランジスタの第１の半導体チップ６１を実装し、ｎ＋奇数番目の行方向に第１の半導体チップ６１に隣接して集積回路の第２の半導体チップ８１を実装する。隣接実装された各半導体チップ６１、８１を挟んで複数のシリコンチップ６２、８２、８３、８４、８５を実装する。
【００３２】
支持基板７０は比較的熱伝導性が良好な材料からなるものが用いられ、例えば、銅、アルミニウム、セラミックス、ガラスエポキシ等から形成された厚さ約０．３mm〜１．２mmの薄状基板を用いる。その支持基板７０上に膜厚約２μ〜５μ厚のポリイミド系の樹脂が約３００℃〜約４００℃の加熱温度で貼着される。
複数の半導体チップ６１、８１及び複数のシリコンチップ６２、８２、８３、８４、８５は、支持基板７０を上記した加熱温度よりも低い加熱温度、例えば約２００℃〜約３００℃に加熱した状態で支持基板７０上に実装する。この時の加熱温度を最初の加熱温度より高温にしておくと、各半導体チップ６１、８１等を絶縁樹脂層７１上にダイボンドしたときに接着力が高くなりすぎて，後述する支持基板７０の剥離に悪影響を及ぼす。
【００３３】
本実施形態では、外部接続用手段６２、８２、８３、８４、８５は上述したように、シリコンチップを用いている。このシリコンチップ６２、８２、８３、８４、８５のサイズは、各半導体チップ６１、８１サイズに依存するが、例えば、半導体チップサイズが０．４０〜０．８mm×０．４０〜０．８mmである場合には、シリコンチップサイズは０．２５〜０．５mm×０．２５〜０．５mm程度に設計すればよい。従って、シリコンチップ６２、８２、８３、８４、８５も半導体チップ６１、８１同様に半導体ウエハを周知のダイシング技術により個別に形成することができる。本実施形態で使用されるシリコンチップ６２、８２、８３、８４、８５には、内部抵抗を低減化する目的から表面から反主面まで高濃度不純物が拡散されている。
【００３４】
支持基板７０上には、それぞれのチップが個々に形成されたシリコンウエハからダイボンディング装置により、それぞれピックアップされ、図６に示すように、支持基板７０上に指定された領域に規則的に複数の第１及び第２の半導体チップ６１、８１、及び、シリコンチップ６２、８２、８３、８４、８５を上述した配列でダイボンディンする。ダイボンディングされた両チップは支持基板７０上に形成された絶縁樹脂層７１の接着力によって、支持基板７０上に仮固着されることになる。
【００３５】
両チップを支持基板７０上に実装した後、図６に示すように、各半導体チップ６１、８１の表面に形成された外部接続用電極パッドと対応する各外部接続用のシリコンチップ６２、８２、８３、８４、８５とをそれぞれ金、アルミニウム等の金属細線でワイヤーボンディング接続し電気的接続を行う。この際、例えば、同図に示すように、シリコンチップ８２（外部接続電極８２）には第１の半導体チップ６１のベース電極と第２の半導体チップ８１の電極とがそれぞれワイヤーボンディング接続され、シリコンチップ８２を介してトランジスタが形成された第１の半導体チップ６１と集積回路が形成された第２の半導体チップ８１とが電気的に接続される。この実施形態では、シリコンチップ８２を介して両チップ６１、８１の接続を行っていが、両チップを直接ワイヤで接続できることは説明するまでもない。
【００３６】
次に、図７に示すように、支持基板７０上にエポキシ樹脂等の熱硬化性の封止用樹脂１１０を塗布し、約１５０℃〜約２００℃の温度で加熱処理を行い、支持基板７０上に実装した複数の第１及び第２の半導体チップ６１、８１、及び複数のシリコンチップ６２、８２、８３、８４、８５を封止用樹脂１１０で固定する。この時、半導体チップ６１、８１及びシリコンチップ６２、８２、８３、８４、８５の表面が露出しないように封止用樹脂１１０の厚みを考慮する。
【００３７】
両チップを封止用樹脂１１０で固定した後、図８に示すように、封止用樹脂１１０と密着した支持基板７０を封止用樹脂１１０から剥離する。封止用樹脂１１０は、溶剤を用いて溶かす科学的剥離を行うか、又は支持基板７０を約１５０℃〜約２００℃に加熱し樹脂層の接着力を低下させた状態で機械的な剥離を行う。支持基板７０を剥離し半導体チップ６１、８１及びシリコンチップ６２、８２、８３、８４、８５の表面を露出させた後、封止用樹脂１１０で固定された少なくとも第１及び第２の半導体チップ６１、８１とその半導体チップ６１、８１と接続される各シリコンチップ６２、８２、８３、８４、８５とを含む領域、具体的には、例えば、図８に示す矢印線及び図６に示す点線領域の封止用樹脂１１０をダイシング装置等の切断装置を用いて切断し個々に分割することにより、図１に示したトランジスタ及び集積回路の半導体チップを内蔵した複合型の半導体装置を製造することができる。
【００３８】
上述した本発明の半導体装置の有効面積率を従来の半導体装置と比較してみると、従来例で説明した半導体装置のチップサイズは、０．４０mm×０．４０mmで、この半導体チップ６１を金属リード端子とワイヤーで接続し、樹脂モールドすると半導体装置の全体のサイズが１．６mm×１．６mmとなる。チップ面積は０．１６mm2に対して、半導体装置を実装する実装面積は半導体装置の面積とほぼ同様として考えて２．５６mm2であるため、従来の半導体装置の有効面積率は約６．２５％であった。
【００３９】
それに対して、本発明の半導体装置はトランジスタ及び集積回路の半導体チップが内蔵され、そのチップサイズは多少異なるにしても、金属製リード端子が不要となる。従来のトランジスタ、集積回路の半導体装置２個分と比較した場合、実装基板上に実装する実装面積のデットスペースを小さくすることができ、実装基板の小型化に寄与することができる。
【００４０】
上述した、本発明の半導体装置の製造法によれば、支持基板７０上に半導体チップ６１、８１及びシリコンチップ６２、８２、８３、８４、８５を実装し電気的接続を行い封止用樹脂１１０で固定した後、支持基板７０を剥離し少なくとも半導体チップ６１、８１とその半導体チップ６１、８１と接続される外部接続手段６２、８２、８３、８４、８５とを含んだ封止用樹脂１１０領域で個々に分割することにより、従来の半導体装置のような金属製のリード端子を不要にでき生産コストの低減化およびトランジスタと集積回路とを内蔵した半導体装置を多量生産することができる。
【００４１】
本実施形態では、第１の半導体チップ６１にトランジスタを形成したが、縦型或いは比較的発熱量の少ない横型のデバイスであればこれに限らず、例えば、パワーＭＯＳＦＥＴ、ＩＧＢＴ、ＨＢＴ等のデバイスを形成した半導体チップ６１、であっても、本発明に応用ができることは説明するまでもない。
【００４２】
【発明の効果】
以上に詳述したように、本発明の半導体装置によれば、トランジスタが形成された第１の半導体チップと集積回路が形成された第２の半導体チップとを隣接配置し、その各半導体チップの近傍に配置された複数の外部接続手段と第１及び第２の半導体チップとの電気的接続を行い、配線基板等の実装基板上に実装固着するための外部電極となる第１及び第２の半導体チップ及び複数の外部接続手段の一主面を露出させる用に封止用樹脂で固定することにより、従来の半導体装置のように、半導体チップをマウントする外部電極接続用の金属製のリード端子を不要とし、且つ、前記リード端子及び半導体チップの表面電極と接続する他のリード端子が封止モールド樹脂から導出しないために、複数の半導体チップを内蔵した複合型の半導体装置であってもその外観寸法を著しく小型化にすることができる。その結果、トランジスタ及び集積回路の半導体チップを内蔵した半導体装置の外観寸法を著しく小型化にすることができ、実装基板上に実装したときの不必要なデットスペースを無くすことができ、実装基板の小型化に大きく寄与することができる。
【図面の簡単な説明】
【図１】本発明の半導体装置を示す断面図。
【図２】本発明の半導体装置の裏面を示す図。
【図３】一般的なトランジスタの断面図。
【図４】一般的な集積回路の断面図。
【図５】本発明の半導体装置の製造方法を説明する図。
【図６】本発明の半導体装置の製造方法を説明する図。
【図７】本発明の半導体装置の製造方法を説明する図。
【図８】本発明の半導体装置の製造方法を説明する図。
【図９】従来の半導体装置の断面図。
【図１０】従来の半導体装置を実装基板上に実装した断面図。
【図１１】従来の半導体装置の平面図。
【図１２】従来の半導体装置の平面図。
【図１３】従来の半導体装置を実装基板上に実装した断面図。
【図１４】従来の半導体装置を実装基板上に実装した断面図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved mounting effective area ratio expressed by a ratio between a chip area of the semiconductor device and a mounting area where the semiconductor device is mounted on a mounting substrate such as a printed circuit board.
[0002]
[Prior art]
In general, a semiconductor device in which a transistor element is formed on a silicon substrate mainly has a configuration as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.
[0003]
As shown in FIG. 3, the transistor element formed on the silicon substrate 11 has a base region formed by, for example, diffusing a P-type impurity such as boron into an N-type epitaxial layer 12 serving as a collector region in the N-type silicon substrate 11. 13 is formed, and an emitter region 14 is formed by diffusing N-type impurities such as phosphorus in the base region 13. An insulating film 15 having openings for exposing portions of the base region 13 and the emitter region 14 is formed on the surface of the silicon substrate 11, and a metal such as aluminum is deposited on the exposed base region 13 and emitter region 14. Then, the base electrode 16 and the emitter electrode 17 are formed. In the transistor having such a configuration, the silicon substrate serves as the collector electrode 18.
[0004]
As described above, the silicon substrate 1 on which the transistor elements are formed is fixedly mounted on the island 2 such as a copper-based heat sink via the brazing material 5 such as solder as shown in FIG. A base electrode and an emitter electrode of the transistor element are electrically connected to the lead terminals 3 arranged in the periphery by wires by wire bonding. The lead terminal connected to the collector electrode is formed integrally with the island, and after being electrically connected by mounting the silicon substrate on the island, transfer molding with a thermosetting resin 4 such as epoxy resin, A semiconductor device having a three-terminal structure is provided by completely covering and protecting the silicon substrate and a part of the lead terminal.
[0005]
[Problems to be solved by the invention]
A resin-molded semiconductor device is usually mounted on a mounting substrate such as a glass epoxy substrate, and is electrically connected to other semiconductor devices and circuit elements mounted on the mounting substrate to perform a predetermined circuit operation. Treated as a part.
FIG. 10 shows a cross-sectional view when a semiconductor device is mounted on a mounting substrate. 20 is a semiconductor device, 21 and 23 are base or emitter electrode lead terminals, 22 is a collector lead terminal, and 30 is a mounting substrate. It is.
[0006]
A mounting area where the semiconductor device 20 is mounted on the mounting substrate 30 is represented by a region surrounded by lead terminals 21, 22, and 23 and conductive pads connected to the lead terminals. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, and most of the mounting area is taken by the mold resin and the lead terminal as compared with the area of the semiconductor chip that actually has a function.
[0007]
Here, it is confirmed that the effective area ratio is extremely low in the resin-molded semiconductor device when the effective area ratio is considered as the ratio between the actually functioning semiconductor chip area and the mounting area. The low effective area ratio means that when the semiconductor device 20 is connected to other circuit elements on the mounting substrate 30, most of the mounting area becomes a dead space that is not directly related to a functioning semiconductor chip. If the effective area ratio is small, the dead space is increased on the mounting substrate 30 as described above, which hinders high-density downsizing of the mounting substrate 30.
[0008]
This problem is particularly noticeable in a semiconductor device having a small package size. For example, the maximum size of a semiconductor chip mounted on the outer shape of the SC-75A, which is an EIAJ standard, is a maximum of 0.40 mm × 0.40 mm as shown in FIG. When this semiconductor chip is connected to a metal lead terminal with a wire and resin-molded, the overall size of the semiconductor device is 1.6 mm × 1.6 mm. The chip area of this semiconductor device is 0.16 mm, and the mounting area for mounting the semiconductor device is 2.56 mm, assuming that it is almost the same as the area of the semiconductor device. Therefore, the effective area ratio of this semiconductor device is about 6.25. Therefore, most of the mounting area is a dead space not directly related to the area of the functioning semiconductor chip.
[0009]
This problem regarding the effective area ratio is particularly noticeable in a semiconductor device having a very small package size and a large chip size as described above, but the semiconductor chip is wire-connected with a metal lead terminal, resin-molded, and resin-encapsulated. A similar problem arises in the case of a type semiconductor device.
Mounting boards used in recent electronic devices, for example, portable information processing devices such as personal computers and electronic notebooks, 8 mm video cameras, mobile phones, cameras, liquid crystal televisions, etc. The mounting substrate used is also in the trend of high density and miniaturization.
[0010]
However, in the above-described prior art resin-encapsulated semiconductor device, as described above, since the mounting area for mounting the semiconductor device has a large dead space, there is a limit to downsizing of the mounting substrate, and downsizing of the mounting substrate. Was one of the obstacles.
By the way, there is JP-A-3-248551 as a prior art for improving the effective area ratio. This prior art will be briefly described with reference to FIG. In this prior art, lead terminals 41, 42, and 43 connected to the base, emitter, and collector electrodes of the semiconductor chip 40 are provided in order to minimize the mounting area when the resin mold type semiconductor device is mounted on a mounting substrate or the like. It is described that the lead terminals 41, 42, 43 are formed so as to be flush with the side surface of the resin mold 44 without being led out from the side surface of the resin mold 44.
[0011]
According to this configuration, the mounting area can be reduced by the amount that the tip portions of the lead terminals 41, 42, 43 are not led out, and the effective area ratio can be slightly improved.
However, in the semiconductor device described above, the tip portion of the lead terminal connected to the semiconductor chip is bent at the corner portion of the bottom surface portion of the resin mold 44, so that the structure can sufficiently withstand the stress during the bending process. Therefore, the length of each lead terminal embedded in the resin mold must be sufficient. As a result, the resin mold size becomes larger than the semiconductor chip size to be mounted, and the effective area ratio does not decrease. Furthermore, each lead terminal connected to the semiconductor chip is required, and the material cost and the manufacturing process become complicated, and there is a problem that the manufacturing cost cannot be reduced.
[0012]
In order to maximize the effective area ratio, as described above, by mounting the semiconductor chip directly on the mounting substrate, the area of the semiconductor chip and the mounting area are almost the same, and the effective area ratio is maximized.
As one prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-6-338504, a flip chip in which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 is used as a mounting substrate. A technique of face-down bonding on 47 is known (see FIG. 13). In this prior art, a gate (base) electrode, a source (emitter) electrode, and a drain (collector) electrode are usually formed on the same main surface of a silicon substrate such as a MOSFET, and a current or voltage path is formed in a horizontal direction. It is mainly used for horizontal semiconductor devices that generate a relatively small amount of heat.
[0013]
However, in a vertical semiconductor device such as a transistor device where a silicon substrate is one of the electrodes and each electrode is formed on a different surface and the current path flows in the vertical direction, the above-described flip chip technology is not used. Have difficulty.
As another prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in Japanese Patent Laid-Open No. 7-38334, a semiconductor chip 53 is formed on a conductive pattern 52 formed on a mounting substrate 51. A technique of bonding and connecting electrodes of the conductive pattern 52 and the semiconductor chip 53 arranged around the semiconductor chip 53 with a wire 54 is known (see FIG. 14). This prior art can be used for a semiconductor chip such as a transistor having a vertical structure in which the above-described silicon substrate constitutes one electrode.
[0014]
Since the wire 54 that connects the semiconductor chip 53 and the conductive pattern 52 disposed around the semiconductor chip 53 is usually a gold fine wire, the peel strength (tensile force) of the bonding joint that is bonded to the gold fine wire is increased. Therefore, it is preferable to perform bonding in a heated atmosphere of about 200 ° C. to 300 ° C. However, when die-bonding a semiconductor chip on an insulating resin-based mounting substrate, the mounting substrate is distorted when heated to the above temperature, and chip capacitors, chip resistors, etc. mounted on the mounting substrate Since the solder for fixing other circuit elements is melted, wire bonding connection is performed at a heating temperature of about 100 ° C. to 150 ° C., so that there is a problem that the peel strength of the bonding junction is lowered.
[0015]
In this prior art, since the die-bonded semiconductor chip is usually covered and protected with a sealing resin such as an epoxy resin, the decrease in peel strength is caused by the shrinkage of the epoxy resin during thermal curing, etc. There is a problem that.
The present invention has been made in view of the above-described circumstances, and the present invention provides an external connection for input / output of each semiconductor chip of a composite semiconductor device incorporating a semiconductor chip on which a transistor and an integrated circuit are formed. Electrodes are arranged on the same plane, and the effective area ratio, which is the ratio between the area of each semiconductor chip and the mounting area of a single semiconductor device mounted on the mounting board, is maximized, and the dead space of the mounting area is minimized. Provided is a composite semiconductor device with a limited size.
[0016]
[Means for Solving the Problems]
The present invention employs the following configuration and manufacturing method in order to solve the above problems.
That is, a semiconductor device according to the present invention is provided on a surface of a first semiconductor chip in which a transistor is formed in a semiconductor substrate, a second semiconductor chip in which an integrated circuit is formed, and the surfaces of the first and second semiconductor chips. A plurality of external connection means electrically connected to the electrode pads, and the first and second semiconductor chips are disposed adjacent to each other and electrically connected to each other, and are disposed in the vicinity thereof. Electrical connection is made with the external connection means, and the main surfaces of the external connection means and the first and second semiconductor chips are exposed and fixed with a sealing resin.
[0017]
Here, one main surface of the plurality of external connection means and the first and second semiconductor chips are arranged on the same plane.
As described above, according to the semiconductor device of the present invention, the first semiconductor chip in which the transistor is formed and the second semiconductor chip in which the integrated circuit is formed are arranged adjacent to each other and arranged in the vicinity of each semiconductor chip. First and second semiconductor chips which are external electrodes for electrically connecting the plurality of external connection means to the first and second semiconductor chips and mounting and fixing them on a mounting board such as a wiring board; Fixing with a sealing resin to expose one main surface of multiple external connection means eliminates the need for metal lead terminals for connecting external electrodes to mount semiconductor chips as in conventional semiconductor devices. In addition, since the lead terminals and other lead terminals connected to the surface electrodes of the semiconductor chip are not led out from the sealing mold resin, the semiconductor device is a composite semiconductor device having a plurality of semiconductor chips. It can also significantly reduce the size of the appearance dimension.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the semiconductor device of the present invention will be described.
As shown in FIG. 1, the semiconductor device of the present invention includes a first semiconductor chip 61 in which a transistor is formed, a second semiconductor chip 81 in which an integrated circuit is formed, and surface electrodes of the semiconductor chips 61 and 81. A plurality of external connection means 62, 82, 83, 84, 85 to be electrically connected, and the first and second semiconductor chips 61, 81 and the external connection means 62, 82, 83, 84, 85 are fixed. And a sealing resin 110.
[0019]
A transistor is formed in the first semiconductor chip 61. For example, as shown in FIG. 3, an N− type epitaxial layer 12 is formed on an N + type single crystal silicon substrate 11 by an epitaxial growth technique. An active element such as an NPN transistor is formed on the substrate 11. On the other hand, an integrated circuit is formed on the second semiconductor chip 81.
[0020]
The present invention is particularly suitable for a so-called vertical structure device having external connection electrodes on the front and back surfaces of the first and second semiconductor chips 61 and 81. FIG. 3 is a cross-sectional view of the general NPN transistor described above. For example, a transistor having an N− type epitaxial layer 12 as a collector region is formed, a photoresist is formed on the semiconductor substrate 11, and An island-shaped base region 13 having a predetermined depth is formed by selectively thermally diffusing P-type impurities such as boron (B) in the region exposed by the photoresist.
[0021]
After the base region 13 is formed, a photoresist is formed again on the semiconductor substrate 11, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively thermally diffused in the base region 13 exposed by the photoresist. An emitter region 14 of the transistor is formed. When the emitter region 14 is formed, an N + type diffusion region for a ring-shaped guard ring surrounding the base region 13 may be formed.
[0022]
An insulating film 15 such as a silicon oxide film or a silicon nitride film having a base contact hole exposing the surface of the base region 13 and an emitter contact hole exposing the surface of the emitter region is formed on the surface of the semiconductor substrate 11.
On the base contact hole 13 and the emitter region 14 exposed through the base contact hole and the emitter contact hole, a base electrode 16 and an emitter electrode 17 selectively deposited with a metal material such as aluminum, and pads for external connection of these electrodes (Not shown) is formed. The back surface of the semiconductor substrate 11 is subjected to metal plating and used as the collector electrode 18.
[0023]
As the second semiconductor chip 81, for example, a single crystal P-type semiconductor substrate is used, and an integrated circuit such as a bipolar IC or a MOSIC is formed. For example, as shown in FIG. 4, a photomask having a predetermined shape is formed on a P-type semiconductor substrate, and an N-type high concentration impurity such as antimony is diffused to form an island-like N + -type buried collector region 101. The After removing the photomask, an N − type epitaxial layer 102 is formed on the substrate 100 by an epitaxial growth technique.
[0024]
A mask that exposes the isolation diffusion region is formed on the epitaxial layer 102, and an isolation diffusion region 103 is formed by diffusing a P + -type impurity such as boron in the isolation diffusion region. By this isolation diffusion region 103, an N-type region which becomes an active region of the transistor is surrounded by a P-type impurity.
[0025]
A photoresist is formed on the epitaxial layer 102, and an island-like base region 104 having a predetermined depth is formed by selectively thermally diffusing a P-type impurity such as boron (B) in the region exposed by the photoresist. The
After the base region 104 is formed, a photoresist is formed again on the epitaxial layer 102, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively introduced into the base region 104 and the collector region exposed by the photoresist. By thermal diffusion, an emitter region 105 and a collector contact diffusion region 106 of the transistor are formed.
[0026]
An insulating film 107 such as a silicon oxide film or a silicon nitride film having a base contact hole exposing the surface of the base region 104, an emitter contact hole exposing the surface of the emitter region 105, and a collector contact hole exposing the surface of the collector contact diffusion region is formed. Is done.
The base region 104, the emitter region 106, and the collector contact region 107 exposed by the base contact hole, the emitter contact hole, and the collector contact hole are selectively formed by a base electrode 107, an emitter electrode 108, A collector electrode 109 is formed.
[0027]
A feature of the present invention is that an external connection electrode pad (base electrode, emitter electrode, etc.) provided on the surface side of the first and second semiconductor chips 61, 81 is connected to a plurality of external connection means 62, 82. , 83, 84, 85 without being led out from the sealing resin 110, arranged on the same side as the external connection electrodes (collector electrode, ground electrode) on the back surface of each semiconductor chip 61, 81, and sealing resin Minimize the size and improve the effective area ratio.
[0028]
The external connection means 62, 82, 83, 84, 85 correspond to the number of external connection electrode pads such as bases and emitters provided on the surfaces of the first and second semiconductor chips 61, 81. It is arranged near the periphery of the chips 61 and 81 (see FIG. 2). The external connection means 62, 82, 83, 84, 85 and the electrode pads for the base and emitter of the first and second semiconductor chips 61, 81 are electrically connected by wires made of fine metal wires such as gold or aluminum. Thus, the first and second semiconductor chips 61 and 81 are electrically connected by this wire. For example, as shown in FIG. 2, the external connection electrode 82 is connected to the base electrode of the first semiconductor chip 61 with a wire, and further connected to the electrode of the second semiconductor chip 81, whereby both semiconductor chips are connected. Connections 61 and 81 are made. In this embodiment, the two chips are connected via the external connection electrodes, but needless to say, they can be directly connected by wires.
[0029]
The external connection means 62, 82, 83, 84, 85 are not particularly limited as long as they are made of a metal piece such as copper, invar, tellurium or the like or a conductive material such as a silicon chip made of a silicon material. In the present embodiment, a silicon chip is used in consideration of workability and cost. The semiconductor chips 61, 81 and the external connection silicon chips 62, 82, 83, 84, 85, which are electrically connected by wires, are fixed with a thermosetting sealing resin 110 such as an epoxy resin. At this time, the back surfaces of the first and second semiconductor chips 61 and 81 serving as the collector electrode and the ground electrode, and the back surfaces of the respective external connection silicon chips 62, 82, 83, 84, and 85 serving as input / output electrodes Are arranged on the same plane.
[0030]
As described above, according to the present invention, unlike the conventional semiconductor device, the metal lead terminal for connecting the external electrode for mounting the semiconductor chip is unnecessary, and the lead terminal and the surface electrode of the semiconductor chip are connected. Since the other lead terminals are not led out from the sealing mold resin, the external dimensions of the semiconductor device can be remarkably reduced. More specifically, the present invention includes a first semiconductor chip 61 in which a transistor is formed in a single semiconductor device and a second semiconductor chip 81 in which an integrated circuit is formed. Since the back side is directly connected to the mounting substrate and the external connection means connected to the surface electrodes of the semiconductor chips 61 and 81 are silicon chips 62, 82, 83, 84, and 85, the semiconductor Metal lead terminals connected to the chips 61 and 81 can be dispensed with.
[0031]
A method for manufacturing a semiconductor device according to the present invention will be described below.
First, as shown in FIG. 5, a plurality of first and second semiconductor chips 61, 81 and a plurality of silicon chips 62, 82 are formed on an insulating resin layer 71 such as polyimide resin on one main surface of a support substrate 70. 83, 84, and 85 are regularly arranged. For example, as shown in FIG. 6, the first and second semiconductor chips 61 and 81 have the first semiconductor chip 61 of the transistor mounted in the n-row and n-row + even-numbered row direction of the support substrate 70, A second semiconductor chip 81 of an integrated circuit is mounted adjacent to the first semiconductor chip 61 in the (n + odd) number row direction. A plurality of silicon chips 62, 82, 83, 84, and 85 are mounted with the adjacent semiconductor chips 61 and 81 interposed therebetween.
[0032]
The support substrate 70 is made of a material having relatively good thermal conductivity. For example, a thin substrate having a thickness of about 0.3 mm to 1.2 mm formed of copper, aluminum, ceramics, glass epoxy, or the like is used. Use. A polyimide resin having a thickness of about 2 to 5 μm is stuck on the support substrate 70 at a heating temperature of about 300 ° C. to about 400 ° C.
The plurality of semiconductor chips 61, 81 and the plurality of silicon chips 62, 82, 83, 84, 85 are in a state where the support substrate 70 is heated to a heating temperature lower than the above-described heating temperature, for example, about 200 ° C. to about 300 ° C. It is mounted on the support substrate 70. If the heating temperature at this time is set higher than the initial heating temperature, the adhesive force becomes too high when the semiconductor chips 61, 81, etc. are die-bonded on the insulating resin layer 71, and the support substrate 70 described later is peeled off. Adversely affect.
[0033]
In the present embodiment, as described above, the external connection means 62, 82, 83, 84, 85 use silicon chips. The size of the silicon chips 62, 82, 83, 84, 85 depends on the size of each semiconductor chip 61, 81, but for example, the semiconductor chip size is 0.40 to 0.8 mm × 0.40 to 0.8 mm. In some cases, the silicon chip size may be designed to be about 0.25 to 0.5 mm × 0.25 to 0.5 mm. Therefore, similarly to the semiconductor chips 61 and 81, the silicon wafers 62, 82, 83, 84, and 85 can be formed individually by a known dicing technique. In the silicon chips 62, 82, 83, 84, 85 used in the present embodiment, high concentration impurities are diffused from the surface to the anti-main surface for the purpose of reducing the internal resistance.
[0034]
On the support substrate 70, each chip is individually picked up by a die bonding apparatus from a silicon wafer on which each chip is formed. As shown in FIG. The first and second semiconductor chips 61 and 81 and the silicon chips 62, 82, 83, 84, and 85 are die-bonded in the arrangement described above. Both die-bonded chips are temporarily fixed on the support substrate 70 by the adhesive force of the insulating resin layer 71 formed on the support substrate 70.
[0035]
After both the chips are mounted on the support substrate 70, as shown in FIG. 6, the external connection silicon chips 62, 82 corresponding to the external connection electrode pads formed on the surfaces of the semiconductor chips 61, 81 are provided. 83, 84, and 85 are electrically connected by wire bonding with fine metal wires such as gold and aluminum. At this time, for example, as shown in the figure, the base electrode of the first semiconductor chip 61 and the electrode of the second semiconductor chip 81 are connected to the silicon chip 82 (external connection electrode 82) by wire bonding, respectively. The first semiconductor chip 61 in which the transistor is formed and the second semiconductor chip 81 in which the integrated circuit is formed are electrically connected via the chip 82. In this embodiment, the two chips 61 and 81 are connected via the silicon chip 82, but needless to say, the two chips can be directly connected by a wire.
[0036]
Next, as shown in FIG. 7, a thermosetting sealing resin 110 such as an epoxy resin is applied on the support substrate 70, and heat treatment is performed at a temperature of about 150 ° C. to about 200 ° C. The plurality of first and second semiconductor chips 61, 81 and the plurality of silicon chips 62, 82, 83, 84, 85 mounted on the top are fixed with a sealing resin 110. At this time, the thickness of the sealing resin 110 is considered so that the surfaces of the semiconductor chips 61 and 81 and the silicon chips 62, 82, 83, 84, and 85 are not exposed.
[0037]
After fixing both the chips with the sealing resin 110, as shown in FIG. 8, the support substrate 70 in close contact with the sealing resin 110 is peeled from the sealing resin 110. The sealing resin 110 may be subjected to scientific peeling using a solvent, or mechanical peeling in a state where the support substrate 70 is heated to about 150 ° C. to about 200 ° C. to reduce the adhesive strength of the resin layer. Do. After the support substrate 70 is peeled off to expose the surfaces of the semiconductor chips 61 and 81 and the silicon chips 62, 82, 83, 84, and 85, at least the first and second semiconductor chips 61 fixed with the sealing resin 110. , 81 and each of the silicon chips 62, 82, 83, 84, 85 connected to the semiconductor chips 61, 81, specifically, for example, an arrow line shown in FIG. 8 and a dotted line area shown in FIG. 1 is cut using a cutting device such as a dicing device and divided into individual pieces, thereby manufacturing a composite semiconductor device incorporating the transistor and the integrated circuit semiconductor chip shown in FIG. it can.
[0038]
When the effective area ratio of the semiconductor device of the present invention described above is compared with that of a conventional semiconductor device, the chip size of the semiconductor device described in the conventional example is 0.40 mm × 0.40 mm. When the lead terminal is connected with a wire and resin molding is performed, the entire size of the semiconductor device becomes 1.6 mm × 1.6 mm. Since the chip area is 0.16 mm 2 and the mounting area for mounting the semiconductor device is 2.56 mm 2 assuming that it is almost the same as the area of the semiconductor device, the effective area ratio of the conventional semiconductor device is about 6.25%. there were.
[0039]
On the other hand, the semiconductor device of the present invention incorporates a transistor and a semiconductor chip of an integrated circuit, and a metal lead terminal is not required even if the chip size is slightly different. Compared with two conventional transistors and integrated circuit semiconductor devices, the dead space of the mounting area to be mounted on the mounting substrate can be reduced, which contributes to downsizing of the mounting substrate.
[0040]
According to the manufacturing method of the semiconductor device of the present invention described above, the semiconductor chips 61 and 81 and the silicon chips 62, 82, 83, 84, and 85 are mounted on the support substrate 70 to be electrically connected, and the sealing resin 110. After fixing, the supporting substrate 70 is peeled off, and the sealing resin 110 region including at least the semiconductor chips 61 and 81 and the external connection means 62, 82, 83, 84, and 85 connected to the semiconductor chips 61 and 81. Thus, the metal lead terminals as in the conventional semiconductor device can be made unnecessary, the production cost can be reduced, and the semiconductor device incorporating the transistor and the integrated circuit can be mass-produced.
[0041]
In this embodiment, a transistor is formed on the first semiconductor chip 61. However, the device is not limited to this as long as it is a vertical type or a horizontal type device with a relatively small amount of heat generation. For example, a device such as a power MOSFET, IGBT, or HBT It goes without saying that even the formed semiconductor chip 61 can be applied to the present invention.
[0042]
【The invention's effect】
As described above in detail, according to the semiconductor device of the present invention, the first semiconductor chip in which the transistor is formed and the second semiconductor chip in which the integrated circuit is formed are arranged adjacent to each other. A plurality of external connection means arranged in the vicinity and the first and second semiconductor chips are electrically connected, and the first and second become the external electrodes for mounting and fixing on a mounting substrate such as a wiring substrate. A metal lead terminal for connecting an external electrode for mounting a semiconductor chip as in a conventional semiconductor device by fixing with a sealing resin to expose one main surface of the semiconductor chip and a plurality of external connection means And no other lead terminal connected to the lead electrode and the surface electrode of the semiconductor chip is led out from the sealing mold resin, so that a composite semiconductor device incorporating a plurality of semiconductor chips is provided. Even it can be significantly downsized their appearance dimensions. As a result, the external dimensions of a semiconductor device incorporating a transistor and an integrated circuit semiconductor chip can be significantly reduced, and unnecessary dead space when mounted on a mounting board can be eliminated. This can greatly contribute to downsizing.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.
FIG. 2 is a view showing a back surface of a semiconductor device of the present invention.
FIG. 3 is a cross-sectional view of a general transistor.
FIG. 4 is a cross-sectional view of a general integrated circuit.
FIGS. 5A and 5B illustrate a method for manufacturing a semiconductor device of the present invention. FIGS.
6A and 6B illustrate a method for manufacturing a semiconductor device of the present invention.
7A to 7C illustrate a method for manufacturing a semiconductor device of the present invention.
FIGS. 8A to 8C are diagrams illustrating a method for manufacturing a semiconductor device of the present invention. FIGS.
FIG. 9 is a cross-sectional view of a conventional semiconductor device.
FIG. 10 is a cross-sectional view of a conventional semiconductor device mounted on a mounting substrate.
FIG. 11 is a plan view of a conventional semiconductor device.
FIG. 12 is a plan view of a conventional semiconductor device.
FIG. 13 is a cross-sectional view of a conventional semiconductor device mounted on a mounting substrate.
FIG. 14 is a cross-sectional view of a conventional semiconductor device mounted on a mounting substrate.

Claims (2)

半導体基板内にトランジスタが形成された第１の半導体チップ及び、集積回路が形成された第２の半導体チップと、複数の外部接続手段とを有し、前記第１及び第２の半導体チップは隣接配置されると共に電気的接続が行われ、且つその近傍に配置された前記外部接続手段と電気的接続が行われ、前記外部接続手段及び前記第１及び第２の半導体チップの裏面のみを露出させて封止用樹脂で固定されたことを特徴とする半導体装置。And the first semiconductor chip in which a transistor is formed in a semiconductor substrate, a second semiconductor chip on which an integrated circuit is formed, and an external connecting means of multiple, said first and second semiconductor chips Adjacent and electrically connected, and electrically connected to the external connecting means arranged in the vicinity thereof, and only the back surfaces of the external connecting means and the first and second semiconductor chips are exposed. A semiconductor device characterized by being fixed with sealing resin. 複数の前記外部接続手段及び前記第１及び第２の半導体チップの裏面は同一平面上に配置されることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the plurality of external connection means and the back surfaces of the first and second semiconductor chips are arranged on the same plane.
JP27494396A 1996-10-17 1996-10-17 Semiconductor device Expired - Fee Related JP3639390B2 (en)

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