JP4190518B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a semiconductor element is provided on a mounting substrate made of silicon, and a mounting substrate made of silicon used therein.

  In general, a semiconductor device in which a transistor element is formed on a silicon substrate mainly has a configuration as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.

  As shown in FIG. 6, the transistor element formed on the silicon substrate 11 has a base region formed by diffusing a P-type impurity such as boron into an N-type epitaxial layer 12 serving as a collector region in the N-type silicon substrate 11, for example. 13 is formed, and an emitter region 14 is formed by diffusing N-type impurities such as phosphorus in the base region 13. An insulating film 15 having openings for exposing portions of the base region 13 and the emitter region 14 is formed on the surface of the silicon substrate 11, and a metal such as aluminum is deposited on the exposed base region 13 and emitter region 14. Then, the base electrode 16 and the emitter electrode 17 are formed. In the transistor having such a configuration, the silicon substrate serves as the collector electrode 18.

  As described above, the silicon substrate 1 on which the transistor element is formed is fixedly mounted on an island 2 such as a copper-based heat sink via a brazing material 5 such as solder, as shown in FIG. A base electrode and an emitter electrode of the transistor element are electrically connected to the lead terminals 3 arranged in the periphery by wires by wire bonding. The lead terminal connected to the collector electrode is formed integrally with the island, and after being electrically connected by mounting the silicon substrate on the island, transfer molding with a thermosetting resin 4 such as epoxy resin, A semiconductor device having a three-terminal structure in which a silicon substrate and a part of a lead terminal are completely covered and protected is provided.

  A resin-molded semiconductor device is usually mounted on a wiring substrate such as a glass epoxy substrate, and is electrically connected to other semiconductor devices and circuit elements mounted on the mounting substrate to perform a predetermined circuit operation. Treated as a part.

  FIG. 8 shows a cross-sectional view when a semiconductor device is mounted on a mounting substrate, 20 is a semiconductor device, 21 and 23 are base or emitter electrode lead terminals, 22 is a collector lead terminal, and 30 is a mounting substrate. It is.

  A mounting area where the semiconductor device 20 is mounted on the mounting substrate 30 is represented by a region surrounded by lead terminals 21, 22, and 23 and conductive pads connected to the lead terminals. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, and most of the mounting area is taken by the mold resin and the lead terminal as compared with the area of the semiconductor chip that actually has a function.

  Here, it is confirmed that the effective area ratio is extremely low in the resin-molded semiconductor device when the effective area ratio is considered as the ratio between the actually functioning semiconductor chip area and the mounting area. The low effective area ratio means that when the semiconductor device 20 is connected to other circuit elements on the wiring board 30, most of the mounting area becomes a dead space that is not directly related to a functioning semiconductor chip. If the effective area ratio is small, the dead space is increased on the mounting substrate 30 as described above, which hinders high-density downsizing of the mounting substrate 30.

  This problem is particularly noticeable in a semiconductor device having a small package size. For example, the maximum size of a semiconductor chip mounted on the EIAJ standard SC75A outline is 0.40 mm × 0.40 mm as shown in FIG. When this semiconductor chip is connected to a metal lead terminal with a wire and resin-molded, the overall size of the semiconductor device is 1.6 mm × 1.6 mm. The chip area of this semiconductor device is 0.16 mm, and the mounting area for mounting the semiconductor device is 2.56 mm, assuming that it is almost the same as the area of the semiconductor device. Therefore, the effective area ratio of this semiconductor device is about 6.25. Therefore, most of the mounting area is a dead space not directly related to the area of the functioning semiconductor chip.

  This problem regarding the effective area ratio is particularly noticeable in a semiconductor device having a very small package size as described above. However, in a resin-encapsulated semiconductor device in which a semiconductor chip is wire-connected by a metal lead terminal and resin-molded. Even if it exists, it becomes a problem as well.

  Wiring boards used in recent electronic devices, for example, portable information processing devices such as personal computers and electronic notebooks, 8 mm video cameras, mobile phones, cameras, liquid crystal televisions, etc. The mounting substrate used is also in the trend of high density and miniaturization.

  However, in the above-described prior art resin-encapsulated semiconductor device, as described above, since the mounting area for mounting the semiconductor device has a large dead space, there is a limit to downsizing of the mounting substrate, and downsizing of the mounting substrate. Was one of the obstacles.

  By the way, there is JP-A-3-248551 as a prior art for improving the effective area ratio. This prior art will be briefly described with reference to FIG. In this prior art, lead terminals 41, 42, and 43 connected to the base, emitter, and collector electrodes of the semiconductor chip 40 are provided in order to minimize the mounting area when the resin mold type semiconductor device is mounted on a mounting substrate or the like. It is described that the lead terminals 41, 42, 43 are formed so as to be flush with the side surface of the resin mold 44 without being led out from the side surface of the resin mold 44.

  According to this configuration, the mounting area can be reduced by an amount that does not lead out the leading end portions of the lead terminals 41, 42, and 43, and the effective area ratio can be slightly improved, but the size of the dead space is greatly improved. Not.

  In order to improve the effective area ratio, it is necessary to make the semiconductor chip area and mounting area of the semiconductor device substantially the same. In the resin mold type semiconductor device, as in this prior art, the tip of the lead terminal Even if the part is not derived, it is difficult to improve the effective area ratio due to the presence of the mold resin.

  Further, in the above semiconductor device, the lead terminal to be connected to the semiconductor chip and the mold resin are indispensable, and therefore, a process of wire connection process between the semiconductor chip and the lead terminal and an injection molding process of the mold resin are required. There is a problem that the cost and the manufacturing process are complicated, and the manufacturing cost cannot be reduced.

In order to maximize the effective area ratio, as described above, by mounting the semiconductor chip directly on the mounting substrate, the area of the semiconductor chip and the mounting area are almost the same, and the effective area ratio is maximized.
As shown in Japanese Patent Laid-Open No. 6-338504, a technique is known in which a flip chip in which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 is face-down bonded to a mounting substrate 47 (see FIG. 10). In this prior art, a gate (base) electrode, a source (emitter) electrode, and a drain (collector) electrode are usually formed on the same main surface of a silicon substrate such as a MOSFET, and a current or voltage path is formed in a horizontal direction. It is mainly used for horizontal semiconductor devices that generate a relatively small amount of heat.

  However, in a vertical semiconductor device such as a transistor device where a silicon substrate is one of the electrodes and each electrode is formed on a different surface and the current path flows in the vertical direction, the above-described flip chip technology is not used. Have difficulty.

  As another prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in Japanese Patent Laid-Open No. 7-38334, a semiconductor chip 53 is formed on a conductive pattern 52 formed on a mounting substrate 51. A technique for bonding and connecting electrodes of the conductive pattern 52 and the semiconductor chip 53 arranged around the semiconductor chip 53 with a wire 54 is known (see FIG. 11). This prior art can be used for a semiconductor chip such as a transistor having a vertical structure in which the above-described silicon substrate constitutes one electrode.

  Since the wire 54 that connects the semiconductor chip 53 and the conductive pattern 52 disposed around the semiconductor chip 53 is usually a gold fine wire, the peel strength (tensile force) of the bonding joint that is bonded to the gold fine wire is increased. Therefore, it is preferable to perform bonding in a heated atmosphere of about 200 ° C. to 300 ° C. However, when a semiconductor chip is die-bonded on an insulating resin-based mounting substrate, the wiring substrate is distorted when heated to the above temperature, and a chip capacitor mounted on the mounting substrate, a chip resistor, etc. Since the solder for fixing other circuit elements is melted, wire bonding connection is performed at a heating temperature of about 100 ° C. to 150 ° C., so that there is a problem that the peel strength of the bonding junction is lowered.

  In this prior art, since the die-bonded semiconductor chip is usually covered and protected with a thermosetting resin such as an epoxy resin, the reduction in peel strength is caused by the shrinkage during the thermosetting of the epoxy resin and the joint part is peeled off. There is a problem that.

  The present invention has been made in view of the above-described circumstances, and the present invention does not require a lead terminal connected to a semiconductor chip and a mold resin, and a semiconductor chip area and a mounting area mounted on a mounting substrate. The effective area ratio, which is the ratio of the above, is maximally improved, and a semiconductor device with a reduced mounting space is minimized.

The present invention employs the following configuration in order to solve the above problems.

First, a mounting substrate that is formed of a silicon substrate and is provided on an insulating layer on the surface thereof and provided with wiring insulated from the silicon substrate, an active element formed on the surface, and the wiring are electrically connected. And a semiconductor device having a semiconductor chip provided on the mounting substrate,
The mounting substrate is made of silicon constituting the semiconductor chip, and is solved.
The mounting substrate on which the wiring is provided is also made of silicon, thereby matching the thermal expansion coefficients of the semiconductor chip and the mounting substrate and suppressing the stress.
Second, the silicon substrate has conductivity, and the influence of noise is reduced by electrically connecting the wiring and the silicon substrate through a portion where the silicon substrate is exposed.
Third, a passivation film is formed on the wiring and the silicon substrate, and the wiring is exposed by removing a part of the passivation film, and the wiring and the active element are electrically connected via the exposed portion. By connecting them electrically, corrosion of the wiring on the mounting board is prevented.
Fourth, the mounting substrate is formed of a silicon substrate and provided on an insulating layer on the surface thereof, and provided with wiring insulated from the silicon substrate, and the active element formed on the surface and the wiring are electrically connected. A semiconductor device having a semiconductor chip connected to a surface of the mounting substrate facing the surface on which the active element is provided,
The problem is solved by providing an adhesive resin between the mounting substrate and the semiconductor chip.
Fifth, the adhesive resin is a thermosetting type, and the electrical continuity between the active element and the wiring is further improved by heat shrinkage during curing.
Sixth, there is a mounting substrate made of a silicon substrate for mounting a semiconductor element on its surface, and an insulating layer is provided on the surface of the silicon substrate, and a wiring electrically connected to the semiconductor element is provided. It will be solved.
Seventh, the semiconductor element is made of silicon, and the silicon substrate has a thermal expansion coefficient equal to that of the semiconductor element.
Eighth, the problem is solved by providing a passivation film so as to cover the wiring and the silicon substrate, and exposing the wiring by removing a part of the passivation.
Ninth, the insulating layer is solved by being made of a silicon oxide film or a silicon nitride film.
Tenth, the wiring and the silicon substrate are solved by being electrically connected.

By using a silicon substrate for the wiring board,
First, there is a feature that an existing semiconductor manufacturing apparatus can be used as it is, and it is not necessary to newly introduce equipment.
Second, if both the substrates 60 and 65 are silicon substrates when they are fixed to the substrate 60, the thermal expansion coefficient α is equal, so even if heat is generated by external heating or self-heating, the same stress is applied vertically to cancel out. Therefore, it has a feature that the adverse effect due to the distortion of the substrates 60 and 65 can be suppressed.
Third, since the silicon substrate has conductivity, the wiring pattern 67 and the wiring substrate 65 can be electrically connected. As a result, the wiring board 65 becomes a shield plate to obtain a shielding effect, and the adverse effect due to noise can be suppressed.

  Hereinafter, embodiments of the semiconductor device of the present invention will be described.

  As shown in FIG. 1, the semiconductor device of the present invention includes a semiconductor substrate 60, an active element formation region 61 in which an active element is formed, and one electrode of the active element formed in the active element formation region 61. One external connection electrode 62 for external connection, and other external connection electrodes 63 and 64 that are electrically separated from the active element formation region 61 and use a part of the substrate 60 as an external electrode of another electrode of the active element. And a wiring pattern that connects the high-concentration diffusion layer 81 formed in the electrode regions 63A and 64A of the external connection electrodes 63 and 64 and the other electrodes of the active element and the other external connection electrodes 63 and 64. The wiring board 65 is made up of.

  The semiconductor substrate 60 is an N + type single crystal silicon substrate, and an N − type epitaxial layer 66 is formed on the substrate 60 by an epitaxial growth technique. A predetermined region of the semiconductor substrate 60 is provided with an active element formation region 61 where active elements such as power MOSs and transistors are formed, and external connection electrode regions 63A and 64A which are connected to the active element electrodes and become external connection electrodes 63 and 64. It has been.

  The active element described above is formed in the active element formation region 61. Here, a transistor having an N− type epitaxial layer as a collector region 66A is formed. A photoresist is formed on the active element formation region 61, and P-type impurities such as boron (B) are selectively thermally diffused into the region exposed by the photoresist to form an island-shaped base region 71 having a predetermined depth. Is formed.

After the base region 71 is formed, a photoresist is formed again on the active element forming region 61, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively thermally diffused in the base region 71 exposed by the photoresist. Thus, the emitter region 72 of the transistor is formed. When the emitter region 72 is formed, an N + type diffusion region 73 for a ring-shaped guard ring surrounding the base region 71 may be formed.
Further, when the N + -type emitter region 72 is formed, the N + -type diffusion is also performed on the electrode regions 63A and 64A serving as external connection electrodes, and the high concentration diffusion layer 81 is formed in the electrode regions 63A and 64A. Is done.

  An insulating film 74 such as a silicon oxide film or a silicon nitride film having a base contact hole exposing the surface of the base region 71 and an emitter contact hole exposing the surface of the emitter region 72 is formed on the surface of the semiconductor substrate 60. When the guard ring diffusion region 73 is formed, the guard ring contact hole exposing the surface of the diffusion region 73 is formed. The insulating film 74 is also formed on the electrode regions 63A and 64A serving as external connection electrodes, and external connection contact holes are formed to expose the surfaces of the electrode regions 63A and 64A.

  On the base region 71, the emitter region 72, the electrode regions 63A and 64A, and the guard ring diffusion region 73 exposed by the base contact hole, the emitter contact hole, the external connection contact hole and the guard ring contact hole, aluminum or the like is selectively formed. A base electrode 75, an emitter electrode 76, and a connection electrode 77 deposited with the above metal material are formed.

  When aluminum is used for the base electrode 75, the emitter electrode 76, and the connection electrode 77, a passivation film made of an insulator such as a PSG film, SiN, SiNx, etc. is formed on the substrate 60, and the base electrode 75, the emitter electrode 76, the passivation film on the connection electrode 77 is selectively removed, and the surfaces of the electrodes 75, 76, 77 are exposed. Furthermore, it is necessary to selectively plate chromium, copper, or the like in the exposed region to form a plated layer 79 to prevent problems due to corrosion of the electrodes 75, 76, 77.

  The active element formation region 61 and the external connection electrode regions 63A and 64A can be formed in a predetermined arbitrary region of the semiconductor substrate 60. In this embodiment, as shown in FIG. An element formation region 61 is formed, and external connection electrode regions 63A and 64A are formed so as to have a triangle shape with the region 61 interposed therebetween.

  A silicon-based, epoxy-based, polyimide-based, or photocurable insulating adhesive resin layer 78 is provided on the surface of the semiconductor substrate 60 having the active element forming region 61 in which the transistor is formed and the external connection electrode regions 63A, 64A. The wiring board 65 is fixed. A wiring pattern 67 made of aluminum, copper, or the like is formed on the wiring substrate 65. With this wiring pattern 67, the base electrode 75 and emitter electrode 76 of the transistor are electrically connected to the external connection electrode regions 63A and 64A. Each done.

  As the wiring substrate 65, a glass epoxy substrate, a ceramic substrate, an insulated metal substrate, a phenol substrate, a silicon substrate, or the like can be used. In the present invention, it is preferable to use a silicon substrate. When a silicon substrate is used as the wiring substrate 65, an insulating layer such as SiO2 or SiNx is formed on the surface, and a metal such as aluminum is selectively deposited on the insulating layer to form a wiring pattern 67 having a predetermined shape. The

  The main reason for using a silicon substrate for the wiring board 65 is that an existing semiconductor manufacturing apparatus can be used as it is, and it is not necessary to introduce new equipment. Second, if both the substrates 60 and 65 are silicon substrates when they are fixed to the substrate 60, the thermal expansion coefficient α is equal, so even if heat is generated by external heating or self-heating, the same stress is applied vertically to cancel out. Therefore, adverse effects due to distortion of the substrates 60 and 65 can be suppressed. Third, the silicon substrate is conductive.

  On the wiring substrate 65 using a silicon substrate, as described above, a predetermined metal made of a metal such as aluminum connected to the base electrode 75 and the emitter electrode 76 of the transistor via the insulating layer 82 such as SiO 2 or SiN ×. A redundant wiring pattern 67 having a shape is formed. One of the wiring patterns 67 is electrically connected to the wiring board 65. That is, a contact hole is formed at a predetermined position of the insulating layer 82 formed on the wiring board 65, and a plating layer 83 of nickel or the like is formed in the contact hole, and a part of the wiring pattern 67 is formed on the plating layer 83. By overlapping the wiring pattern 67, the wiring pattern 67 and the wiring board 65 can be electrically connected.

  Other wiring patterns 67 are kept insulated from the wiring board 65. In the present embodiment, only the wiring pattern 67 connected to the emitter electrode 76 is electrically connected to the wiring substrate 65 made of a silicon substrate. By making the emitter electrode 76 and the wiring board 65 electrically conductive, the wiring board 65 becomes a shield plate and a shielding effect can be obtained, and adverse effects due to noise can be suppressed.

  Here, as the wiring pattern 67 formed on the wiring substrate 65, only a pattern for making the base and emitter electrodes of the transistor redundant is formed, but a pattern other than the redundant pattern may be formed if necessary.

  When aluminum is used for the wiring pattern 67, as described above, a passivation film made of an insulator such as a PSG film, SiN, SiNx or the like is formed on the wiring substrate 65, and the passivation film on the wiring pattern 67 is selectively used. The surface of the wiring pattern 67 on which the bump electrode 68 is formed is exposed. Further, chromium, copper, or the like is selectively plated in the exposed region to form a plated layer 69 to prevent problems due to corrosion of the wiring pattern 67. A bump electrode 68 made of a metal such as gold having a height of about 3 μ to 25 μ is formed on the plating layer 69, and the bump electrode 68 is in contact with the connection electrode 77 formed in the external connection electrode regions 63 A and 64 A. And electrical conduction is established. As described above, the resin layer 78 for bonding the semiconductor substrate 60 and the wiring substrate 65 includes various materials. For example, a thermosetting resin such as an acrylic resin that is cured by ultraviolet rays and a thermosetting resin such as an epoxy resin. It is assumed that a hybrid type photothermosetting resin mixed with a curable resin is used. A photothermosetting resin is applied onto the substrate 60, and the base electrode 75, the emitter electrode 76 and the connection electrodes 77 formed on the external connection electrode regions 63A and 64A formed on the active element formation region 61 and the wiring substrate. The two substrates 60 and 65 are aligned and brought into close contact so that the bump electrodes 68 formed on 65 coincide with each other.

  Thereafter, a heat treatment of about 80 ° C. to 100 ° C. is performed to thermally cure the resin layer 78, and the substrates 60 and 65 are fixed and integrated. At this time, the electrodes 75, 76, 77 and the bump electrode 68 are in contact with each other and are electrically connected, but are not in a sufficiently conductive state. Thereafter, curing of the photocurable resin in the resin layer 78 is started by irradiating with ultraviolet rays, and both the substrates 60 and 65 are attracted to each other by the contraction force at the time of curing of the photothermosetting resin. 75, 76, 77 and the bump electrode 68 are sufficiently kept in contact with each other to ensure electrical conduction. The resin layer 78 provides good conduction between the electrodes 75, 76, 77 and the bump electrode 68, and simultaneously bonds the two substrates 60, 65 together.

  By the way, when the height of the bump electrode 68 formed on the wiring pattern 67 is low, it is preferable to form the bump electrode also on each electrode formed on the substrate 60. If the bump electrode 68 formed on the wiring pattern 67 is too low, the distance between the substrates 60 and 65, that is, the film thickness of the resin layer 78 becomes thin. There is a possibility that the distal end portion of 80 reaches the surface of the wiring board 65 and the wiring pattern 67 is disconnected, and it is necessary to sufficiently consider the distance between the boards 60 and 65.

  The active element formation region 61 and the external connection electrode regions 63A and 64A formed on the same substrate 60 are electrically separated from each other by the slit holes 80 formed from the back surface side of the substrate 60. 63A and 64A become the external connection electrodes 62, 63 and 64 of the transistor.

  That is, the substrate 60 in the active element formation region 61 is the external connection electrode 62 for the collector electrode of the transistor, the substrate 60 in the one external connection electrode region 64A is the external connection electrode 64 for the base electrode of the transistor, and other external connection electrodes. The substrate 60 in the connection electrode region 63A becomes the external connection electrode 63 for the emitter electrode of the transistor. The same semiconductor substrate 60 is used, and the external connection electrodes 62, 63, 64 of each electrode of the transistor are formed on the same plane. Will be formed.

  As described above, the high concentration diffusion layer 81 is formed in the electrode regions 64A and 63A to be the external connection electrode 64 for the base electrode of the transistor and the external connection electrode 63 for the emitter electrode. The loss due to the wiring resistance between the base electrode external connection electrode 64 and the emitter electrode 76 and the emitter electrode external connection electrode 63 is reduced. The high-concentration diffusion layer 81 is formed in the diffusion step of forming the emitter region 72 as described above when the epitaxial layer 66 in the electrode regions 64A and 63A is relatively thin.

  When the film thickness of the epitaxial layer 60 is relatively large, N + type impurities are deposited on the electrode regions 63A and 64A before the epitaxial layer 60 is formed, and then the epitaxial layer 60 is formed and further heated. If the high concentration diffusion region 81 is grown from the substrate 60 side by performing the diffusion process, the high concentration diffusion regions 81 and 81 come into contact with each other when the emitter region 72 is formed, and the electrode regions 63A and 64A A high concentration diffusion layer 81 can be formed.

  As described above, the slit hole 80 for electrically separating the external connection electrodes 62, 63, 64 is formed so as to reach the resin layer 78 from the back surface side of the semiconductor substrate 60. For example, an ion beam, a laser, etc. Is formed by a chemical method using dry etching, wet etching, or a mechanical method using a dicing blade by a dicing apparatus. The slit hole 80 can be formed by any of the above methods.

  What is important here is that if the depth of the slit hole 80 becomes shallow, the electrical connection between the external connection electrodes 62, 63, 64 is not sufficiently performed, and a short circuit failure occurs. The front end portion (bottom portion) of the slit hole 80 is formed so as to be within the resin layer 78 by about 2 μ to 6 μ so that 63 and 64 are completely electrically separated. The external connection electrodes 62, 63, 64 are completely separated and partitioned by the slit hole 80, but are supported and fixed on the same plane by the resin layer 78. In addition, a plating layer such as solder plating is formed on the surface of the substrate 60 to be the external connection electrodes 62, 63, 64, so that the solder connection with the conductive pattern formed on the wiring substrate is improved.

  A semiconductor device in which a slit hole 80 is provided in a semiconductor substrate 60 and the external connection electrodes 62, 63, 64 of the transistor are electrically separated includes a ceramic substrate, a glass epoxy substrate, a phenol substrate, and a metal substrate subjected to insulation treatment. It is fixedly mounted on a pad of a conductive pattern formed on a wiring board such as. A solder layer in which solder cream is pre-printed is formed on the pad, and the semiconductor device can be fixedly mounted on the pad of the wiring board by melting the solder and mounting the semiconductor device of the present invention. . Although not shown, this fixed mounting process can be performed in the same process as the mounting process of other circuit elements to be mounted by solder such as chip capacitors and chip resistors mounted on the mounting substrate.

  When the semiconductor device of the present invention is mounted on the wiring board, the external connection electrodes 62, 63, 64 are separated by the interval of the slit holes 80, so that the solder that is fixed to the mounting board is disposed adjacently. The external connection electrodes 62, 63, 64 are not short-circuited.

  By the way, as shown in FIG. 2, in the semiconductor device of this embodiment, for example, the active element active element forming region 61 having substantially the same function as the semiconductor device described in the conventional example is 0.5 mm × 0.5 mm in size, In the semiconductor device in which the connection electrode regions 63A and 64A serving as the base and emitter electrodes are 0.3 mm × 0.2 mm in size and the width of the slit hole 80 is 0.1 mm, the effective area ratio is as follows. That is, the element area is 0.25 mm, and the area of the semiconductor device as the mounting area is 1.28 mm, so that the effective area ratio is about 19.53%.

  Since the effective area ratio of the semiconductor device having the chip size of 0.40 mm × 0.40 mm described in the conventional example is 6.25% as described above, the effective area ratio of the semiconductor device of the present invention is about 3. It becomes 12 times larger, the dead space of the mounting area to be mounted on the mounting board can be reduced, and it can contribute to the downsizing of the mounting board.

  In the present embodiment, the external connection electrodes 62, 63, and 64 are arranged so as to form a triangle in consideration of the ease of connection with the mounting board. However, if the external connection electrodes 62, 63, and 64 are arranged on a straight line, The unused area on the semiconductor substrate 60 can be eliminated, and the effective area ratio can be further improved.

  As described above, according to the semiconductor device of the present invention, the wiring substrate on which the wiring pattern connected to the base region and the emitter region is fixedly disposed on the semiconductor substrate, and a plurality of slit holes formed in the semiconductor substrate. The element region and the external connection electrode region are separated from each other by the external connection poles for the collector region, the base region, and the emitter region, and the wiring pattern connected to the emitter electrode is electrically connected to the wiring substrate. By using the same potential as the wiring board, the metal lead terminals connected to the external electrodes and the protective sealing mold are not required as in conventional semiconductor devices, and the external dimensions of the semiconductor device are significantly reduced. In addition, it is possible to provide a semiconductor device with improved shielding effect and excellent anti-noise characteristics.

  Further, as described above, the metal lead terminal for external connection and the mold for resin sealing are unnecessary, so that the manufacturing cost of the semiconductor device can be significantly reduced.

  In the present embodiment, the transistor is formed in the active element formation region 61. However, the transistor is not limited to this as long as it is a vertical type or a horizontal type device with a relatively small amount of heat generation. Needless to say, the invention can be applied.

  By the way, in the above-described embodiment, the photothermosetting resin is used for the resin layer 78 to electrically connect the electrodes of the substrate 60 and the wiring pattern of the wiring substrate 65. The continuity can be applied to any means. For example, even if an anisotropic conductive resin is used as the resin layer 78 as shown in FIG. 3, the connection of each electrode of the substrate 60 and the wiring pattern of the wiring substrate 65 is easy. Can be done.

  Anisotropic conductive resins include those in which conductive material 81 having a particle size is mixed in a resin paste and those in which conductive material having a particle size is dispersed in a resin sheet. Either type of resin can be used. It is. The anisotropic conductive resin is electrically connected through a conductive material 81 having a grain size in a region where wiring patterns and the like formed on both substrates 60 and 65 overlap. When an anisotropic conductive resin is used, it is preferable to form bump electrodes 68 on the electrodes 75, 76, 77 on the substrate 60 and the wiring pattern 67 on the wiring substrate 65.

  For example, an anisotropic conductive sheet is disposed on the substrate 60 and aligned so that the bump electrodes 68 on the substrate 60 and the bump electrodes 68 on the wiring substrate 65 coincide with each other. The conductive sheet is melted to form a resin layer 78 by applying a heat treatment at about 120 ° C. while adding the conductive material 81, and the electrodes 75, 76, 77 are electrically connected to the wiring pattern 67 by the conductive material 81 having a particle size. By forming the bump electrode 68 on each of the electrodes 75, 76, 77 and the wiring pattern 67, the conductive material of the anisotropic conductive resin is not brought into contact with the guard ring electrode overlapping the wiring pattern 67. The bump electrode 68 of each electrode 75, 76, 77 and the bump electrode 68 on the wiring board 65 are surely in contact with each other, and electrical conduction is performed.

  As another electrical conduction method, as shown in FIG. 4, the bump electrodes 83 and 83 formed on the both substrates 60 and 65 are aligned so that the both substrates 60 and 65 coincide with each other, and are melted to form bump electrodes. 83 and 83 are connected, and electrical connection between the electrodes 75, 76, 77 on the substrate 60 and the wiring pattern 67 on the wiring substrate 65 is performed. Thereafter, while applying pressure to both the substrates 60 and 65, an impregnating material made of a liquid thermosetting resin is poured between the substrates 60 and 65 to perform heat treatment, thereby forming the resin layer 78, and the slit holes 80 are formed.

  In the present invention, any structure and any material can be used as long as each electrode 75, 76, 77 and the wiring pattern 67 are connected.

  As described in detail above, according to the semiconductor device of the present invention, the wiring substrate on which the wiring pattern connected to the base region and the emitter region is formed is fixedly disposed on the semiconductor substrate and formed on the semiconductor substrate. The element region and the external connection electrode region are separated from each other by a plurality of slit holes, and are used as external connection electrodes for the collector region, base region, and emitter region, respectively, and the wiring pattern connected to the emitter electrode is electrically connected to the wiring substrate. By setting the emitter electrode and the wiring board to the same potential, the metal lead terminal connected to the external electrode and the protective sealing mold are unnecessary as in the conventional semiconductor device, and the external dimensions of the semiconductor device Can be remarkably reduced in size and the shielding effect can be improved, and a semiconductor device having excellent anti-noise characteristics can be provided.

  Further, as described above, the metal lead terminal for external connection and the mold for resin sealing are unnecessary, so that the manufacturing cost of the semiconductor device can be significantly reduced.

Sectional drawing which shows the semiconductor device of this invention. The figure which shows the back surface of the semiconductor device of this invention. Sectional drawing which shows the semiconductor device of this invention. Sectional drawing which shows the semiconductor device of this invention. Sectional drawing which shows the conventional semiconductor device. Sectional drawing of a general transistor. Sectional drawing which mounted the conventional semiconductor device on the wiring board. The top view of the conventional semiconductor device. The top view of the conventional semiconductor device. The figure which shows the conventional semiconductor device. The figure which shows the conventional semiconductor device.

Explanation of symbols

60: Semiconductor substrate 61: Active element formation region 65: Wiring substrate 67: Wiring pattern

Claims (1)

A conductive silicon substrate; an insulating layer provided on a surface of the silicon substrate; a contact hole provided in the insulating layer; and the contact hole provided on the silicon substrate having the insulating layer. A substrate made of silicon having a wiring pattern electrically connected to the silicon substrate at one end, and a passivation film having an opening in which the other end of the wiring pattern is exposed and covering the silicon substrate; ,
Mounted on a substrate made of silicon, and having a semiconductor substrate made of silicon on which active elements are formed on the surface;
Electrically connecting the active element of the semiconductor substrate and the other end of the wiring pattern exposed from the opening; electrically connecting one end of the wiring pattern to the silicon substrate;
A semiconductor device characterized in that the substrate made of silicon is made of silicon constituting the semiconductor substrate, thereby suppressing generation of thermal stress and providing a shielding effect to the substrate made of silicon.