JPH10125855A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve effective area ratio of a semiconductor device. SOLUTION: This device consists of the following; a first semiconductor chip 61 wherein a transistor is formed in a semiconductor device, a second semiconductor chip 81 wherein an integrated circuit is formed, and a plurality of external part connecting means 62, 82... which are electrically connected to electrode pads arranged on the surfaces of both the semiconductor chips 61, 81. Both of the semiconductor chips 61, 81 are adjacently arranged, electrically connected with each other, and electrically connected to the external part connecting means arranged in the vicinity of the chips. Main surfaces of the external part connecting means and the first and the second semiconductor chips 61, 81 are exposed and fixed by using resin 110 for sealing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having an improved effective mounting area ratio represented by a ratio of a chip area of the semiconductor device to a mounting area for mounting the semiconductor device on a mounting board such as a printed board.

[0002]

2. Description of the Related Art Generally, a semiconductor device in which a transistor element is formed on a silicon substrate mainly has a structure as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.

As shown in FIG. 3, a transistor element formed on a silicon substrate 11 is, for example, an N-type epitaxial layer 1 serving as a collector region on an N-type silicon substrate 11.
2, a P-type impurity such as boron is diffused into the base region 13.
Is formed, and an N-type impurity such as phosphorus is diffused in base region 13 to form emitter region 14. Base region 13 and emitter region 14 are provided on the surface of silicon substrate 11.
An insulating film 15 having an opening exposing a part of the base region 13 and the exposed emitter region 14 is formed.
A metal such as aluminum is deposited on the base electrode 16,
An emitter electrode 17 is formed. In the transistor having such a configuration, the silicon substrate becomes the collector electrode 18.

As described above, the silicon substrate 1 on which the transistor elements are formed is fixedly mounted on an island 2 such as a copper-based heat radiating plate via a brazing material 5 such as solder, as shown in FIG. The base electrode and the emitter electrode of the transistor element are electrically connected to the lead terminals 3 arranged around the substrate 1 by wires by wire bonding. The lead terminal connected to the collector electrode is formed integrally with the island, and after being electrically connected by mounting a silicon substrate on the island, transfer molding is performed using a thermosetting resin 4 such as an epoxy resin. A semiconductor device having a three-terminal structure is provided by completely covering and protecting a silicon substrate and part of a lead terminal.

[0005]

A resin-molded semiconductor device is usually mounted on a mounting substrate such as a glass epoxy substrate, and is electrically connected to other semiconductor devices and circuit elements mounted on the mounting substrate. It is handled as one component for performing a predetermined circuit operation. FIG. 10 is a cross-sectional view of a semiconductor device mounted on a mounting substrate, wherein 20 is a semiconductor device, 21 and 23 are lead terminals for base or emitter electrodes, 22 is a lead terminal for collector, and 30 is a mounting substrate. It is.

The mounting area where the semiconductor device 20 is mounted on the mounting board 30 is represented by a region surrounded by the lead terminals 21, 22, and 23 and conductive pads connected to the lead terminals. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, and most of the mounting area is taken by the mold resin and the lead terminals as compared with the area of the semiconductor chip having an actual function.

Here, considering the ratio between the area of the semiconductor chip having the actual function and the mounting area as the effective area ratio,
It has been confirmed that a resin-molded semiconductor device has an extremely low effective area ratio. The low effective area ratio means that
When the semiconductor device 20 is used for connection with another circuit element on the mounting board 30, most of the mounting area becomes a dead space which is not directly related to a semiconductor chip having a function. If the effective area ratio is small, the dead space on the mounting substrate 30 increases as described above, which hinders the high-density and miniaturization of the mounting substrate 30.

In particular, this problem appears remarkably in a semiconductor device having a small package size. For example, as shown in FIG. 11, the maximum size of a semiconductor chip mounted on the SC-75A outer shape of the EIAJ standard is 0.40 mm × 0.40 mm.
mm is the largest. When this semiconductor chip is connected to metal lead terminals by wires and resin-molded, the overall size of the semiconductor device becomes 1.6 mm × 1.6 mm. The chip area of this semiconductor device is 0.16 mm, and the mounting area for mounting the semiconductor device is 2.56 mm, assuming that it is almost the same as the area of the semiconductor device. Therefore, the effective area ratio of this semiconductor device is about 6.25. %, And most of the mounting area is a dead space that is not directly related to the area of the semiconductor chip having functions.

The problem relating to the effective area ratio is particularly prominent in a semiconductor device having a very small package size and a large chip size as described above. However, the semiconductor chip is wire-connected with metal lead terminals and resin-molded. A similar problem arises with a resin-sealed semiconductor device. In recent years, mounting substrates used in electronic devices, for example, portable information processing devices such as personal computers and electronic organizers, 8 mm video cameras, mobile phones, cameras, liquid crystal televisions, etc. There is also a tendency for high-density and small-sized mounting boards to be used.

However, in the above-mentioned prior art resin-encapsulated semiconductor device, as described above, the mounting area for mounting the semiconductor device has a large dead space. Has been one of the factors that hindered the miniaturization of the system. Incidentally, Japanese Patent Application Laid-Open No. 3-248551 is a prior art for improving the effective area ratio. This prior art will be briefly described with reference to FIG. In this prior art, lead terminals 41, 42, and 43 connected to a base, an emitter, and a collector electrode of a semiconductor chip 40 are formed in order to minimize a mounting area when a resin mold type semiconductor device is mounted on a mounting substrate or the like. It is described that the lead terminals 41, 42, and 43 are formed so as not to be led out from the side surface of the resin mold 44 and to be flush with the side surface of the resin mold 44.

According to this structure, the lead terminals 41, 4
The mounting area can be reduced by the extent that the leading end portions of 2, 43 are not led out, and the effective area ratio can be slightly improved. However, in the above-described semiconductor device, the tip end of the lead terminal connected to the semiconductor chip is formed by the resin mold 44.
Since it is bent at the corner of the bottom of the resin, it has a structure that can sufficiently withstand the stress during the bending process, so each lead terminal embedded in the resin mold must have a sufficient length, As a result, the resin mold size becomes larger than the semiconductor chip size to be mounted, and the effective area ratio does not decrease. Furthermore, each lead terminal connected to a semiconductor chip is required, and material cost and a manufacturing process become complicated, and there is a problem that manufacturing cost cannot be reduced.

In order to maximize the effective area ratio, as described above, the semiconductor chip is directly mounted on the mounting board, so that the semiconductor chip area and the mounting area are almost the same and the effective area ratio is maximized. . As one prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-6-338504, a flip chip in which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 is mounted on a mounting substrate. A technique for performing face-down bonding on a surface 47 is known (see FIG. 13). In this prior art, a gate (base) electrode, a source (emitter) electrode,
A drain (collector) electrode is formed, and a current or voltage path is formed in a lateral direction, and is mainly used for a lateral semiconductor device having a relatively small amount of heat generation.

However, in a vertical semiconductor device such as a transistor device in which a silicon substrate becomes one of the electrodes, each electrode is formed on a different surface, and a current path flows in a vertical direction, the above-mentioned flip chip technology is used. It is difficult to do. As another prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-7-38334, a semiconductor chip 53 is mounted on a conductive pattern 52 formed on a mounting substrate 51 by die. Conductive pattern 5 bonded and placed around semiconductor chip 53
A technique for connecting the electrodes of the semiconductor chip 2 and the semiconductor chip 53 with wires 54 is known (see FIG. 14). In this prior art, the above-described silicon substrate can be used for a semiconductor chip such as a transistor having a vertical structure in which one electrode forms one electrode.

The wire 54 for connecting the semiconductor chip 53 and the conductive pattern 52 disposed around the semiconductor chip 53 is usually a gold wire, and therefore, the peel strength (tensile force) of the bonding joint connected to the gold wire by bonding. Is preferably performed in a heating atmosphere at about 200 ° C. to 300 ° C. However, when a semiconductor chip is die-bonded on an insulating resin-based mounting substrate, the mounting substrate may be distorted when heated to the above-mentioned temperature, and a chip capacitor and a chip resistor mounted on the mounting substrate may be distorted. Since the solder for fixing other circuit elements is melted, the wire bonding connection is performed at a heating temperature of about 100 ° C. to about 150 ° C.,
There is a problem that the peel strength of the bonding portion is reduced.

In this prior art, usually, the die-bonded semiconductor chip is covered and protected with a sealing resin such as an epoxy resin, so that the decrease in peel strength is caused by shrinkage of the epoxy resin during thermosetting or the like. There is a problem that is peeled off. The present invention has been made in view of the circumstances described above, and the present invention provides an external connection for input / output of each semiconductor chip of a composite semiconductor device including a transistor and a semiconductor chip on which an integrated circuit is formed. The electrodes are arranged on the same plane to maximize the effective area ratio, which is the ratio of the area of each semiconductor chip to the mounting area of a single semiconductor device mounted on the mounting board, and minimize the dead space of the mounting area. Provided is a composite semiconductor device that is as small as possible.

[0016]

The present invention employs the following constitution and manufacturing method to solve the above-mentioned problems. That is, the semiconductor device of the present invention is provided on a first semiconductor chip having a transistor formed in a semiconductor substrate, a second semiconductor chip having an integrated circuit formed thereon, and provided on the surfaces of the first and second semiconductor chips. A plurality of external connection means electrically connected to the electrode pads, wherein the first and second semiconductor chips are arranged adjacent to each other, are electrically connected, and are arranged in the vicinity thereof. An electrical connection is made with the external connection means, and the main surfaces of the external connection means and the first and second semiconductor chips are exposed and fixed with a sealing resin.

Here, the plurality of external connection means and one main surface of the first and second semiconductor chips are arranged on the same plane. As described above, according to the semiconductor device of the present invention, the first semiconductor chip on which the transistor is formed and the second semiconductor chip on which the integrated circuit is formed are arranged adjacent to each other, and arranged near each semiconductor chip. Electrical connection between the plurality of external connection means and the first and second semiconductor chips, and first and second semiconductor chips serving as external electrodes for mounting and fixing on a mounting board such as a wiring board; and By fixing with a sealing resin to expose one main surface of the plurality of external connection means, a metal lead terminal for connecting an external electrode for mounting a semiconductor chip, unlike a conventional semiconductor device, becomes unnecessary. In addition, since the lead terminals and other lead terminals connected to the surface electrodes of the semiconductor chip are not led out of the sealing mold resin, the composite semiconductor device includes a plurality of semiconductor chips. It can also significantly reduce the size of the appearance dimension.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the semiconductor device according to the present invention will be described. FIG. 1 shows a semiconductor device according to the present invention.
As shown in FIG. 5, a first semiconductor chip 61 on which a transistor is formed, a second semiconductor chip 81 on which an integrated circuit is formed, and a plurality of external chips electrically connected to surface electrodes of the semiconductor chips 61 and 81. Connecting means 62, 82, 83,
84, 85 and first and second semiconductor chips 61, 81
And the sealing resin 110 for fixing the external connection means 62, 82, 83, 84, 85.

In the first semiconductor chip 61, transistors are formed. For example, as shown in FIG. 3, an N- type epitaxial layer 12 is formed on an N + type single crystal silicon substrate 11 by an epitaxial growth technique. An active element such as an NPN transistor is formed on the semiconductor substrate 11. On the other hand, an integrated circuit is formed on the second semiconductor chip 81.

The present invention is particularly applicable to a device having a so-called vertical structure having external connection electrodes on the front and back surfaces of the first and second semiconductor chips 61 and 81. FIG.
FIG. 2 is a cross-sectional view of the general NPN transistor described above. For example, a transistor in which an N− type epitaxial layer 12 is used as a collector region is formed. A photoresist is formed on a semiconductor substrate 11 and is formed by a photoresist. P-type impurities such as boron (B) are selectively thermally diffused into the exposed regions to form island-like base regions 13 having a predetermined depth.

After the formation of the base region 13, a photoresist is formed again on the semiconductor substrate 11, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively heated in the base region 13 exposed by the photoresist. The diffusion forms the emitter region 14 of the transistor. When forming the emitter region 14, a ring-shaped guard ring N + type diffusion region surrounding the base region 13 may be formed in some cases.

The base region 1 is provided on the surface of the semiconductor substrate 11.
An insulating film 15 such as a silicon oxide film or a silicon nitride film having a base contact hole exposing the three surfaces and an emitter contact hole exposing the emitter region surface is formed. Base region 13 and emitter region 14 exposed by base contact hole and emitter contact hole
A base electrode 16 and an emitter electrode 17 and a pad (not shown) for external connection of these electrodes are formed on the base electrode 16 and the emitter electrode 17 selectively deposited by a metal material such as aluminum. A metal plating process is performed on the back surface of the semiconductor substrate 11 to be used as the collector electrode 18.

As the second semiconductor chip 81, for example, a single-crystal P-type semiconductor substrate is used.
An integrated circuit such as an SIC is formed. For example, as shown in FIG. 4, a photomask of a predetermined shape is formed on a P-type semiconductor substrate, and an N-type high concentration impurity such as antimony is diffused to form an island-shaped N + type buried collector region 101. You. After removing the photomask, the N− type epitaxial layer 102 is formed on the substrate 100 by an epitaxial growth technique.
Is formed.

A mask for exposing the isolation diffusion region is formed on the epitaxial layer 102, and a P + type impurity such as boron is diffused into the isolation diffusion region to form an isolation diffusion region 103.
The N-type region serving as the active region of the transistor is surrounded by the P-type impurity by the isolation diffusion region 103.

A photoresist is formed on the epitaxial layer 102, and a P-type impurity such as boron (B) is selectively thermally diffused into a region exposed by the photoresist to form an island-shaped base region 104 having a predetermined depth. Is formed. After the formation of the base region 104, a photoresist is formed again on the epitaxial layer 102, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively formed in the base region 104 and the collector region exposed by the photoresist. By thermal diffusion, an emitter region 105 and a collector contact diffusion region 106 of the transistor are formed.

An insulating film such as a silicon oxide film or a silicon nitride film having a base contact hole exposing the surface of the base region 104, an emitter contact hole exposing the surface of the emitter region 105, and a collector contact hole exposing the surface of the collector contact diffusion region. 107 is formed. Base region 10 exposed by base contact hole, emitter contact hole, and collector contact hole
4. Emitter region 106, collector contact region 10
7, a base electrode 107, an emitter electrode 108, and a collector electrode 109 selectively formed of a metal material such as aluminum are formed.

A feature of the present invention is that an external connection electrode pad (base electrode, emitter electrode, etc.) provided on the surface side of the first and second semiconductor chips 61 and 81 is connected to a plurality of external connection means. An external connection electrode (collector electrode, collector electrode, etc.) on the back surface of each semiconductor chip 61, 81 without being led out of the sealing resin 110 via 62, 82, 83, 84, 85.
(Earth electrode) on the same surface side to minimize the size of the sealing resin and to improve the effective area ratio.

External connection means 62, 82, 83, 84, 8
Reference numeral 5 is disposed near the periphery of each of the semiconductor chips 61 and 81 so as to correspond to the number of a plurality of external connection electrode pads such as bases and emitters provided on the surfaces of the first and second semiconductor chips 61 and 81. (See FIG. 2). External connection means 62,
82, 83, 84, 85 and the electrode pads for the base and the emitter of the first and second semiconductor chips 61, 81 are
The first and second semiconductor chips 6 are electrically connected by wires made of a thin metal wire such as gold or aluminum.
Numerals 1 and 81 are electrically connected by these wires. For example, as shown in FIG.
Is connected to the base electrode of the first semiconductor chip 61 by a wire, and further connected to the electrode of the second semiconductor chip 81, whereby the two semiconductor chips 61, 81 are connected. In this embodiment, the two chips are connected via the external connection electrodes. However, it is needless to say that they can be directly connected by wires.

External connection means 62, 82, 83, 84, 8
5 is not particularly limited as long as it is made of a metal piece such as copper, invar, tellurium, or a conductive material such as a silicon chip made of a silicon material. In the present embodiment, a silicon chip is used in consideration of workability and cost. Semiconductor chips 61 and 81 electrically connected by wires and silicon chips 62 and 8 for external connection
2, 83, 84 and 85 are fixed with a thermosetting sealing resin 110 such as an epoxy resin. At this time, the first and second semiconductor chips 6 serving as a collector electrode and an earth electrode
The back surface of each of the external connection silicon chips 62, 82, 83, 84, and 85 serving as input / output electrodes is arranged on the same plane.

As described above, according to the present invention, unlike the conventional semiconductor device, the metal lead terminal for connecting the external electrode for mounting the semiconductor chip is not required, and the lead terminal and the surface electrode of the semiconductor chip are not required. Since the other lead terminals connected to the semiconductor device are led out of the sealing mold resin, the external dimensions of the semiconductor device can be significantly reduced. More specifically, in the present invention, a single semiconductor device incorporates a first semiconductor chip 61 having transistors formed therein and a second semiconductor chip 81 having an integrated circuit formed therein. The back side is directly connected to the mounting substrate, and the external connection means connected to the surface electrodes of the semiconductor chips 61 and 81 is connected to the silicon chips 62 and 8.
With the structure of 2, 83, 84, 85, metal lead terminals connected to the semiconductor chips 61, 81 can be eliminated.

The following is a description of a method of manufacturing a semiconductor device according to the present invention. First, as shown in FIG.
A plurality of first and second semiconductor chips 61, 81 and a plurality of silicon chips 62, 82, 83, 84, 85 are regularly arranged on an insulating resin layer 71 such as a polyimide resin on one main surface. First and second semiconductor chips 61, 81
For example, as shown in FIG. 6, the first semiconductor chips 61 of the transistors are mounted on the n-th row and the n-th row + even-numbered row direction of the support substrate 70, and the first semiconductor chip 61 is mounted on the n + odd-numbered row direction. A second semiconductor chip 81 of an integrated circuit is mounted adjacent to the chip 61. Each semiconductor chip 6 mounted adjacently
A plurality of silicon chips 62, 82, 8
3, 84 and 85 are implemented.

The support substrate 70 is made of a material having relatively good thermal conductivity. For example, the support substrate 70 is made of copper, aluminum, ceramics, glass epoxy, or the like, and has a thickness of about 0.3 mm to 1.2 mm. Substrate is used. A polyimide resin having a thickness of about 2 μ to 5 μ is adhered on the supporting substrate 70 at a heating temperature of about 300 ° C. to about 400 ° C. The plurality of semiconductor chips 61, 81 and the plurality of silicon chips 62, 82, 83, 84, 85 heat the support substrate 70 at a heating temperature lower than the above-described heating temperature, for example, about 200 °
It is mounted on the support substrate 70 while being heated to about 300 ° C. If the heating temperature at this time is set higher than the first heating temperature, the semiconductor chips 61, 81 and the like are placed on the insulating resin layer 71.
When die-bonding is performed on the upper side, the adhesive strength becomes too high, which adversely affects peeling of the support substrate 70 described later.

In this embodiment, the external connection means 62, 8
2, 83, 84 and 85 use silicon chips as described above. These silicon chips 62, 82, 8
The sizes of 3, 84 and 85 are the same as those of the semiconductor chips 61 and 81.
Although it depends on the size, for example, when the semiconductor chip size is 0.40 to 0.8 mm × 0.40 to 0.8 mm, the silicon chip size is 0.25 to 0.5 mm × 0.
What is necessary is just to design about 25-0.5 mm. Therefore, similarly to the semiconductor chips 61 and 81, the silicon chips 62, 82, 83, 84 and 85 can be formed individually by using a well-known dicing technique on a semiconductor wafer. In the silicon chips 62, 82, 83, 84, 85 used in the present embodiment, high-concentration impurities are diffused from the surface to the opposite main surface for the purpose of reducing internal resistance.

Each chip is picked up from the individually formed silicon wafer on the support substrate 70 by a die bonding apparatus, and regularly arranged in a region designated on the support substrate 70 as shown in FIG. Then, a plurality of first and second semiconductor chips 61 and 81 and silicon chips 62, 82, 83, 84 and 85 are die-bonded in the above-described arrangement. The two die-bonded chips are temporarily fixed on the support substrate 70 by the adhesive force of the insulating resin layer 71 formed on the support substrate 70.

After mounting both chips on the support substrate 70,
As shown in FIG. 6, the external connection electrode pads formed on the surface of each of the semiconductor chips 61 and 81 and the corresponding external connection silicon chips 62, 82, 83, 84 and 85 are made of gold, aluminum or the like, respectively. Wire connection with the thin metal wire for electrical connection. At this time, for example, as shown in FIG.
In 2), the base electrode of the first semiconductor chip 61 and the electrode of the second semiconductor chip 81 are connected by wire bonding, respectively, and the first semiconductor chip 61 in which transistors are formed via the silicon chip 82 and the integrated circuit Are electrically connected to the second semiconductor chip 81 on which is formed. In this embodiment, the two chips 61 and 81 are connected via the silicon chip 82, but it is needless to say that the two chips can be directly connected by wires.

Next, as shown in FIG. 7, a thermosetting sealing resin 110 such as an epoxy resin is applied on the support substrate 70, and a heat treatment is performed at a temperature of about 150 ° C. to about 200 ° C.
A plurality of first and second semiconductor chips 61 and 81 mounted on a support substrate 70 and a plurality of silicon chips 62 and 8
2, 83, 84 and 85 are fixed with a sealing resin 110.
At this time, the semiconductor chips 61 and 81 and the silicon chip 6
The thickness of the sealing resin 110 is considered so that the surfaces of 2, 82, 83, 84 and 85 are not exposed.

After the two chips are fixed with the sealing resin 110, the supporting substrate 70 in close contact with the sealing resin 110 is peeled off from the sealing resin 110, as shown in FIG. The sealing resin 110 is subjected to scientific peeling to be dissolved using a solvent,
Alternatively, the support substrate 70 is heated to about 150 ° C. to about 200 ° C., and mechanical peeling is performed in a state where the adhesive strength of the resin layer is reduced.
After the support substrate 70 is peeled off and the surfaces of the semiconductor chips 61 and 81 and the silicon chips 62, 82, 83, 84 and 85 are exposed, at least the first and second semiconductor chips 61 fixed with the sealing resin 110 , 81 and respective silicon chips 62, 8 connected to the semiconductor chips 61, 81
The sealing resin 110 in the region including 2, 83, 84, and 85, specifically, for example, the region indicated by the arrow line in FIG. 8 and the region indicated by the dotted line in FIG. 6 is cut using a cutting device such as a dicing device. By dividing the semiconductor device into individual components, a composite semiconductor device including the transistor and the integrated circuit semiconductor chip illustrated in FIG. 1 can be manufactured.

When the effective area ratio of the semiconductor device of the present invention is compared with that of the conventional semiconductor device, the chip size of the semiconductor device described in the conventional example is 0.40 mm × 0.40.
When the semiconductor chip 61 is connected to a metal lead terminal by a wire and molded with a resin, the overall size of the semiconductor device becomes 1.6 mm × 1.6 mm. Chip area is 0.1
The mounting area for mounting the semiconductor device is 2.56 mm2 with respect to 6 mm2, assuming that the mounting area is almost the same as the area of the semiconductor device. Therefore, the effective area ratio of the conventional semiconductor device is about 6.25%
Met.

On the other hand, the semiconductor device of the present invention incorporates a transistor and a semiconductor chip of an integrated circuit, and does not require metal lead terminals even if the chip sizes are slightly different. Compared to two conventional transistors and integrated circuit semiconductor devices, the dead space of the mounting area mounted on the mounting substrate can be reduced, which can contribute to the miniaturization of the mounting substrate.

According to the above-described method for manufacturing a semiconductor device of the present invention, the semiconductor chips 61 and 81 and the silicon chips 62, 82, 83, 84 and 85 are mounted on the support substrate 70, and are electrically connected and sealed. After fixing with the resin 110, the support substrate 70 is peeled off, and at least the semiconductor chips 61 and 81 and the external connection means 62, 82, 83, 84 and 85 connected to the semiconductor chips 61 and 81 are used for sealing. Resin 1
By dividing into ten regions individually, metal lead terminals as in the conventional semiconductor device are not required, the production cost can be reduced, and a large number of semiconductor devices incorporating transistors and integrated circuits can be manufactured.

In the present embodiment, the first semiconductor chip 61
However, the invention is not limited to this as long as the device is a vertical device or a horizontal device that generates a relatively small amount of heat. For example, a semiconductor chip 61 formed with a device such as a power MOSFET, IGBT, or HBT may be used. It goes without saying that the present invention can be applied.

[0042]

As described in detail above, according to the semiconductor device of the present invention, the first semiconductor chip on which the transistor is formed and the second semiconductor chip on which the integrated circuit is formed are arranged adjacent to each other. A plurality of external connection means arranged in the vicinity of each of the semiconductor chips is electrically connected to the first and second semiconductor chips, and an external electrode serving as an external electrode for mounting and fixing on a mounting substrate such as a wiring substrate. By fixing the first and second semiconductor chips and a plurality of external connection means with a sealing resin so as to expose one main surface thereof, an external electrode connection for mounting the semiconductor chip as in a conventional semiconductor device is performed. A composite that incorporates a plurality of semiconductor chips to eliminate the need for metal lead terminals and to prevent the lead terminals and other lead terminals connected to the surface electrodes of the semiconductor chip from being led out of the sealing mold resin. Even the semiconductor device can be greatly miniaturized its appearance dimensions. As a result, the external dimensions of a semiconductor device incorporating a transistor and an integrated circuit semiconductor chip can be significantly reduced, and unnecessary dead space when mounted on a mounting substrate can be eliminated. This can greatly contribute to miniaturization.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 2 is a diagram showing a back surface of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional view of a general transistor.

FIG. 4 is a cross-sectional view of a general integrated circuit.

FIG. 5 illustrates a method for manufacturing a semiconductor device of the present invention.

FIG. 6 illustrates a method for manufacturing a semiconductor device of the present invention.

FIG. 7 illustrates a method for manufacturing a semiconductor device of the present invention.

FIG. 8 illustrates a method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a cross-sectional view of a conventional semiconductor device.

FIG. 10 is a cross-sectional view of a conventional semiconductor device mounted on a mounting substrate.

FIG. 11 is a plan view of a conventional semiconductor device.

FIG. 12 is a plan view of a conventional semiconductor device.

FIG. 13 is a cross-sectional view of a conventional semiconductor device mounted on a mounting board.

FIG. 14 is a cross-sectional view in which a conventional semiconductor device is mounted on a mounting board.

Claims (2)

[Claims] 1. A first semiconductor chip having a transistor formed in a semiconductor substrate and a second semiconductor chip having an integrated circuit formed therein.
And a plurality of external connection means provided on the surfaces of the first and second semiconductor chips and electrically connected to the electrode pads, wherein the first and second semiconductor chips are arranged adjacent to each other. Electrical connection is made, and electrical connection is made with the external connection means disposed in the vicinity thereof, exposing one main surface of the external connection means and the first and second semiconductor chips. A semiconductor device fixed by a sealing resin. 2. The semiconductor device according to claim 1, wherein said plurality of external connection means and one main surface of said first and second semiconductor chips are arranged on the same plane.