JPH1022330A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve effective area ratio. SOLUTION: An active element is formed in an active element-forming region 61 of a semiconductor substrate 60. The back of the substrate 60 of the active element-forming region 61 is made one electrode of the active element and one outer connection electrode 62 is formed. Other outer connection electrodes 63, 64 which are electrically connected with the other electrodes of the active element are formed. The electrodes 63, 64 are constituted of a part of the substrate 60 which part is isolated form the active element-forming region 61 and formed. The above-mentioned other electrodes are electrically connected with the outer connection electrodes 63, 64, by using a wiring pattern 67 formed on a wiring board 65.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having an improved effective mounting area ratio represented by a ratio of a chip area of the semiconductor device to a mounting area for mounting the semiconductor device on a mounting board such as a printed board.

[0002]

2. Description of the Related Art Generally, a semiconductor device in which a transistor element is formed on a silicon substrate mainly has a structure as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.

As shown in FIG. 6, a transistor element formed on a silicon substrate 11 has, for example, an N-type epitaxial layer 1 serving as a collector region on an N-type silicon substrate 11.
2, a P-type impurity such as boron is diffused into the base region 13.
Is formed, and an N-type impurity such as phosphorus is diffused in base region 13 to form emitter region 14. Base region 13 and emitter region 14 are provided on the surface of silicon substrate 11.
An insulating film 15 having an opening exposing a part of the base region 13 and the exposed emitter region 14 is formed.
A metal such as aluminum is deposited on the base electrode 16,
An emitter electrode 17 is formed. In the transistor having such a configuration, the silicon substrate becomes the collector electrode 18.

As described above, the silicon substrate 1 on which the transistor elements are formed is fixedly mounted on an island 2 such as a copper-based heat sink through a brazing material 5 such as solder, as shown in FIG. The base electrode and the emitter electrode of the transistor element are electrically connected to the lead terminals 3 arranged around the substrate 1 by wires by wire bonding. The lead terminal connected to the collector electrode is formed integrally with the island, and after being electrically connected by mounting a silicon substrate on the island, transfer molding is performed using a thermosetting resin 4 such as an epoxy resin. A semiconductor device having a three-terminal structure is provided by completely covering and protecting a silicon substrate and part of a lead terminal.

[0005]

A resin-molded semiconductor device is usually mounted on a wiring board such as a glass epoxy board and electrically connected to other semiconductor devices and circuit elements mounted on the mounting board. It is handled as one component for performing a predetermined circuit operation. FIG. 7 is a cross-sectional view of a semiconductor device mounted on a mounting substrate, wherein 20 is a semiconductor device, 21 and 23 are lead terminals for base or emitter electrodes, 22 is a lead terminal for collector, and 30 is a mounting substrate. It is.

The mounting area where the semiconductor device 20 is mounted on the mounting board 30 is represented by a region surrounded by the lead terminals 21, 22, and 23 and conductive pads connected to the lead terminals. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, and most of the mounting area is taken by the mold resin and the lead terminals as compared with the area of the semiconductor chip having an actual function.

Here, considering the ratio between the area of the semiconductor chip having the actual function and the mounting area as the effective area ratio,
It has been confirmed that a resin-molded semiconductor device has an extremely low effective area ratio. The low effective area ratio means that
When the semiconductor device 20 is used for connection with another circuit element on the wiring board 30, most of the mounting area becomes a dead space which is not directly related to a semiconductor chip having a function. If the effective area ratio is small, the dead space on the mounting substrate 30 increases as described above, which hinders the high-density and miniaturization of the mounting substrate 30.

In particular, this problem appears remarkably in a semiconductor device having a small package size. For example, as shown in FIG. 8, the minimum size of a semiconductor chip mounted on an EIAJ standard SC75A outer shape is 0.40 mm × 0.40 mm. When this semiconductor chip is connected to metal lead terminals by wires and resin-molded, the overall size of the semiconductor device becomes 1.6 mm × 1.6 mm. The chip area of this semiconductor device is 0.16 mm, and the mounting area for mounting the semiconductor device is assumed to be substantially the same as the area of the semiconductor device.
6 mm, the effective area ratio of this semiconductor device is about 6.
25%, which is a dead space in which most of the mounting area is not directly related to the area of the semiconductor chip having functions.

The problem regarding the effective area ratio is particularly prominent in a semiconductor device having an extremely small package size as described above. However, the semiconductor chip is wire-connected with metal lead terminals and resin-molded. A problem also occurs in a semiconductor device. In recent years, wiring boards used in electronic devices such as personal computers, portable information processing apparatuses such as electronic notebooks, 8 mm video cameras, mobile phones, cameras, liquid crystal televisions, etc. There is also a tendency for high-density miniaturization of mounting boards used.

However, in the above-mentioned prior art resin-encapsulated semiconductor device, as described above, the mounting area for mounting the semiconductor device has a large dead space. Has been one of the factors that hindered the miniaturization of the system. Incidentally, Japanese Patent Application Laid-Open No. 3-248551 is a prior art for improving the effective area ratio. This prior art will be briefly described with reference to FIG. In this prior art, lead terminals 41, 42, and 43 connected to a base, an emitter, and a collector electrode of a semiconductor chip 40 are formed in order to minimize a mounting area when a resin mold type semiconductor device is mounted on a mounting substrate or the like. It is described that the lead terminals 41, 42, and 43 are formed so as not to be led out from the side surface of the resin mold 44 and to be flush with the side surface of the resin mold 44.

According to this structure, the lead terminals 41, 4
Although the mounting area can be reduced by the extent that the leading end portions of 2, 43 are not led out and the effective area ratio can be slightly improved, the size of the dead space is not significantly improved. In order to improve the effective area ratio, it is a condition that the semiconductor chip area and the mounting area of the semiconductor device are made substantially the same. In a resin-molded semiconductor device, as in this prior art, the tip of the lead terminal is not provided. Even if the portion is not led out, it is difficult to improve the effective area ratio due to the presence of the mold resin.

In addition, in the above-mentioned semiconductor device, since a lead terminal for connecting to the semiconductor chip and a molding resin are indispensable, a step of connecting a wire between the semiconductor chip and the lead terminal and a step of injection molding of the molding resin are required. However, there is a problem that the material cost and the manufacturing process are complicated, and the manufacturing cost cannot be reduced. In order to maximize the effective area ratio, as described above, by mounting the semiconductor chip directly on the mounting board, the semiconductor chip area and the mounting area are almost the same, and the effective area ratio is maximized.

One prior art for mounting a semiconductor chip on a substrate such as a mounting substrate is disclosed in, for example, JP-A-6-338.
As shown in JP-A-504-504, there is known a technique in which a flip chip in which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 is face-down bonded to a mounting substrate 47 (see FIG. 10). This prior art usually uses MOSFE
T (gate) electrode, source (emitter) electrode, drain (collector) electrode are formed on the same main surface of a silicon substrate such as T, and current or voltage paths are formed in the horizontal direction. Mainly used for semiconductor devices.

However, in a vertical semiconductor device such as a transistor device in which a silicon substrate becomes one of the electrodes, each electrode is formed on a different surface, and a current path flows in a vertical direction, the above-described flip chip technology is used. It is difficult to do. As another prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-7-38334, a semiconductor chip 53 is mounted on a conductive pattern 52 formed on a mounting substrate 51 by die. Conductive pattern 5 bonded and placed around semiconductor chip 53
A technique for connecting the electrodes of the semiconductor chip 53 and the semiconductor chip 53 with wires 54 is known (see FIG. 11). In this prior art, the above-described silicon substrate can be used for a semiconductor chip such as a transistor having a vertical structure in which one electrode forms one electrode.

A wire 54 for connecting the semiconductor chip 53 and the conductive pattern 52 disposed around the semiconductor chip 53 is usually a gold wire, and therefore, the peel strength (tensile force) of a bonding portion bonded to the gold wire by bonding. Is preferably performed in a heating atmosphere at about 200 ° C. to 300 ° C. However, when a semiconductor chip is die-bonded on an insulating resin-based mounting substrate, the wiring substrate may be distorted when heated to the above-described temperature, and a chip capacitor, a chip resistor, etc. mounted on the mounting substrate may be distorted. Since the solder for fixing other circuit elements is melted, the wire bonding connection is performed at a heating temperature of about 100 ° C. to about 150 ° C.,
There is a problem that the peel strength of the bonding portion is reduced.

In this prior art, a die-bonded semiconductor chip is usually covered and protected with a thermosetting resin such as an epoxy resin. Therefore, a decrease in peel strength is caused by shrinkage of the epoxy resin during thermosetting or the like. There is a problem that is peeled off. The present invention has been made in view of the above circumstances, and the present invention does not require a lead terminal connected to a semiconductor chip, and a molding resin, and requires a semiconductor chip area and a mounting area mounted on a mounting board. And a semiconductor device in which the effective area ratio, which is the ratio of the semiconductor device, is minimized and the dead space of the mounting area is minimized.

[0017]

The present invention has the following features to attain the object mentioned above. That is, in the semiconductor device of the present invention, an active element is formed in a predetermined active element forming region of a substrate, and one external connection electrode is formed by using the back surface of the substrate in the active element forming region as one electrode of the active element. A semiconductor substrate having a region, another external connection electrode region electrically connected to another electrode of the active element and being a part of the substrate, and the other electrode and the other external connection electrode; A wiring board on which a metal wiring for electrically connecting the semiconductor substrate and the wiring board is integrated, and the active element of the active element is formed via the metal wiring formed on the semiconductor substrate. The other external connection electrode connected to another electrode is connected, and a slit provided in the semiconductor substrate electrically connects the one external connection electrode region and the other external connection electrode region. Is characterized by being separated into There.

Here, the wiring substrate is a silicon substrate,
A glass epoxy substrate, a ceramic substrate, or a metal thin film substrate is used. As described above, according to the semiconductor device of the present invention, an active element forming region in which an active element in which a semiconductor substrate is used as one external connection electrode is formed on a semiconductor substrate, The external connection electrode region is formed, the active element formation region and the external connection electrode region are electrically separated by a slit hole provided in the substrate, and the other electrodes of the active element are formed by metal wiring formed on the wiring substrate. By electrically connecting the semiconductor device to another external connection electrode region, unlike a conventional semiconductor device, a metal lead terminal connected to the external electrode and a sealing mold for protection are not required, and the semiconductor device is not required. The external dimensions can be significantly reduced.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the semiconductor device according to the present invention will be described. FIG. 1 shows a semiconductor device according to the present invention.
As shown in the figure, a semiconductor substrate 60, an active element forming region 61 in which an active element is formed, and one electrode of the active element formed in the active element forming region 61, and one external connection for external connection. Electrodes for external connection 63 and 64, which are electrically separated from the active element forming region 61 and use a part of the substrate 60 as an external electrode of another electrode of the active element;
A wiring board 65 on which a wiring pattern for connecting the other electrodes of the active element and the other external connection electrodes 63 and 64 is formed.

As the semiconductor substrate 60, an N + type single crystal silicon substrate is used, and an N − type epitaxial layer 66 is formed on the substrate 60 by an epitaxial growth technique. A predetermined area of the semiconductor substrate 60 is an active element forming area 61 in which active elements such as a power MOS and a transistor are formed.
And external connection electrode regions 63A and 64A which are connected to the electrodes of the active element and become external connection electrodes 63 and 64.

The active elements described above are formed in the active element forming region 61. Here, a transistor in which the N− type epitaxial layer is the collector region 66A is formed. A photoresist is formed on the active element formation region 61,
P-type impurities such as boron (B) are selectively thermally diffused into the region exposed by the photoresist to form an island-shaped base region 71 having a predetermined depth.

After forming the base region 71, a photoresist is formed again on the active element forming region 61, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively formed in the base region 71 exposed by the photoresist. Is diffused to form an emitter region 72 of the transistor. When forming the emitter region 72, a ring-shaped guard ring N + type diffusion region 73 surrounding the base region 71 may be formed in some cases.

The base region 7 is provided on the surface of the semiconductor substrate 60.
An insulating film 74 such as a silicon oxide film or a silicon nitride film having a base contact hole exposing one surface and an emitter contact hole exposing the surface of the emitter region 72 is formed. When the guard ring diffusion region 73 is formed, a guard ring contact hole exposing the surface of the diffusion region 73 is formed. The insulating film 74 is also formed on the electrode regions 63A and 64A serving as external connection electrodes, and has external connection contact holes exposing the surfaces of the electrode regions 63A and 64A.

The base region 71, the emitter region 72, the electrode regions 63A and 64A, and the guard ring diffusion region 73 exposed by the base contact hole, the emitter contact hole, the external connection contact hole, and the guard ring contact hole are selectively provided. A base electrode 75, an emitter electrode 76, and a connection electrode 77 are formed by depositing a metal material such as aluminum.

When aluminum is used for the base electrode 75, the emitter electrode 76, and the connection electrode 77, a PSG film, a passivation film made of an insulator such as SiN or SiNx is formed on the substrate 60, and the base electrode 75 Then, the passivation film on the emitter electrode 76 and the connection electrode 77 is selectively removed to expose the surfaces of the electrodes 75, 76, 77. Further, chromium, copper, or the like is selectively plated in the exposed region to form a plating layer 79, and each electrode 75,
It is necessary to prevent problems due to corrosion of 76 and 77.

The active element formation region 61 and the external connection electrode regions 63A and 64A can be formed in a predetermined arbitrary region of the semiconductor substrate 60. In this embodiment, as shown in FIG. Active element formation region 61
Are formed, and external connection electrode regions 63A and 64A are formed so as to form a triangle with the region 61 interposed therebetween.

On the surface of the semiconductor substrate 60 having the active element forming region 61 in which the transistor is formed and the external connection electrode regions 63A and 64A, a silicon-based, epoxy-based, polyimide-based or photo-curable insulating adhesive resin layer 78 is provided. The wiring board 65 is fixed via the. A wiring pattern 67 of aluminum, copper, or the like is formed on the wiring board 65, and the wiring pattern 67 allows the base electrode 75, the emitter electrode 76, and the external connection electrode region 6 of the transistor to be formed.
Electrical connection with 3A and 64A is made respectively.

As the wiring substrate 65, a substrate such as a glass epoxy substrate, a ceramic substrate, an insulated metal substrate, a phenol substrate, or a silicon substrate can be used. For example, when a silicon substrate is used as the wiring substrate 65,
An insulating layer such as SiO2 or SiNx is formed on the surface, and a metal such as aluminum is selectively deposited on the insulating layer,
A wiring pattern 67 having a predetermined shape is formed. Of these substrates, the use of a silicon substrate is most preferred.

The main reason for using a silicon substrate for the wiring substrate 65 is that, first, an existing semiconductor manufacturing apparatus can be used as it is, and it is not necessary to newly introduce equipment.
Second, when both substrates 60 and 65 are silicon substrates when they are fixed to the substrate 60, they have the same thermal expansion coefficient α, so that even when heat is generated by external heating or self-heating, the same stress is applied to the upper and lower sides to cancel each other. This is because adverse effects due to distortion of the substrates 60 and 65 can be suppressed.

As the wiring pattern 67 formed on the wiring board 65, only a pattern for making the base and emitter electrodes of the transistor redundant is formed here, but a pattern other than the redundant pattern may be formed as necessary. .
When aluminum is used for the wiring pattern 67, as described above, the PSG film, SiN, S
A passivation film made of an insulator such as iNx is formed, the passivation film on the wiring pattern 67 is selectively removed, and the wiring pattern 6 on which the bump electrode 68 is formed is formed.
7 is exposed. Further, chrome, copper, or the like is selectively plated in the exposed region to form a plating layer 69, thereby preventing a problem due to corrosion of the wiring pattern 67.
A bump electrode 68 made of a metal such as gold having a height of about 3 μ to 25 μ is formed on the plating layer 69.
By virtue of 8, contact is made with the connection electrodes 77 formed in the external connection electrode regions 63A and 64A, and electrical conduction is achieved.

As described above, the resin layer 78 for bonding the semiconductor substrate 60 and the wiring substrate 65 includes various materials. For example, a photo-curable resin such as an acrylic resin that is cured by ultraviolet rays and an epoxy resin or the like are used. And a thermosetting resin of a hybrid type mixed with the thermosetting resin. A photothermosetting resin is applied on the substrate 60, and the base electrode 75, the emitter electrode 76, and the external connection electrode region 63 of the transistor formed on the active element formation region 61 are formed.
A, connection electrode 77 formed on 64A and wiring board 65
The two substrates 60 and 65 are aligned and brought into close contact with each other so that the bump electrodes 68 formed thereon match.

Thereafter, a heat treatment at about 80 ° C. to 100 ° C. is performed to thermally cure the resin layer 78, and the two substrates 60 and 65 are fixedly integrated. At this time, each of the electrodes 75, 76, 77 and the bump electrode 68 are in contact with each other and electrical conduction is performed.
Not sufficiently conductive. Then, the photocurable resin in the resin layer 78 starts to be cured by irradiating ultraviolet rays, and the substrates 60 and 65 are attracted to each other by the contraction force at the time of curing of the photothermosetting resin. 75, 76,
The contact between the bump electrode 77 and the bump electrode 68 is sufficiently maintained, and electrical conduction is ensured. The resin layer 78 includes the electrodes 75, 76,
77 and the bump electrode 68 are satisfactorily conducted,
The two substrates 60 and 65 are simultaneously bonded.

When the height of the bump electrode 68 formed on the wiring pattern 67 is low, it is preferable to form a bump electrode on each of the formed electrodes on the substrate 60. If the height of the bump electrode 68 formed on the wiring pattern 67 is too low, the distance between the two substrates 60 and 65, that is, the thickness of the resin layer 78 becomes thin, and when the slit hole 80 described later is formed, the slit hole 80 is the wiring board 6
There is a possibility that the wiring pattern 67 may reach the surface of the wiring 5 and the wiring pattern 67 may be broken, and it is necessary to sufficiently consider the distance between the substrates 60 and 65.

The active element formation region 61 and the external connection electrode regions 63A and 64A formed on the same substrate 60 are separated by slit holes 80 formed from the back side of the substrate 60.
Each of them is electrically isolated, and the individual regions 61, 63A,
64A is an external connection electrode 62, 63, 6 of the transistor
It becomes 4. That is, the substrate 60 of the active element formation region 61 is an external connection electrode 62 for the collector electrode of the transistor, the substrate 60 of one external connection electrode region 64A is the external connection electrode 64 for the base electrode of the transistor, and another external electrode. The substrate 60 in the connection electrode region 63A becomes the external connection electrode 63 for the emitter electrode of the transistor, and
0, and the external connection electrodes 62, 63, 64 of the respective electrodes of the transistor are formed on the same plane.

The slit holes 80 for electrically separating the external connection electrodes 62, 63, 64 are formed so as to reach the resin layer 78 from the back side of the semiconductor substrate 60 as described above. , An optical method of irradiating a laser or the like, a chemical method by dry etching or wet etching, or a mechanical method using a dicing blade by a dicing device. The slit hole 80 can be formed by any of the above methods.

What is important here is that if the depth of the slit hole 80 becomes shallow, the electrodes 62, 63 and 64 for external connection are not sufficiently electrically separated, resulting in a short-circuit failure. The tip (bottom) of the slit hole 80 is formed so as to enter the resin layer 78 by about 2 to 6 μ so that the electrodes 62, 63, and 64 are completely electrically separated. Each of the external connection electrodes 6 is formed by the slit holes 80.
2, 63 and 64 are completely separated from each other,
Are supported and fixed on the same plane. In addition, a plating layer such as solder plating is formed on the surface of the substrate 60 that becomes the external connection electrodes 62, 63, and 64, thereby improving the solder connection with the conductive pattern formed on the wiring board.

The semiconductor substrate 60 is provided with a slit hole 80, and the external connection electrodes 62, 63, 64 of the transistor are provided.
Semiconductor device, which is electrically separated from a ceramic substrate,
It is fixedly mounted on a pad of a conductive pattern formed on a wiring board such as a glass epoxy board, a phenol board, and an insulated metal board. A solder layer on which solder cream is pre-printed is formed on this pad. If the semiconductor device of the present invention is mounted by melting the solder, the semiconductor device can be fixedly mounted on the pad of the wiring board. . Although not shown, this fixed mounting process can be performed in the same process as the mounting process of other circuit elements to be solder-mounted such as chip capacitors and chip resistors mounted on a mounting board.

Further, when the semiconductor device of the present invention is mounted on a wiring board, since the external connection electrodes 62, 63, and 64 are separated by the distance of the slit hole 80, the solder fixed to the mounting board is small. External connection electrodes 62 arranged adjacent to each other,
There is no short circuit between 63 and 64. By the way, as shown in FIG. 2, in the semiconductor device of the present embodiment, for example, the active element active element formation region 61 having almost the same function as the semiconductor device described in the conventional example is set to a size of 0.5 mm × 0.5 mm. Connection electrode regions 63A serving as base and emitter electrodes,
64A is 0.3mm x 0.2mm size, and slit hole 8
In a semiconductor device in which the width of 0 is 0.1 mm, the effective area ratio is as follows. That is, since the element area is 0.25 mm and the area of the semiconductor device which is the mounting area is 1.28 mm, the effective area ratio is about 19.53%.

0.40 mm × 0.40 mm explained in the conventional example
Since the effective area ratio of the semiconductor device having the chip size of 6.25% is 6.25% as described above, the effective area ratio of the semiconductor device of the present invention is about 3.12 times larger, and the semiconductor device of the present invention is mounted on a mounting substrate. The dead space of the area can be reduced, which can contribute to downsizing of the mounting substrate.

In this embodiment, the external connection electrodes 62, 63, and 64 are arranged so as to form a triangle in consideration of the ease of connection with the mounting substrate.
By arranging 3, 64 on a straight line, an unused area on the semiconductor substrate 60 can be eliminated, and the effective area ratio can be further improved. As described above, according to the present invention, the semiconductor substrate 6 electrically separated from the active element forming region 61 in which the transistor is formed on the semiconductor substrate 60 using the semiconductor substrate 60 as the external connection electrode 62 for the collector electrode.
By using a part of 0 as the external connection electrodes 63 and 64 for the base electrode 75 and the emitter electrode 76 of the transistor, a metal lead terminal connected to the external electrode and a protective seal are provided as in a conventional semiconductor device. The need for a stop mold is eliminated, the external dimensions of the semiconductor device can be significantly reduced, and the effective area ratio can be increased.

In the present embodiment, the transistor is formed in the active element formation region 61. However, the present invention is not limited to this, as long as the device is a vertical device or a horizontal device that generates a relatively small amount of heat.
It goes without saying that the present invention can be applied to devices such as power MOSFETs, IGBTs, and HBTs. By the way, in the above embodiment, the electrical conduction between each electrode of the substrate 60 and the wiring pattern of the wiring substrate 65 is performed by using a photo-thermosetting resin for the resin layer 78.
The electrical conduction between the two can be applied to any means. For example, even if an anisotropic conductive resin is used as the resin layer 78 as shown in FIG.
Can easily be connected to the wiring pattern.

The anisotropic conductive resin includes a resin in which a conductive material 81 having a particle size is mixed in a resin paste and a resin in which a conductive material having a particle size is dispersed in a resin sheet. Either type of resin is used. It is also possible. Anisotropic conductive resin is used for both substrates 6
A region where a wiring pattern or the like formed on 0 and 65 overlaps is electrically connected via a conductor 81 having a particle size. When an anisotropic conductive resin is used, it is preferable to form the bump electrodes 68 on each of the electrodes 75, 76, 77 on the substrate 60 and on the wiring pattern 67 on the wiring substrate 65.

For example, an anisotropic conductive sheet is placed on the substrate 60, and the bump electrodes 68 on the substrate 60 are aligned with the bump electrodes 68 on the wiring board 65 so as to be aligned. About 120 ° C while applying the specified pressure
The heat treatment is performed to a degree to melt the conductive sheet and the resin layer 7
8, each of the electrodes 75, 76, 7
7 and the wiring pattern 67 are conducted. Each electrode 7
5, 76, 77 and the formation of the bump electrode 68 on the wiring pattern 67 ensure that the guard ring electrode overlapping the wiring pattern 67 does not conduct because the conductive material of the anisotropic conductive resin is not in contact with the guard ring electrode. Then, the bump electrodes 68 of the electrodes 75, 76, and 77 come into contact with the bump electrodes 68 on the wiring board 65, and electrical conduction is performed.

As another method of electrical conduction, as shown in FIG. 4, bump electrodes 8 formed on both substrates 60 and 65 are formed.
The positions of the two substrates 60 and 65 are adjusted so that the positions of the substrates 3 and 83 coincide with each other, and the substrates are melted and connected to the bump electrodes 83 and 83.
Each of the electrodes 75, 76, 77 on the substrate 60 is electrically connected to the wiring pattern 67 on the wiring substrate 65. Then, while applying pressure to both substrates 60 and 65, both substrates 6
A resin layer 78 is formed by pouring an impregnating material made of a liquid thermosetting resin into the gaps 0 and 65 to form a resin layer 78, and a slit hole 80 is formed.

In the present invention, any structure and any material can be used as long as the electrodes 75, 76 and 77 and the wiring pattern 67 are connected.

[0046]

As described in detail above, according to the semiconductor device of the present invention, an active element forming region in which an active element is formed on a semiconductor substrate using the semiconductor substrate as one external connection electrode;
Forming another external connection electrode area connected to another electrode of the active element, electrically separating the active element formation area and the external connection electrode area by a slit hole provided in the substrate, and forming on the wiring substrate By electrically connecting the other electrodes of the active element and other external connection electrode regions with the provided metal wiring, a metal lead terminal connected to the external electrode and a protective The need for a sealing mold is eliminated, the external dimensions of the semiconductor device can be significantly reduced, and unnecessary dead space when mounted on a mounting substrate can be reduced. Can contribute.

Further, in the semiconductor device of the present invention, as described above, the metal lead terminal for external connection and the mold for resin sealing are unnecessary, so that the manufacturing cost of the semiconductor device can be significantly reduced. it can.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 2 is a diagram showing a back surface of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view illustrating a conventional semiconductor device.

FIG. 6 is a cross-sectional view of a general transistor.

FIG. 7 is a cross-sectional view in which a conventional semiconductor device is mounted on a wiring board.

FIG. 8 is a plan view of a conventional semiconductor device.

FIG. 9 is a plan view of a conventional semiconductor device.

FIG. 10 illustrates a conventional semiconductor device.

FIG. 11 illustrates a conventional semiconductor device.

Claims (2)

[Claims] An active element is formed in a predetermined active element forming region of a substrate, and one external connection electrode region in which the back surface of the substrate in the active element forming region is used as one electrode of the active element. A semiconductor substrate electrically connected to another electrode of the active element and having another external connection electrode region formed of a part of the substrate; and electrically connecting the other electrode and the other external connection electrode. A wiring board on which a metal wiring to be connected is formed, wherein the semiconductor substrate and the wiring board are integrated, and another electrode of the active element is formed through the metal wiring formed on the semiconductor substrate. The other external connection electrode to be connected is connected, and the one external connection electrode region and the other external connection electrode region are electrically separated by a slit provided in the semiconductor substrate. Semiconductor device characterized by Place. 2. The semiconductor device according to claim 1, wherein the wiring substrate is a silicon substrate, a glass epoxy substrate, a ceramic substrate, or a metal thin film substrate.