JPH1022330A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1022330A JPH1022330A JP8170282A JP17028296A JPH1022330A JP H1022330 A JPH1022330 A JP H1022330A JP 8170282 A JP8170282 A JP 8170282A JP 17028296 A JP17028296 A JP 17028296A JP H1022330 A JPH1022330 A JP H1022330A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrode
- active element
- semiconductor device
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特に、半導体装置のチップ面積と、半導体装置をプリン
ト基板等の実装基板上に実装する実装面積との比率で表
す実装有効面積率を向上させた半導体装置に関する。The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having an improved effective mounting area ratio represented by a ratio of a chip area of the semiconductor device to a mounting area for mounting the semiconductor device on a mounting board such as a printed board.
【0002】[0002]
【従来の技術】一般的にシリコン基板上にトランジスタ
素子が形成された半導体装置は、図5に示すような構成
が主に用いられる。1はシリコン基板、2はシリコン基
板1が実装される放熱板等のアイランド、3はリード端
子、及び4は封止用の樹脂モールドである。2. Description of the Related Art Generally, a semiconductor device in which a transistor element is formed on a silicon substrate mainly has a structure as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.
【0003】シリコン基板11に形成されるトランジス
タ素子は、図6に示すように、例えば、N型シリコン基
板11にコレクタ領域となるN型のエピタキシャル層1
2にボロン等のP型の不純物を拡散してベース領域13
が形成され、そのベース領域13内にリン等のN型の不
純物を拡散してエミッタ領域14が形成される。シリコ
ン基板11の表面にベース領域13、エミッタ領域14
の一部を露出させる開口部を有した絶縁膜15が形成さ
れ、その露出されたベース領域13、エミッタ領域14
上にアルミニウム等の金属が蒸着されベース電極16、
エミッタ電極17が形成される。このような構成のトラ
ンジスタではシリコン基板がコレクタ電極18となる。As shown in FIG. 6, a transistor element formed on a silicon substrate 11 has, for example, an N-type epitaxial layer 1 serving as a collector region on an N-type silicon substrate 11.
2, a P-type impurity such as boron is diffused into the base region 13.
Is formed, and an N-type impurity such as phosphorus is diffused in base region 13 to form emitter region 14. Base region 13 and emitter region 14 are provided on the surface of silicon substrate 11.
An insulating film 15 having an opening exposing a part of the base region 13 and the exposed emitter region 14 is formed.
A metal such as aluminum is deposited on the base electrode 16,
An emitter electrode 17 is formed. In the transistor having such a configuration, the silicon substrate becomes the collector electrode 18.
【0004】上記のように、トランジスタ素子が形成さ
れたシリコン基板1は、図5に示すように、銅ベースの
放熱板等のアイランド2に半田等のろう材5を介して固
着実装され、シリコン基板1の周辺に配置されたリード
端子3にトランジスタ素子のベース電極、エミッタ電極
とがそれぞれワイヤーボンディングによってワイヤーで
電気的に接続されている。コレクタ電極に接続されるリ
ード端子はアイランドと一体に形成されており、シリコ
ン基板をアイランド上に実装することで電気的に接続さ
れた後、エポキシ樹脂等の熱硬化型樹脂4によりトラン
スファーモールドによって、シリコン基板とリード端子
の一部を完全に被覆保護し、3端子構造の半導体装置が
提供される。As described above, the silicon substrate 1 on which the transistor elements are formed is fixedly mounted on an island 2 such as a copper-based heat sink through a brazing material 5 such as solder, as shown in FIG. The base electrode and the emitter electrode of the transistor element are electrically connected to the lead terminals 3 arranged around the substrate 1 by wires by wire bonding. The lead terminal connected to the collector electrode is formed integrally with the island, and after being electrically connected by mounting a silicon substrate on the island, transfer molding is performed using a thermosetting resin 4 such as an epoxy resin. A semiconductor device having a three-terminal structure is provided by completely covering and protecting a silicon substrate and part of a lead terminal.
【0005】[0005]
【発明が解決しようとする課題】樹脂モールドされた半
導体装置は、通常、ガラスエポキシ基板等の配線基板に
実装され、実装基板上に実装された他の半導体装置、回
路素子と電気的に接続され所定の回路動作を行うための
一部品として取り扱われる。図7は、実装基板上に半導
体装置を実装したときの断面図を示し、20は半導体装
置、21、23はベース又はエミッタ電極用のリード端
子、22はコレクタ用のリード端子、30は実装基板で
ある。A resin-molded semiconductor device is usually mounted on a wiring board such as a glass epoxy board and electrically connected to other semiconductor devices and circuit elements mounted on the mounting board. It is handled as one component for performing a predetermined circuit operation. FIG. 7 is a cross-sectional view of a semiconductor device mounted on a mounting substrate, wherein 20 is a semiconductor device, 21 and 23 are lead terminals for base or emitter electrodes, 22 is a lead terminal for collector, and 30 is a mounting substrate. It is.
【0006】実装基板30上に半導体装置20が実装さ
れる実装面積は、リード端子21、22、23とそのリ
ード端子と接続される導電パッドで囲まれた領域によっ
て表される。実装面積は半導体装置20内のシリコン基
板(半導体チップ)面積に比べ大きく、実際に機能を持
つ半導体チップの面積に比べ実装面積の殆どはモールド
樹脂、リード端子によって取られている。The mounting area where the semiconductor device 20 is mounted on the mounting board 30 is represented by a region surrounded by the lead terminals 21, 22, and 23 and conductive pads connected to the lead terminals. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, and most of the mounting area is taken by the mold resin and the lead terminals as compared with the area of the semiconductor chip having an actual function.
【0007】ここで、実際に機能を持つ半導体チップ面
積と実装面積との比率を有効面積率として考慮すると、
樹脂モールドされた半導体装置では有効面積率が極めて
低いことが確認されている。有効面積率が低いことは、
半導体装置20を配線基板30上の他の回路素子と接続
使用とする場合に、実装面積の殆どが機能を有する半導
体チップとは直接関係のないデッドスペースとなる。有
効面積率が小さいと上記したように、実装基板30上で
デットスペースが大きくなり、実装基板30の高密度小
型化の妨げとなる。Here, considering the ratio between the area of the semiconductor chip having the actual function and the mounting area as the effective area ratio,
It has been confirmed that a resin-molded semiconductor device has an extremely low effective area ratio. The low effective area ratio means that
When the semiconductor device 20 is used for connection with another circuit element on the wiring board 30, most of the mounting area becomes a dead space which is not directly related to a semiconductor chip having a function. If the effective area ratio is small, the dead space on the mounting substrate 30 increases as described above, which hinders the high-density and miniaturization of the mounting substrate 30.
【0008】特に、この問題はパッケージサイズが小さ
い半導体装置に顕著に現れる。例えば、EIAJ規格の
SC75A外形に搭載される半導体チップの最大サイズ
は、図8に示すように、0.40mm×0.40mmが最小
である。この半導体チップを金属リード端子とワイヤー
で接続し、樹脂モールドすると半導体装置の全体のサイ
ズは、1.6mm×1.6mmとなる。この半導体装置のチ
ップ面積は0.16mmで、半導体装置を実装する実装面
積は半導体装置の面積とほぼ同様として考えて、2.5
6mmであるため、この半導体装置の有効面積率は約6.
25%となり、実装面積の殆どが機能を持つ半導体チッ
プ面積と直接関係のないデットスペースとなっている。In particular, this problem appears remarkably in a semiconductor device having a small package size. For example, as shown in FIG. 8, the minimum size of a semiconductor chip mounted on an EIAJ standard SC75A outer shape is 0.40 mm × 0.40 mm. When this semiconductor chip is connected to metal lead terminals by wires and resin-molded, the overall size of the semiconductor device becomes 1.6 mm × 1.6 mm. The chip area of this semiconductor device is 0.16 mm, and the mounting area for mounting the semiconductor device is assumed to be substantially the same as the area of the semiconductor device.
6 mm, the effective area ratio of this semiconductor device is about 6.
25%, which is a dead space in which most of the mounting area is not directly related to the area of the semiconductor chip having functions.
【0009】この有効面積率に関する問題は、特に、上
記したようにパッケージサイズが極めて小さい半導体装
置において顕著に現れるが、半導体チップを金属リード
端子でワイヤー接続し、樹脂モールドする、樹脂封止型
の半導体装置であっても同様に問題となる。近年の電子
機器、例えば、パーソナルコンピュータ、電子手帳等の
携帯情報処理装置、8mmビデオカメラ、携帯電話、カ
メラ、液晶テレビ等において用いられる配線基板は、電
子機器本体の小型化に伴い、その内部に使用される実装
基板も高密度小型化の傾向にある。The problem regarding the effective area ratio is particularly prominent in a semiconductor device having an extremely small package size as described above. However, the semiconductor chip is wire-connected with metal lead terminals and resin-molded. A problem also occurs in a semiconductor device. In recent years, wiring boards used in electronic devices such as personal computers, portable information processing apparatuses such as electronic notebooks, 8 mm video cameras, mobile phones, cameras, liquid crystal televisions, etc. There is also a tendency for high-density miniaturization of mounting boards used.
【0010】しかし、上記の先行技術の樹脂封止型の半
導体装置では、上述したように、半導体装置を実装する
実装面積にデットスペースが大きいため、実装基板の小
型化に限界があり、実装基板の小型化の妨げの一つの要
因となっていた。ところで、有効面積率を向上させる先
行技術として特開平3−248551号公報がある。こ
の先行技術について、図9にもとずいて簡単に説明す
る。この先行技術は、樹脂モールド型半導体装置を実装
基板等に実装したときの実装面積をできるだけ小さくす
るために、半導体チップ40のベース、エミッタ、及び
コレクタ電極と接続するリード端子41、42、43を
樹脂モールド44の側面より外側に導出させず、リード
端子41、42、43を樹脂モールド44側面と同一面
となるように形成することが記載されている。However, in the above-mentioned prior art resin-encapsulated semiconductor device, as described above, the mounting area for mounting the semiconductor device has a large dead space. Has been one of the factors that hindered the miniaturization of the system. Incidentally, Japanese Patent Application Laid-Open No. 3-248551 is a prior art for improving the effective area ratio. This prior art will be briefly described with reference to FIG. In this prior art, lead terminals 41, 42, and 43 connected to a base, an emitter, and a collector electrode of a semiconductor chip 40 are formed in order to minimize a mounting area when a resin mold type semiconductor device is mounted on a mounting substrate or the like. It is described that the lead terminals 41, 42, and 43 are formed so as not to be led out from the side surface of the resin mold 44 and to be flush with the side surface of the resin mold 44.
【0011】この構成によれば、リード端子41、4
2、43の先端部分が導出しない分だけ実装面積を小さ
くすることができ、有効面積率を若干向上させることは
できるが、デッドスペースの大きさはあまり改善されな
い。有効面積率を向上させるためには、半導体装置の半
導体チップ面積と実装面積とをほぼ同一にするこが条件
であり、樹脂モールド型の半導体装置では、この先行技
術の様に、リード端子の先端部を導出させなくても、モ
ールド樹脂の存在によって有効面積率を向上させること
は困難である。According to this structure, the lead terminals 41, 4
Although the mounting area can be reduced by the extent that the leading end portions of 2, 43 are not led out and the effective area ratio can be slightly improved, the size of the dead space is not significantly improved. In order to improve the effective area ratio, it is a condition that the semiconductor chip area and the mounting area of the semiconductor device are made substantially the same. In a resin-molded semiconductor device, as in this prior art, the tip of the lead terminal is not provided. Even if the portion is not led out, it is difficult to improve the effective area ratio due to the presence of the mold resin.
【0012】また、上記の半導体装置では、半導体チッ
プと接続するリード端子、モールド樹脂を必要不可欠と
するために、半導体チップとリード端子とのワイヤ接続
工程、モールド樹脂の射出成形工程という工程を必要と
し、材料コスト面及び製造工程が煩雑となり、製造コス
トを低減できない課題がある。有効面積率を最大限大き
くするには、上記したように、半導体チップを直接実装
基板上に実装することにより、半導体チップ面積と実装
面積とがほぼ同一となり有効面積率が最大となる。In addition, in the above-mentioned semiconductor device, since a lead terminal for connecting to the semiconductor chip and a molding resin are indispensable, a step of connecting a wire between the semiconductor chip and the lead terminal and a step of injection molding of the molding resin are required. However, there is a problem that the material cost and the manufacturing process are complicated, and the manufacturing cost cannot be reduced. In order to maximize the effective area ratio, as described above, by mounting the semiconductor chip directly on the mounting board, the semiconductor chip area and the mounting area are almost the same, and the effective area ratio is maximized.
【0013】半導体チップを実装基板等の基板上に実装
する一つの先行技術として、例えば、特開平6−338
504号公報に示すように、半導体チップ45上に複数
のバンプ電極46を形成したフリップチップを実装基板
47フェイスダウンボンディングする技術が知られてい
る(図10参照)。この先行技術は、通常、MOSFE
T等、シリコン基板の同一主面にゲート(ベース)電
極、ソース(エミッタ)電極、ドレイン(コレクタ)電
極が形成され、電流或いは電圧のパスが横方向に形成さ
れる比較的発熱量の少ない横型の半導体装置に主に用い
られる。One prior art for mounting a semiconductor chip on a substrate such as a mounting substrate is disclosed in, for example, JP-A-6-338.
As shown in JP-A-504-504, there is known a technique in which a flip chip in which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 is face-down bonded to a mounting substrate 47 (see FIG. 10). This prior art usually uses MOSFE
T (gate) electrode, source (emitter) electrode, drain (collector) electrode are formed on the same main surface of a silicon substrate such as T, and current or voltage paths are formed in the horizontal direction. Mainly used for semiconductor devices.
【0014】しかし、トランジスタデバイス等のように
シリコン基板が電極の一つとなり、各電極が異なる面に
形成され電流のパスが縦方向に流れる縦型の半導体装置
では、上記のフリップチップ技術を使用することは困難
である。半導体チップを実装基板等の基板上に実装する
他の先行技術として、例えば、特開平7−38334号
公報に示すように、実装基板51上に形成された導電パ
ターン52上に半導体チップ53をダイボンディング
し、半導体チップ53周辺に配置された導電パターン5
2と半導体チップ53との電極をワイヤ54で接続する
技術が知られている(図11参照)。この先行技術で
は、先に述べたシリコン基板が一つの電極を構成した縦
型構造のトランジスタ等の半導体チップに用いることは
できる。However, in a vertical semiconductor device such as a transistor device in which a silicon substrate becomes one of the electrodes, each electrode is formed on a different surface, and a current path flows in a vertical direction, the above-described flip chip technology is used. It is difficult to do. As another prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-7-38334, a semiconductor chip 53 is mounted on a conductive pattern 52 formed on a mounting substrate 51 by die. Conductive pattern 5 bonded and placed around semiconductor chip 53
A technique for connecting the electrodes of the semiconductor chip 53 and the semiconductor chip 53 with wires 54 is known (see FIG. 11). In this prior art, the above-described silicon substrate can be used for a semiconductor chip such as a transistor having a vertical structure in which one electrode forms one electrode.
【0015】半導体チップ53とその周辺に配置された
導電パターン52とを接続するワイヤ54は通常、金細
線が用いられることから、金細線とボンディング接続さ
れるボンディング接合部のピール強度(引張力)を大き
くするために、約200℃〜300℃の加熱雰囲気中で
ボンディングを行うことが好ましい。しかし、絶縁樹脂
系の実装基板上に半導体チップをダイボンディングする
場合には、上記した温度まで加熱すると配線基板に歪み
が生じること、及び、実装基板上に実装されたチップコ
ンデンサ、チップ抵抗等の他の回路素子を固着する半田
が溶融するために、加熱温度を約100℃〜150℃程
度にしてワイヤボンディング接続が行われているため、
ボンディング接合部のピール強度が低下する問題があ
る。A wire 54 for connecting the semiconductor chip 53 and the conductive pattern 52 disposed around the semiconductor chip 53 is usually a gold wire, and therefore, the peel strength (tensile force) of a bonding portion bonded to the gold wire by bonding. Is preferably performed in a heating atmosphere at about 200 ° C. to 300 ° C. However, when a semiconductor chip is die-bonded on an insulating resin-based mounting substrate, the wiring substrate may be distorted when heated to the above-described temperature, and a chip capacitor, a chip resistor, etc. mounted on the mounting substrate may be distorted. Since the solder for fixing other circuit elements is melted, the wire bonding connection is performed at a heating temperature of about 100 ° C. to about 150 ° C.,
There is a problem that the peel strength of the bonding portion is reduced.
【0016】この先行技術では、通常、ダイボンディン
グされた半導体チップはエポキシ樹脂等の熱硬化性樹脂
で被覆保護されるために、ピール強度の低下はエポキシ
樹脂の熱硬化時の収縮等によって接合部が剥離されると
いう問題がある。本発明は、上述した事情に鑑みて成さ
れたものであり、本発明は、半導体チップと接続される
リード端子、及びモールド樹脂を必要とせず、半導体チ
ップ面積と実装基板上に実装する実装面積との比率であ
る有効面積率を最大限向上させ、実装面積のデットスペ
ース最小限小さくした半導体装置を提供する。In this prior art, a die-bonded semiconductor chip is usually covered and protected with a thermosetting resin such as an epoxy resin. Therefore, a decrease in peel strength is caused by shrinkage of the epoxy resin during thermosetting or the like. There is a problem that is peeled off. The present invention has been made in view of the above circumstances, and the present invention does not require a lead terminal connected to a semiconductor chip, and a molding resin, and requires a semiconductor chip area and a mounting area mounted on a mounting board. And a semiconductor device in which the effective area ratio, which is the ratio of the semiconductor device, is minimized and the dead space of the mounting area is minimized.
【0017】[0017]
【課題を解決するための手段】本発明は、上記の課題を
解決するために以下の構成を採用した。即ち、本発明の
半導体装置は、基板の所定の能動素子形成領域に能動素
子が形成され、前記能動素子形成領域の前記基板の裏面
を前記能動素子の一の電極とした一の外部接続用電極領
域と、前記能動素子の他の電極と電気的に接続され前記
基板の一部分よりなる他の外部接続用電極領域とを有し
た半導体基板と、前記他の電極と前記他の外部接続用電
極とを電気的に接続する金属配線が形成された配線基板
とを有し、前記半導体基板と前記配線基板とが一体化さ
れ、前記半導体基板上に形成された前記金属配線を介し
て前記能動素子の他の電極と接続される前記他の外部接
続用電極とが接続され、前記半導体基板に設けられたス
リットにより、前記一の外部接続用電極領域と前記他の
外部接続用電極領域とが電気的に分離したことを特徴と
している。The present invention has the following features to attain the object mentioned above. That is, in the semiconductor device of the present invention, an active element is formed in a predetermined active element forming region of a substrate, and one external connection electrode is formed by using the back surface of the substrate in the active element forming region as one electrode of the active element. A semiconductor substrate having a region, another external connection electrode region electrically connected to another electrode of the active element and being a part of the substrate, and the other electrode and the other external connection electrode; A wiring board on which a metal wiring for electrically connecting the semiconductor substrate and the wiring board is integrated, and the active element of the active element is formed via the metal wiring formed on the semiconductor substrate. The other external connection electrode connected to another electrode is connected, and a slit provided in the semiconductor substrate electrically connects the one external connection electrode region and the other external connection electrode region. Is characterized by being separated into There.
【0018】ここで、前記配線基板は、シリコン基板、
ガラスエポキシ基板、セラミックス基板、或いは金属薄
膜基板を用いることを特徴としている。上述したよう
に、本発明の半導体装置によれば、半導体基板に半導体
基板を一の外部接続用電極とした能動素子を形成した能
動素子形成領域と、能動素子の他の電極と接続される他
の外部接続電極領域とを形成し、能動素子形成領域と外
部接続電極領域とを基板に設けたスリット孔で電気的に
分離し、配線基板上に形成された金属配線で能動素子の
他の電極と他の外部接続電極領域とを電気的に接続する
ことにより、従来の半導体装置のように、外部電極と接
続する金属製のリード端子、保護用の封止モールドが不
必要となり、半導体装置の外観寸法を著しく小型化にす
ることができる。Here, the wiring substrate is a silicon substrate,
A glass epoxy substrate, a ceramic substrate, or a metal thin film substrate is used. As described above, according to the semiconductor device of the present invention, an active element forming region in which an active element in which a semiconductor substrate is used as one external connection electrode is formed on a semiconductor substrate, The external connection electrode region is formed, the active element formation region and the external connection electrode region are electrically separated by a slit hole provided in the substrate, and the other electrodes of the active element are formed by metal wiring formed on the wiring substrate. By electrically connecting the semiconductor device to another external connection electrode region, unlike a conventional semiconductor device, a metal lead terminal connected to the external electrode and a sealing mold for protection are not required, and the semiconductor device is not required. The external dimensions can be significantly reduced.
【0019】[0019]
【発明の実施の形態】以下に、本発明の半導体装置の実
施形態について説明する。本発明の半導体装置は、図1
に示すように、半導体基板60と、能動素子が形成され
る能動素子形成領域61と、能動素子形成領域61に形
成された能動素子の一の電極であり、外部接続するため
の一の外部接続用電極62と、能動素子形成領域61と
電気的に分離され基板60の一部分を能動素子の他の電
極の外部電極とする他の外部接続用電極63、64と、
能動素子の他の電極と他の外部接続用電極63、64と
を接続する配線パターンが形成された配線基板65とを
から構成されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the semiconductor device according to the present invention will be described. FIG. 1 shows a semiconductor device according to the present invention.
As shown in the figure, a semiconductor substrate 60, an active element forming region 61 in which an active element is formed, and one electrode of the active element formed in the active element forming region 61, and one external connection for external connection. Electrodes for external connection 63 and 64, which are electrically separated from the active element forming region 61 and use a part of the substrate 60 as an external electrode of another electrode of the active element;
A wiring board 65 on which a wiring pattern for connecting the other electrodes of the active element and the other external connection electrodes 63 and 64 is formed.
【0020】半導体基板60は、N+型の単結晶シリコ
ン基板が用いられ、その基板60上にエピタキシャル成
長技術によりN-型のエピタキシャル層66が形成され
る。半導体基板60の所定領域はパワーMOS、トラン
ジスタ等の能動素子が形成される能動素子形成領域61
と能動素子の電極接続され外部接続用電極63、64と
なる外部接続電極領域63A,64Aとが設けられてい
る。As the semiconductor substrate 60, an N + type single crystal silicon substrate is used, and an N − type epitaxial layer 66 is formed on the substrate 60 by an epitaxial growth technique. A predetermined area of the semiconductor substrate 60 is an active element forming area 61 in which active elements such as a power MOS and a transistor are formed.
And external connection electrode regions 63A and 64A which are connected to the electrodes of the active element and become external connection electrodes 63 and 64.
【0021】この能動素子形成領域61に上記した能動
素子が形成される。ここでは、N-型のエピタキシャル層
をコレクタ領域66Aとしたトランジスタが形成され
る。能動素子形成領域61上にホトレジストを形成し、
ホトレジストによって露出された領域にボロン(B)等
のP型の不純物を選択的に熱拡散して所定の深さを有し
た島状のベース領域71が形成される。The active elements described above are formed in the active element forming region 61. Here, a transistor in which the N− type epitaxial layer is the collector region 66A is formed. A photoresist is formed on the active element formation region 61,
P-type impurities such as boron (B) are selectively thermally diffused into the region exposed by the photoresist to form an island-shaped base region 71 having a predetermined depth.
【0022】ベース領域71形成後、能動素子形成領域
61上に再度ホトレジストを形成し、ホトレジストによ
って露出されたベース領域71内にリン(P)、アンチ
モン(Sb)等のN型の不純物を選択的に熱拡散してト
ランジスタのエミッタ領域72が形成される。このエミ
ッタ領域72を形成する際に、ベース領域71を囲むリ
ング状のガードリング用のN+型の拡散領域73を形成
しておく場合もある。After forming the base region 71, a photoresist is formed again on the active element forming region 61, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively formed in the base region 71 exposed by the photoresist. Is diffused to form an emitter region 72 of the transistor. When forming the emitter region 72, a ring-shaped guard ring N + type diffusion region 73 surrounding the base region 71 may be formed in some cases.
【0023】半導体基板60の表面には、ベース領域7
1表面を露出するベースコンタクト孔及びエミッタ領域
72表面を露出するエミッタコンタクト孔を有するシリ
コン酸化膜、或いはシリコン窒化膜等の絶縁膜74が形
成される。ガードリング用の拡散領域73を形成した場
合には、かかる、拡散領域73表面を露出するガードリ
ングコンタクト孔が形成される。この絶縁膜74は、外
部接続用電極となる電極領域63A,64A上にも形成
され、電極領域63A,64Aの表面を露出する外部接
続用コンタクト孔が形成されている。The base region 7 is provided on the surface of the semiconductor substrate 60.
An insulating film 74 such as a silicon oxide film or a silicon nitride film having a base contact hole exposing one surface and an emitter contact hole exposing the surface of the emitter region 72 is formed. When the guard ring diffusion region 73 is formed, a guard ring contact hole exposing the surface of the diffusion region 73 is formed. The insulating film 74 is also formed on the electrode regions 63A and 64A serving as external connection electrodes, and has external connection contact holes exposing the surfaces of the electrode regions 63A and 64A.
【0024】ベースコンタクト孔、エミッタコンタクト
孔、外部接続用コンタクト孔及びガードリングコンタク
ト孔によって露出されたベース領域71、エミッタ領域
72、電極領域63A,64A及びガードリング拡散領
域73上には、選択的にアルミニウム等の金属材料で蒸
着されたベース電極75、エミッタ電極76、接続用電
極77が形成される。The base region 71, the emitter region 72, the electrode regions 63A and 64A, and the guard ring diffusion region 73 exposed by the base contact hole, the emitter contact hole, the external connection contact hole, and the guard ring contact hole are selectively provided. A base electrode 75, an emitter electrode 76, and a connection electrode 77 are formed by depositing a metal material such as aluminum.
【0025】ベース電極75、エミッタ電極76、及び
接続用電極77にアルミニウムを用いた場合には、基板
60上にPSG膜、SiN、SiNx等の絶縁物からな
るパッシベーション膜を形成し、ベース電極75、エミ
ッタ電極76、接続用電極77上のパッシベーション膜
を選択的に除去し、各電極75、76、77の表面を露
出させる。さらに、露出された領域内にクロム、銅等を
選択的にメッキしてメッキ層79を形成し各電極75、
76、77の腐食による不具合を防止する必要がある。When aluminum is used for the base electrode 75, the emitter electrode 76, and the connection electrode 77, a PSG film, a passivation film made of an insulator such as SiN or SiNx is formed on the substrate 60, and the base electrode 75 Then, the passivation film on the emitter electrode 76 and the connection electrode 77 is selectively removed to expose the surfaces of the electrodes 75, 76, 77. Further, chromium, copper, or the like is selectively plated in the exposed region to form a plating layer 79, and each electrode 75,
It is necessary to prevent problems due to corrosion of 76 and 77.
【0026】能動素子形成領域61及び外部接続電極領
域63A,64Aは、半導体基板60の所定の任意の領
域に形成することができ、この実施形態では、図2に示
すように、基板60の中央部分に能動素子形成領域61
が形成され、その領域61の挟んでトライアングル形状
に成るように外部接続用電極領域63A,64Aが形成
される。The active element formation region 61 and the external connection electrode regions 63A and 64A can be formed in a predetermined arbitrary region of the semiconductor substrate 60. In this embodiment, as shown in FIG. Active element formation region 61
Are formed, and external connection electrode regions 63A and 64A are formed so as to form a triangle with the region 61 interposed therebetween.
【0027】トランジスタが形成された能動素子形成領
域61と外部接続電極領域63A,64Aとを有した半
導体基板60表面上にはシリコン系、エポキシ系或いは
ポリイミド系或いは光硬化性の絶縁接着樹脂層78を介
して配線基板65が固着される。配線基板65上にはア
ルミニウム、銅等の配線パターン67が形成されてお
り、この配線パターン67によって、トランジスタのベ
ース電極75、エミッタ電極76と外部接続電極領域6
3A,64Aとの電気的が接続がそれぞれ行われる。On the surface of the semiconductor substrate 60 having the active element forming region 61 in which the transistor is formed and the external connection electrode regions 63A and 64A, a silicon-based, epoxy-based, polyimide-based or photo-curable insulating adhesive resin layer 78 is provided. The wiring board 65 is fixed via the. A wiring pattern 67 of aluminum, copper, or the like is formed on the wiring board 65, and the wiring pattern 67 allows the base electrode 75, the emitter electrode 76, and the external connection electrode region 6 of the transistor to be formed.
Electrical connection with 3A and 64A is made respectively.
【0028】配線基板65は、ガラスエポキシ基板、セ
ラミックス基板、絶縁処理された金属基板、フェノール
基板、シリコン基板等の基板を用いることができる。例
えば、シリコン基板を配線基板65として用いた場合、
表面にSiO2或いはSiN×等の絶縁層を形成し、そ
の絶縁層上にアルミニウム等の金属を選択的に蒸着し、
所定形状の配線パターン67が形成される。これら基板
の中でシリコン基板の使用がもっとも好ましい。As the wiring substrate 65, a substrate such as a glass epoxy substrate, a ceramic substrate, an insulated metal substrate, a phenol substrate, or a silicon substrate can be used. For example, when a silicon substrate is used as the wiring substrate 65,
An insulating layer such as SiO2 or SiNx is formed on the surface, and a metal such as aluminum is selectively deposited on the insulating layer,
A wiring pattern 67 having a predetermined shape is formed. Of these substrates, the use of a silicon substrate is most preferred.
【0029】配線基板65にシリコン基板を用いる大き
な理由は、第1に、既存の半導体製造装置をそのまま使
用することができ、新たに設備導入を行う必要がない。
第2に、基板60と固着したときに両基板60、65が
共にシリコン基板であると熱膨張係数αが等しいため外
部加熱或いは自己発熱による熱発生が生じた場合でも上
下で同一応力が加わり相殺するために基板60、65の
歪による悪影響を抑制することができるためである。The main reason for using a silicon substrate for the wiring substrate 65 is that, first, an existing semiconductor manufacturing apparatus can be used as it is, and it is not necessary to newly introduce equipment.
Second, when both substrates 60 and 65 are silicon substrates when they are fixed to the substrate 60, they have the same thermal expansion coefficient α, so that even when heat is generated by external heating or self-heating, the same stress is applied to the upper and lower sides to cancel each other. This is because adverse effects due to distortion of the substrates 60 and 65 can be suppressed.
【0030】配線基板65上に形成される配線パターン
67は、ここでは、トランジスタのベース、エミッタ電
極を冗長させるパターンのみが形成されるが、必要に応
じて冗長パターン以外のパターン形成する場合もある。
配線パターン67にアルミニウムを用いた場合には、上
記したように、配線基板65上にPSG膜、SiN、S
iNx等の絶縁物からなるパッシベーション膜を形成
し、配線パターン67上のパッシベーション膜を選択的
に除去し、バンプ電極68が形成される配線パターン6
7の表面を露出させる。さらに、露出された領域内にク
ロム、銅等を選択的にメッキしてメッキ層69を形成し
配線パターン67の腐食による不具合を防止している。
メッキ層69上には、高さ約3μ〜25μの金等の金属
からなるバンプ電極68が形成され、このバンプ電極6
8により、外部接続電極領域63A,64Aに形成され
た接続電極77との接触が行われ電気的導通が成され
る。As the wiring pattern 67 formed on the wiring board 65, only a pattern for making the base and emitter electrodes of the transistor redundant is formed here, but a pattern other than the redundant pattern may be formed as necessary. .
When aluminum is used for the wiring pattern 67, as described above, the PSG film, SiN, S
A passivation film made of an insulator such as iNx is formed, the passivation film on the wiring pattern 67 is selectively removed, and the wiring pattern 6 on which the bump electrode 68 is formed is formed.
7 is exposed. Further, chrome, copper, or the like is selectively plated in the exposed region to form a plating layer 69, thereby preventing a problem due to corrosion of the wiring pattern 67.
A bump electrode 68 made of a metal such as gold having a height of about 3 μ to 25 μ is formed on the plating layer 69.
By virtue of 8, contact is made with the connection electrodes 77 formed in the external connection electrode regions 63A and 64A, and electrical conduction is achieved.
【0031】半導体基板60と配線基板65とを接着す
る樹脂層78は、上記したように、種々の材料が存在す
るが、例えば、紫外線で硬化するアクリル樹脂等の光硬
化性樹脂とエポキシ樹脂等の熱硬化性樹脂とを混合させ
たハイブリッドタイプの光熱硬化性樹脂を用いるものと
する。光熱硬化性樹脂を基板60上に塗布し、能動素子
形成領域61上に形成されたトランジスタのベース電極
75、エミッタ電極76および外部接続電極領域63
A、64A上に形成された接続電極77と配線基板65
上に形成したバンプ電極68とが一致するように両基板
60、65との位置合わせを行い密着させる。As described above, the resin layer 78 for bonding the semiconductor substrate 60 and the wiring substrate 65 includes various materials. For example, a photo-curable resin such as an acrylic resin that is cured by ultraviolet rays and an epoxy resin or the like are used. And a thermosetting resin of a hybrid type mixed with the thermosetting resin. A photothermosetting resin is applied on the substrate 60, and the base electrode 75, the emitter electrode 76, and the external connection electrode region 63 of the transistor formed on the active element formation region 61 are formed.
A, connection electrode 77 formed on 64A and wiring board 65
The two substrates 60 and 65 are aligned and brought into close contact with each other so that the bump electrodes 68 formed thereon match.
【0032】その後、約80℃〜100℃程度の加熱処
理を行い樹脂層78を熱硬化させ、両基板60、65を
固着一体化する。この時、各電極75、76、77とバ
ンプ電極68とは接触し電気的導通は行われているが、
十分な導通状態ではない。その後、紫外線を照射するこ
とで樹脂層78中の光硬化性樹脂の硬化が始まり、その
光熱硬性樹脂の硬化時の収縮力で両基板60、65が互
いに引き合わさられ、基板60上の各電極75、76、
77とバンプ電極68との接触が十分に保たれ電気的導
通が確実に行われる。樹脂層78は各電極75、76、
77とバンプ電極68とを良好に導通させるとともに、
両基板60、65の接着をも同時に行うものである。Thereafter, a heat treatment at about 80 ° C. to 100 ° C. is performed to thermally cure the resin layer 78, and the two substrates 60 and 65 are fixedly integrated. At this time, each of the electrodes 75, 76, 77 and the bump electrode 68 are in contact with each other and electrical conduction is performed.
Not sufficiently conductive. Then, the photocurable resin in the resin layer 78 starts to be cured by irradiating ultraviolet rays, and the substrates 60 and 65 are attracted to each other by the contraction force at the time of curing of the photothermosetting resin. 75, 76,
The contact between the bump electrode 77 and the bump electrode 68 is sufficiently maintained, and electrical conduction is ensured. The resin layer 78 includes the electrodes 75, 76,
77 and the bump electrode 68 are satisfactorily conducted,
The two substrates 60 and 65 are simultaneously bonded.
【0033】ところで、配線パターン67上に形成する
バンプ電極68の高さが低い場合には、基板60上の形
成した各電極上にもバンプ電極を形成することが好まし
い。配線パターン67上に形成したバンプ電極68の高
さが低すぎると両基板60、65の離間距離、即ち樹脂
層78の膜厚が薄くなり、後述するスリット孔80を形
成したときに、スリット孔80の先端部分が配線基板6
5の表面まで達し配線パターン67が断線する可能性が
あり、両基板60、65の離間距離を十分に考慮する必
要がある。When the height of the bump electrode 68 formed on the wiring pattern 67 is low, it is preferable to form a bump electrode on each of the formed electrodes on the substrate 60. If the height of the bump electrode 68 formed on the wiring pattern 67 is too low, the distance between the two substrates 60 and 65, that is, the thickness of the resin layer 78 becomes thin, and when the slit hole 80 described later is formed, the slit hole 80 is the wiring board 6
There is a possibility that the wiring pattern 67 may reach the surface of the wiring 5 and the wiring pattern 67 may be broken, and it is necessary to sufficiently consider the distance between the substrates 60 and 65.
【0034】同一基板60上に形成された能動素子形成
領域61と外部接続電極領域63A,64Aとは、基板
60の裏面側から形成されたスリット孔80によって、
それぞれ電気的に分離され、個々の領域61、63A,
64Aがトランジスタの外部接続用電極62、63、6
4となる。即ち、能動素子形成領域61の基板60はト
ランジスタのコレクタ電極用の外部接続用電極62、一
の外部接続電極領域64Aの基板60はトランジスタの
ベース電極用の外部接続用電極64、及び他の外部接続
電極領域63Aの基板60はトランジスタのエミッタ電
極用の外部接続用電極63となり、同一の半導体基板6
0を用い、且つ、同一平面上にトランジスタの各電極の
外部接続用電極62、63、64が形成されることにな
る。The active element formation region 61 and the external connection electrode regions 63A and 64A formed on the same substrate 60 are separated by slit holes 80 formed from the back side of the substrate 60.
Each of them is electrically isolated, and the individual regions 61, 63A,
64A is an external connection electrode 62, 63, 6 of the transistor
It becomes 4. That is, the substrate 60 of the active element formation region 61 is an external connection electrode 62 for the collector electrode of the transistor, the substrate 60 of one external connection electrode region 64A is the external connection electrode 64 for the base electrode of the transistor, and another external electrode. The substrate 60 in the connection electrode region 63A becomes the external connection electrode 63 for the emitter electrode of the transistor, and
0, and the external connection electrodes 62, 63, 64 of the respective electrodes of the transistor are formed on the same plane.
【0035】各外部接続用電極62、63、64を電気
的に分離するスリット孔80は、上記のように、半導体
基板60の裏面側から樹脂層78まで達するように形成
され、例えば、イオンビーム、レーザ等を照射する光学
的方法、ドライエッチング、ウエットエッチングによる
化学的方法、或いはダイシング装置によるダイシングブ
レードを用いた機械的方法等により形成される。上記の
いずれの方法によってもスリット孔80を形成すること
はできる。The slit holes 80 for electrically separating the external connection electrodes 62, 63, 64 are formed so as to reach the resin layer 78 from the back side of the semiconductor substrate 60 as described above. , An optical method of irradiating a laser or the like, a chemical method by dry etching or wet etching, or a mechanical method using a dicing blade by a dicing device. The slit hole 80 can be formed by any of the above methods.
【0036】ここで重要なことは、スリット孔80の深
さが浅くなると各外部接続用電極62、63、64の電
気分離が十分に行なわれず短絡不良となる不具合が生じ
るため、各外部接続用電極62、63、64が完全に電
気的に分離するように、スリット孔80の先端部(底
部)は樹脂層78内に約2μ〜6μ程度入るように形成
される。スリット孔80によって各外部接続用電極6
2、63、64は完全に分離区画されるが、樹脂層78
によって同一平面に支持固定される。また、各外部接続
用電極62、63、64となる基板60表面には、半田
メッキ等のメッキ層が形成され、配線基板上に形成され
た導電パターンとの半田接続を良好にする。What is important here is that if the depth of the slit hole 80 becomes shallow, the electrodes 62, 63 and 64 for external connection are not sufficiently electrically separated, resulting in a short-circuit failure. The tip (bottom) of the slit hole 80 is formed so as to enter the resin layer 78 by about 2 to 6 μ so that the electrodes 62, 63, and 64 are completely electrically separated. Each of the external connection electrodes 6 is formed by the slit holes 80.
2, 63 and 64 are completely separated from each other,
Are supported and fixed on the same plane. In addition, a plating layer such as solder plating is formed on the surface of the substrate 60 that becomes the external connection electrodes 62, 63, and 64, thereby improving the solder connection with the conductive pattern formed on the wiring board.
【0037】半導体基板60にスリット孔80を設け
て、トランジスタの各外部接続用電極62、63、64
を電気的に分離した半導体装置は、セラミックス基板、
ガラスエポキシ基板、フェノール基板、絶縁処理を施し
た金属基板等の配線基板上に形成された導電パターンの
パッド上に固着実装される。このパッド上には半田クリ
ームが予め印刷形成された半田層が形成されており、半
田を溶融させて本発明の半導体装置を搭載すれば配線基
板のパッド上に半導体装置を固着実装することができ
る。この固着実装工程は、図示されないが、実装基板上
に実装されるチップコンデンサ、チップ抵抗等の半田実
装される他の回路素子の実装工程と同一の工程ででき
る。The semiconductor substrate 60 is provided with a slit hole 80, and the external connection electrodes 62, 63, 64 of the transistor are provided.
Semiconductor device, which is electrically separated from a ceramic substrate,
It is fixedly mounted on a pad of a conductive pattern formed on a wiring board such as a glass epoxy board, a phenol board, and an insulated metal board. A solder layer on which solder cream is pre-printed is formed on this pad. If the semiconductor device of the present invention is mounted by melting the solder, the semiconductor device can be fixedly mounted on the pad of the wiring board. . Although not shown, this fixed mounting process can be performed in the same process as the mounting process of other circuit elements to be solder-mounted such as chip capacitors and chip resistors mounted on a mounting board.
【0038】また、本発明の半導体装置を配線基板上に
実装した時、各外部接続用電極62、63、64はスリ
ット孔80の間隔分だけ離間されているために実装基板
と固着する半田は隣接配置された外部接続用電極62、
63、64を短絡させることはない。ところで、図2に
示すように、本実施形態の半導体装置で、例えば、従来
例で説明した半導体装置とほぼ同じ機能をもつ能動素子
能動素子形成領域61を0.5mm×0.5mmサイズと
し、ベース、エミッタ電極となる接続電極領域63A,
64Aを0.3mm×0.2mmサイズとし、スリット孔8
0の幅を0.1mmとする半導体装置では有効面積率は次
のようになる。即ち、素子面積が0.25mmであり、実
装面積となる半導体装置の面積が1.28mmとなること
から、有効面積率は約19.53%となる。Further, when the semiconductor device of the present invention is mounted on a wiring board, since the external connection electrodes 62, 63, and 64 are separated by the distance of the slit hole 80, the solder fixed to the mounting board is small. External connection electrodes 62 arranged adjacent to each other,
There is no short circuit between 63 and 64. By the way, as shown in FIG. 2, in the semiconductor device of the present embodiment, for example, the active element active element formation region 61 having almost the same function as the semiconductor device described in the conventional example is set to a size of 0.5 mm × 0.5 mm. Connection electrode regions 63A serving as base and emitter electrodes,
64A is 0.3mm x 0.2mm size, and slit hole 8
In a semiconductor device in which the width of 0 is 0.1 mm, the effective area ratio is as follows. That is, since the element area is 0.25 mm and the area of the semiconductor device which is the mounting area is 1.28 mm, the effective area ratio is about 19.53%.
【0039】従来例で説明した0.40mm×0.40mm
のチップサイズを有する半導体装置の有効面積率は上記
したように6.25%であることから、本発明の半導体
装置では有効面積率で約3.12倍大きくなり、実装基
板上に実装する実装面積のデットスペースを小さくする
ことができ、実装基板の小型化に寄与することができ
る。0.40 mm × 0.40 mm explained in the conventional example
Since the effective area ratio of the semiconductor device having the chip size of 6.25% is 6.25% as described above, the effective area ratio of the semiconductor device of the present invention is about 3.12 times larger, and the semiconductor device of the present invention is mounted on a mounting substrate. The dead space of the area can be reduced, which can contribute to downsizing of the mounting substrate.
【0040】本実施形態では、実装基板との接続容易性
を考慮し、外部接続用電極62、63、64がトライア
ングルとなるように配置したが、外部接続電極62、6
3、64を直線上に配置すれば、半導体基板60上の不
使用領域を無くすことができ、有効面積率をさらに向上
させることが可能である。上述したように、本発明によ
れば、半導体基板60に半導体基板60をコレクタ電極
用の外部接続用電極62としたトランジスタを形成した
能動素子形成領域61と電気的に分離した半導体基板6
0の一部分をトランジスタのベース電極75、エミッタ
電極76用の外部接続用電極63、64とし用いること
により、従来の半導体装置のように、外部電極と接続す
る金属製のリード端子、保護用の封止モールドが不必要
となり、半導体装置の外観寸法を著しく小型化にするこ
とができ、有効面積率を大きくすることができる。In this embodiment, the external connection electrodes 62, 63, and 64 are arranged so as to form a triangle in consideration of the ease of connection with the mounting substrate.
By arranging 3, 64 on a straight line, an unused area on the semiconductor substrate 60 can be eliminated, and the effective area ratio can be further improved. As described above, according to the present invention, the semiconductor substrate 6 electrically separated from the active element forming region 61 in which the transistor is formed on the semiconductor substrate 60 using the semiconductor substrate 60 as the external connection electrode 62 for the collector electrode.
By using a part of 0 as the external connection electrodes 63 and 64 for the base electrode 75 and the emitter electrode 76 of the transistor, a metal lead terminal connected to the external electrode and a protective seal are provided as in a conventional semiconductor device. The need for a stop mold is eliminated, the external dimensions of the semiconductor device can be significantly reduced, and the effective area ratio can be increased.
【0041】本実施形態では、能動素子形成領域61に
トランジスタを形成したが、縦型或いは比較的発熱量の
少ない横型のデバイスであればこれに限らず、例えば、
パワーMOSFET、IGBT、HBT等のデバイスに
本発明を応用することができることは説明するまでもな
い。ところで、上記の実施形態では、樹脂層78に光熱
硬化性樹脂を用いて基板60の各電極と配線基板65の
配線パターンとの電気的導通を行ったが、本発明では、
この両者の電気的導通はいかなる手段にも応用すること
ができ、例えば、図3に示す用に異方導電性樹脂を樹脂
層78として用いても基板60の各電極と配線基板65
の配線パターンとの接続が容易に行うことができる。In the present embodiment, the transistor is formed in the active element formation region 61. However, the present invention is not limited to this, as long as the device is a vertical device or a horizontal device that generates a relatively small amount of heat.
It goes without saying that the present invention can be applied to devices such as power MOSFETs, IGBTs, and HBTs. By the way, in the above embodiment, the electrical conduction between each electrode of the substrate 60 and the wiring pattern of the wiring substrate 65 is performed by using a photo-thermosetting resin for the resin layer 78.
The electrical conduction between the two can be applied to any means. For example, even if an anisotropic conductive resin is used as the resin layer 78 as shown in FIG.
Can easily be connected to the wiring pattern.
【0042】異方導電性樹脂は、粒径の導電物81を樹
脂ペースト中に混入したものと、粒径の導電物を樹脂シ
ート中に散布したものとがあり、どちらのタイプの樹脂
を用いることも可能である。異方導電性樹脂は両基板6
0、65上に形成された配線パターン等が重畳する領域
が粒径の導電物81を介して電気的接続が行われるもで
ある。異方導電性樹脂を用いる場合には、基板60上の
各電極75、76、77及び配線基板65上の配線パタ
ーン67上のそれぞれにバンプ電極68を形成すること
が好ましい。The anisotropic conductive resin includes a resin in which a conductive material 81 having a particle size is mixed in a resin paste and a resin in which a conductive material having a particle size is dispersed in a resin sheet. Either type of resin is used. It is also possible. Anisotropic conductive resin is used for both substrates 6
A region where a wiring pattern or the like formed on 0 and 65 overlaps is electrically connected via a conductor 81 having a particle size. When an anisotropic conductive resin is used, it is preferable to form the bump electrodes 68 on each of the electrodes 75, 76, 77 on the substrate 60 and on the wiring pattern 67 on the wiring substrate 65.
【0043】例えば、異方導電性シートを基板60上に
配置し、基板60上のバンプ電極68と配線基板65上
のバンプ電極68とが一致するように位置あわせを行い
両基板60、65に所定の圧力を加えながら約120℃
程度の加熱処理を行い導電性シートを溶かして樹脂層7
8とし、粒径の導電物81により各電極75、76、7
7と配線パターン67との導通が行われる。各電極7
5、76、77、及び配線パターン67上にバンプ電極
68を形成することで、配線パターン67と重畳するガ
ードリング用電極とは異方導電性樹脂の導電物が接触さ
れないため導通せず、確実に各電極75、76、77の
バンプ電極68と配線基板65上のバンプ電極68とが
接触し電気的導通が行われる。For example, an anisotropic conductive sheet is placed on the substrate 60, and the bump electrodes 68 on the substrate 60 are aligned with the bump electrodes 68 on the wiring board 65 so as to be aligned. About 120 ° C while applying the specified pressure
The heat treatment is performed to a degree to melt the conductive sheet and the resin layer 7
8, each of the electrodes 75, 76, 7
7 and the wiring pattern 67 are conducted. Each electrode 7
5, 76, 77 and the formation of the bump electrode 68 on the wiring pattern 67 ensure that the guard ring electrode overlapping the wiring pattern 67 does not conduct because the conductive material of the anisotropic conductive resin is not in contact with the guard ring electrode. Then, the bump electrodes 68 of the electrodes 75, 76, and 77 come into contact with the bump electrodes 68 on the wiring board 65, and electrical conduction is performed.
【0044】他の電気的導通の方法として、図4に示す
ように、両基板60、65上に形成したバンプ電極8
3、83を一致するように両基板60、65の位置合わ
せを行い、溶融しバンプ電極83、83の接続を行い、
基板60上の各電極75、76、77と配線基板65上
の配線パターン67との電気的導通が行われる。その
後、両基板60、65に圧力を加えながら、両基板6
0、65のすき間に液状の熱硬化性樹脂からなる含浸材
を流し込み熱処理を行い樹脂層78形成し、スリット孔
80が形成される。As another method of electrical conduction, as shown in FIG. 4, bump electrodes 8 formed on both substrates 60 and 65 are formed.
The positions of the two substrates 60 and 65 are adjusted so that the positions of the substrates 3 and 83 coincide with each other, and the substrates are melted and connected to the bump electrodes 83 and 83.
Each of the electrodes 75, 76, 77 on the substrate 60 is electrically connected to the wiring pattern 67 on the wiring substrate 65. Then, while applying pressure to both substrates 60 and 65, both substrates 6
A resin layer 78 is formed by pouring an impregnating material made of a liquid thermosetting resin into the gaps 0 and 65 to form a resin layer 78, and a slit hole 80 is formed.
【0045】本発明では、各電極75、76、77と配
線パターン67とが接続されるものであれば、いかなる
構造、いかなる材料を用いて行うことができる。In the present invention, any structure and any material can be used as long as the electrodes 75, 76 and 77 and the wiring pattern 67 are connected.
【0046】[0046]
【発明の効果】以上に詳述したように、本発明の半導体
装置によれば、半導体基板に半導体基板を一の外部接続
用電極とした能動素子を形成した能動素子形成領域と、
能動素子の他の電極と接続される他の外部接続電極領域
とを形成し、能動素子形成領域と外部接続電極領域とを
基板に設けたスリット孔で電気的に分離し、配線基板上
に形成された金属配線で能動素子の他の電極と他の外部
接続電極領域とを電気的に接続することにより、従来の
半導体装置のように、外部電極と接続する金属製のリー
ド端子、保護用の封止モールドが不必要となり、半導体
装置の外観寸法を著しく小型化にすることができ、実装
基板上に実装したときの不必要なデットスペースを小さ
くすることができ、実装基板の小型化に大きく寄与する
ことができる。As described in detail above, according to the semiconductor device of the present invention, an active element forming region in which an active element is formed on a semiconductor substrate using the semiconductor substrate as one external connection electrode;
Forming another external connection electrode area connected to another electrode of the active element, electrically separating the active element formation area and the external connection electrode area by a slit hole provided in the substrate, and forming on the wiring substrate By electrically connecting the other electrodes of the active element and other external connection electrode regions with the provided metal wiring, a metal lead terminal connected to the external electrode and a protective The need for a sealing mold is eliminated, the external dimensions of the semiconductor device can be significantly reduced, and unnecessary dead space when mounted on a mounting substrate can be reduced. Can contribute.
【0047】また、本発明の半導体装置では、上記した
ように、外部接続用の金属リード端子、及び樹脂封止用
モールドが不要であるために、半導体装置の製造コスト
を著しく低減化することができる。Further, in the semiconductor device of the present invention, as described above, the metal lead terminal for external connection and the mold for resin sealing are unnecessary, so that the manufacturing cost of the semiconductor device can be significantly reduced. it can.
【図面の簡単な説明】[Brief description of the drawings]
【図1】本発明の半導体装置を示す断面図。FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.
【図2】本発明の半導体装置の裏面を示す図。FIG. 2 is a diagram showing a back surface of the semiconductor device of the present invention.
【図3】本発明の半導体装置を示す断面図。FIG. 3 is a cross-sectional view illustrating a semiconductor device of the present invention.
【図4】本発明の半導体装置を示す断面図。FIG. 4 is a cross-sectional view illustrating a semiconductor device of the present invention.
【図5】従来の半導体装置を示す断面図。FIG. 5 is a cross-sectional view illustrating a conventional semiconductor device.
【図6】一般的なトランジスタの断面図。FIG. 6 is a cross-sectional view of a general transistor.
【図7】従来の半導体装置を配線基板上に実装した断面
図。FIG. 7 is a cross-sectional view in which a conventional semiconductor device is mounted on a wiring board.
【図8】従来の半導体装置の平面図。FIG. 8 is a plan view of a conventional semiconductor device.
【図9】従来の半導体装置の平面図。FIG. 9 is a plan view of a conventional semiconductor device.
【図10】従来の半導体装置を示す図。FIG. 10 illustrates a conventional semiconductor device.
【図11】従来の半導体装置を示す図。FIG. 11 illustrates a conventional semiconductor device.
Claims (2)
子が形成され、前記能動素子形成領域の前記基板の裏面
を前記能動素子の一の電極とした一の外部接続用電極領
域と、前記能動素子の他の電極と電気的に接続され前記
基板の一部分よりなる他の外部接続用電極領域とを有し
た半導体基板と、前記他の電極と前記他の外部接続用電
極とを電気的に接続する金属配線が形成された配線基板
とを有し、前記半導体基板と前記配線基板とが一体化さ
れ、前記半導体基板上に形成された前記金属配線を介し
て前記能動素子の他の電極と接続される前記他の外部接
続用電極とが接続され、前記半導体基板に設けられたス
リットにより、前記一の外部接続用電極領域と前記他の
外部接続用電極領域とが電気的に分離されていることを
特徴とする半導体装置。An active element is formed in a predetermined active element forming region of a substrate, and one external connection electrode region in which the back surface of the substrate in the active element forming region is used as one electrode of the active element. A semiconductor substrate electrically connected to another electrode of the active element and having another external connection electrode region formed of a part of the substrate; and electrically connecting the other electrode and the other external connection electrode. A wiring board on which a metal wiring to be connected is formed, wherein the semiconductor substrate and the wiring board are integrated, and another electrode of the active element is formed through the metal wiring formed on the semiconductor substrate. The other external connection electrode to be connected is connected, and the one external connection electrode region and the other external connection electrode region are electrically separated by a slit provided in the semiconductor substrate. Semiconductor device characterized by Place.
エポキシ基板、セラミックス基板、或いは金属薄膜基板
を用いることを特徴とする請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the wiring substrate is a silicon substrate, a glass epoxy substrate, a ceramic substrate, or a metal thin film substrate.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17028296A JP3609540B2 (en) | 1996-06-28 | 1996-06-28 | Semiconductor device |
US08/881,356 US6075279A (en) | 1996-06-26 | 1997-06-24 | Semiconductor device |
KR1019970027149A KR100254661B1 (en) | 1996-06-26 | 1997-06-25 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17028296A JP3609540B2 (en) | 1996-06-28 | 1996-06-28 | Semiconductor device |
Related Child Applications (1)
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JP2004203081A Division JP2004297091A (en) | 2004-07-09 | 2004-07-09 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
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JPH1022330A true JPH1022330A (en) | 1998-01-23 |
JP3609540B2 JP3609540B2 (en) | 2005-01-12 |
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Family Applications (1)
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JP17028296A Expired - Fee Related JP3609540B2 (en) | 1996-06-26 | 1996-06-28 | Semiconductor device |
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JP (1) | JP3609540B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7880763B2 (en) | 2004-12-14 | 2011-02-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method therefor |
-
1996
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7880763B2 (en) | 2004-12-14 | 2011-02-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method therefor |
US8178972B2 (en) | 2004-12-14 | 2012-05-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method therefor |
Also Published As
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JP3609540B2 (en) | 2005-01-12 |
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