JPH1032284A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a semiconductor device in effective area rate by a method wherein a first and a second active device are electrically connected together, a first semiconductor substrate is divided into sub-boards which are electrically isolated from each other, and the electrically isolated sub-boards are made to serve as the outer connecting electrodes of the first and the second active device. SOLUTION: A semiconductor device has such an integral structure that a first semiconductor substrate 60 where a first active device is formed and a second semiconductor substrate 100 where a second active device is formed are formed into one piece. In this case, the first active device and the second active device are electrically connected together, and the first semiconductor substrate is divided into sub-boards which are electrically isolated from each other, and the electrically isolated sub-boards are made to serve as the outer connecting electrodes 62, 63, 64... of the first and the second active devices.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having an improved effective mounting area ratio, which is expressed as a ratio of a chip area of a semiconductor device to a mounting area for mounting the semiconductor device on a mounting substrate such as a printed circuit board, and having a higher function.

[0002]

2. Description of the Related Art Generally, a semiconductor device in which a transistor element is formed on a silicon substrate mainly has a structure as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.

As shown in FIG. 13, a transistor element formed on a silicon substrate 11 is formed, for example, by diffusing a P-type impurity such as boron into an N-type epitaxial layer 12 serving as a collector region in an N-type silicon substrate 11. Base area 1
3 is formed, and an N-type impurity such as phosphorus is diffused in the base region 13 to form an emitter region 14. Base region 13 and emitter region 1 are formed on the surface of silicon substrate 11.
An insulating film 15 having an opening exposing a part of the base region 4 and the exposed base region 13 and the emitter region 1 is formed.
4, a metal such as aluminum is deposited on the base electrode 1
6. An emitter electrode 17 is formed. In the transistor having such a configuration, the silicon substrate becomes the collector electrode 18.

As described above, the silicon substrate 1 on which the transistor elements are formed is fixedly mounted on an island 2 such as a copper-based heat sink through a brazing material 5 such as solder, as shown in FIG. The base electrode and the emitter electrode of the transistor element are electrically connected to the lead terminals 3 arranged around the substrate 1 by wires by wire bonding. The lead terminal connected to the collector electrode is formed integrally with the island, and after being electrically connected by mounting a silicon substrate on the island, transfer molding is performed using a thermosetting resin 4 such as an epoxy resin. A semiconductor device having a three-terminal structure is provided by completely covering and protecting a silicon substrate and part of a lead terminal.

[0005]

A resin-molded semiconductor device is usually mounted on a wiring board such as a glass epoxy board and electrically connected to other semiconductor devices and circuit elements mounted on the mounting board. It is handled as one component for performing a predetermined circuit operation. FIG. 14 is a cross-sectional view of a semiconductor device mounted on a mounting substrate, wherein 20 is a semiconductor device, 21 and 23 are lead terminals for base or emitter electrodes, 22 is a lead terminal for collector, and 30 is a mounting substrate. It is.

The mounting area where the semiconductor device 20 is mounted on the mounting board 30 is represented by a region surrounded by the lead terminals 21, 22, and 23 and conductive pads connected to the lead terminals. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, and most of the mounting area is taken by the mold resin and the lead terminals as compared with the area of the semiconductor chip having an actual function.

Here, considering the ratio between the area of the semiconductor chip having the actual function and the mounting area as the effective area ratio,
It has been confirmed that a resin-molded semiconductor device has an extremely low effective area ratio. The low effective area ratio means that
When the semiconductor device 20 is used for connection with another circuit element on the wiring board 30, most of the mounting area becomes a dead space which is not directly related to a semiconductor chip having a function. If the effective area ratio is small, the dead space on the mounting substrate 30 increases as described above, which hinders the high-density and miniaturization of the mounting substrate 30.

In particular, this problem appears remarkably in a semiconductor device having a small package size. For example, as shown in FIG. 15, the minimum size of a semiconductor chip mounted on an EIAJ standard SC75A outer shape is 0.40 mm × 0.40 mm. When this semiconductor chip is connected to metal lead terminals by wires and resin-molded, the overall size of the semiconductor device becomes 1.6 mm × 1.6 mm. The chip area of this semiconductor device is 0.16 mm, and the mounting area for mounting the semiconductor device is considered to be substantially the same as the area of the semiconductor device.
Since it is 56 mm, the effective area ratio of this semiconductor device is about 6.25%, and most of the mounting area is a dead space that is not directly related to the area of the semiconductor chip having functions.

The problem regarding the effective area ratio is particularly prominent in a semiconductor device having an extremely small package size as described above. However, the semiconductor chip is wire-connected with metal lead terminals and resin-molded. A problem also occurs in a semiconductor device. In recent years, wiring boards used in electronic devices such as personal computers, portable information processing apparatuses such as electronic notebooks, 8 mm video cameras, mobile phones, cameras, liquid crystal televisions, etc. There is also a tendency for high-density miniaturization of mounting boards used.

However, in the above-mentioned prior art resin-encapsulated semiconductor device, as described above, the mounting area for mounting the semiconductor device has a large dead space. Has been one of the factors that hindered the miniaturization of the system. Incidentally, Japanese Patent Application Laid-Open No. 3-248551 is a prior art for improving the effective area ratio. This prior art will be briefly described with reference to FIG. In this prior art, lead terminals 41, 42, and 43 connected to a base, an emitter, and a collector electrode of a semiconductor chip 40 are formed in order to minimize a mounting area when a resin mold type semiconductor device is mounted on a mounting substrate or the like. It is described that the lead terminals 41, 42, and 43 are formed so as not to be led out from the side surface of the resin mold 44 and to be flush with the side surface of the resin mold 44.

According to this structure, the lead terminals 41, 4
Although the mounting area can be reduced by the extent that the leading end portions of 2, 43 are not led out and the effective area ratio can be slightly improved, the size of the dead space is not significantly improved. In order to improve the effective area ratio, it is a condition that the semiconductor chip area and the mounting area of the semiconductor device are made substantially the same. In a resin-molded semiconductor device, as in this prior art, the tip of the lead terminal is not provided. Even if the portion is not led out, it is difficult to improve the effective area ratio due to the presence of the mold resin.

In addition, in the above-mentioned semiconductor device, since a lead terminal for connecting to the semiconductor chip and a molding resin are indispensable, a step of connecting a wire between the semiconductor chip and the lead terminal and a step of injection molding of the molding resin are required. However, there is a problem that the material cost and the manufacturing process are complicated, and the manufacturing cost cannot be reduced. In order to maximize the effective area ratio, as described above, by mounting the semiconductor chip directly on the mounting board, the semiconductor chip area and the mounting area are almost the same, and the effective area ratio is maximized.

One prior art for mounting a semiconductor chip on a substrate such as a mounting substrate is disclosed in, for example, JP-A-6-338.
As shown in JP-A-504-504, there is known a technique of performing face-down bonding of a flip chip having a plurality of bump electrodes 46 formed on a semiconductor chip 45 on a mounting substrate 47 (see FIG. 17). This prior art usually uses MOSFE
T (gate) electrode, source (emitter) electrode, drain (collector) electrode are formed on the same main surface of a silicon substrate such as T, and current or voltage paths are formed in the horizontal direction. Mainly used for semiconductor devices.

However, in a vertical semiconductor device such as a transistor device in which a silicon substrate becomes one of the electrodes, each electrode is formed on a different surface, and a current path flows in a vertical direction, the above-described flip chip technology is used. It is difficult to do. As another prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-7-38334, a semiconductor chip 53 is mounted on a conductive pattern 52 formed on a mounting substrate 51 by die. Conductive pattern 5 bonded and placed around semiconductor chip 53
A technique for connecting the electrodes of the semiconductor chip 53 and the semiconductor chip 53 with wires 54 is known (see FIG. 18). In this prior art, the above-described silicon substrate can be used for a semiconductor chip such as a transistor having a vertical structure in which one electrode forms one electrode.

A wire 54 for connecting the semiconductor chip 53 and the conductive pattern 52 disposed around the semiconductor chip 53 is usually a gold wire, and therefore, the peel strength (tensile force) of a bonding portion bonded to the gold wire by bonding. Is preferably performed in a heating atmosphere at about 200 ° C. to 300 ° C. However, when a semiconductor chip is die-bonded on an insulating resin-based mounting substrate, the wiring substrate may be distorted when heated to the above-described temperature, and a chip capacitor, a chip resistor, etc. mounted on the mounting substrate may be distorted. Since the solder for fixing other circuit elements is melted, the wire bonding connection is performed at a heating temperature of about 100 ° C. to about 150 ° C.,
There is a problem that the peel strength of the bonding portion is reduced.

In this prior art, a die-bonded semiconductor chip is usually covered and protected with a thermosetting resin such as an epoxy resin. Therefore, a decrease in peel strength is caused by shrinkage of the epoxy resin during thermosetting or the like. There is a problem that is peeled off. Further, conventionally, when a transistor is connected to an active element such as a bipolar IC or a MOSIC on a mounting board, the transistor and the bipolar IC which have been resin-molded must be individually mounted. Lower the mounting area ratio.

The present invention has been made in view of the above circumstances, and the present invention does not require a lead terminal connected to a semiconductor chip and a molding resin, and has a semiconductor chip area and mounting on a mounting substrate. Provided is a semiconductor device which has an effective area ratio, which is a ratio with respect to the mounting area to be improved, as much as possible, minimizes the dead space of the mounting area, and has high functionality.

[0018]

The present invention has the following features to attain the object mentioned above. That is, first, the semiconductor device of the present invention has a first device in which a first active element is formed.
In the semiconductor device in which the semiconductor substrate of the above and the second semiconductor substrate on which the second active element is formed are integrated, the first active element and the second active element are electrically connected, Further, the first and second active elements are characterized in that the external connection electrodes use the first semiconductor substrate which is electrically divided and divided into a plurality of parts.

Secondly, in the semiconductor device of the present invention, a first active element is formed in a predetermined active element forming region of a substrate, and the substrate in the active element forming region is at least one electrode of the active element. A first semiconductor substrate having one external connection electrode region and at least a plurality of other external connection electrode regions electrically connected to at least another electrode of the active element and formed of part of the substrate; A second semiconductor substrate on which a wiring pattern for electrically connecting the other electrode and the other external connection electrode and a second active element are formed; the first semiconductor substrate and the second semiconductor; A substrate, and the other electrode and the other external connection electrode region of the first active element via the wiring pattern formed on the second semiconductor substrate; The electrode of the element and the other outside The connection electrode region is connected to the first semiconductor substrate, and the slit provided in the first semiconductor substrate electrically separates the one external connection electrode region from the other external connection electrode region. Features.

Here, the first semiconductor substrate and the second semiconductor substrate
The semiconductor device is characterized in that the semiconductor substrate is disposed via an insulating adhesive resin layer. Further, the first active element is a transistor or a power MOSFET. Further, the second active element is a bipolar IC or a MOSIC and a composite IC thereof.

As described above, in the semiconductor device in which the first semiconductor substrate on which the first active element is formed and the second semiconductor substrate on which the second active element is formed are integrated, The first active element is electrically connected to the second active element, and the external connection electrodes of the first and second active elements use the first semiconductor substrate which is electrically separated and divided into a plurality. This eliminates the need for a metal lead terminal connected to an external electrode and a protective sealing mold as in a conventional semiconductor device, and can significantly reduce the external dimensions of the semiconductor device. Further, a highly functional semiconductor device in which a first active element such as a transistor and a second active element such as a bipolar IC are combined can be provided.

Further, as described above, since the metal lead terminals for external connection and the mold for resin sealing are not required, the manufacturing cost of the semiconductor device can be significantly reduced.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the semiconductor device according to the present invention will be described. FIG. 1 shows a semiconductor device according to the present invention.
As shown in FIG. 1, a first semiconductor substrate 60, an active element formation region 61 where active elements are formed, and an active element formation region 6
One electrode of the first active element formed on the first substrate, one external connection electrode 62 for external connection, and a part of the first substrate 60 electrically separated from the active element formation region 61. A plurality of other external connection electrodes 63, 64, at least as external electrodes of other electrodes of the active element. . . A second semiconductor substrate 100 disposed opposite to the first substrate 60;
And a second active element formed on the substrate 100.

As the first semiconductor substrate 60, for example, an N + type single crystal silicon substrate is used.
An N-type epitaxial layer 66 is formed thereon by an epitaxial growth technique. A predetermined region of the first semiconductor substrate 60 includes a plurality of external connection electrodes 63 connected to an active element forming region 61 in which a first active element such as a power MOS or a transistor is formed, and at least an electrode of the first active element. 6
4. . . The external connection electrode regions 63A, 64A. . .
Are provided.

In the active element forming area 61, the first
Are formed. Here, a transistor in which the N− type epitaxial layer is the collector region 66A is formed. A photoresist is formed on the active element formation region 61, and a P-type impurity such as boron (B) is selectively thermally diffused into a region exposed by the photoresist to form an island-like base region 71 having a predetermined depth. Is formed.

After forming the base region 71, a photoresist is formed again on the active element forming region 61, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively formed in the base region 71 exposed by the photoresist. Is diffused to form an emitter region 72 of the transistor. When forming the emitter region 72, a ring-shaped guard ring N + type diffusion region 73 surrounding the base region 71 may be formed in some cases. Further, the N + type emitter region 7
2 is formed, the N + -type diffusion is performed by the electrode regions 63A, 64A. . . This is also done on the electrode regions 63A, 64A. . . Then, a high concentration diffusion layer 81 is formed.

An insulating film 7 such as a silicon oxide film or a silicon nitride film having a base contact hole exposing the surface of the base region 71 and an emitter contact hole exposing the surface of the emitter region 72 is formed on the surface of the first semiconductor substrate 60.
4 are formed. When the guard ring diffusion region 73 is formed, a guard ring contact hole exposing the surface of the diffusion region 73 is formed. This insulating film 74
Are electrode regions 63A and 64 serving as external connection electrodes.
A. . . Electrode regions 63A, 64
A. . . The contact hole for external connection which exposes the surface of is formed.

The base region 71, the emitter region 72, the electrode regions 63A and 64A, and the guard ring diffusion region 73 exposed by the base contact hole, the emitter contact hole, the external connection contact hole, and the guard ring contact hole are selectively provided. A base electrode 75, an emitter electrode 76, and a connection electrode 77 are formed by depositing a metal material such as aluminum.

When aluminum is used for the base electrode 75, the emitter electrode 76, and the connection electrode 77, a PSG film, a passivation film 74A made of an insulator such as SiN or SiNx is formed on the substrate 60, and the base electrode 75 is formed. 7
5, the passivation film 74A on the emitter electrode 76 and the connection electrode 77 is selectively removed, and the electrodes 75, 76,
The surface of 77 is exposed. Further, it is necessary to selectively plate chromium, copper, or the like in the exposed region to form a plating layer 79, thereby preventing the electrodes 75, 76, 77 from being damaged by corrosion.

An active element forming region 61 in which a transistor is formed and a plurality of external connection electrode regions 63A, 64A. . .
The second semiconductor substrate 100 is opposed to and fixed to the surface of the first semiconductor substrate 60 having a silicon-based, epoxy-based, or polyimide-based or photocurable insulating adhesive resin layer 78. On the second substrate 100, a second active element and a wiring pattern are formed, and the wiring pattern forms a base electrode 7 of the transistor.
5 or a predetermined external connection electrode region 63A, 64A. . . And electrical connection is made respectively.

As the second semiconductor substrate 100, for example, a single-crystal P-type semiconductor substrate is used, and a second active element such as a bipolar IC or a MOSIC is formed on the substrate 100. For example, as shown in FIG. 1, a photomask of a predetermined shape is formed on a P-type semiconductor substrate, and an N-type high-concentration impurity such as antimony is diffused to form an island-shaped N + -type buried collector region 101. You. After removing the photomask,
On the second substrate 100, N-
A type epitaxial layer 102 is formed.

A mask for exposing the isolation diffusion region is formed on the epitaxial layer 102, and a P + type impurity such as boron is diffused into the isolation diffusion region to form an isolation diffusion region 103.
The N-type region serving as the active region of the transistor is surrounded by the P-type impurity by the isolation diffusion region 103.

A photoresist is formed on the epitaxial layer 102, and a P-type impurity such as boron (B) is selectively thermally diffused into a region exposed by the photoresist to form an island-like base region 104 having a predetermined depth. Is formed. After the formation of the base region 104, a photoresist is formed again on the epitaxial layer 102, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively formed in the base region 104 and the collector region exposed by the photoresist. By thermal diffusion, an emitter region 105 and a collector contact diffusion region 106 of the transistor are formed.

On the surface of the second semiconductor substrate 100, silicon having a base contact hole exposing the surface of the base region 104, an emitter contact hole exposing the surface of the emitter region 105, and a collector contact hole exposing the surface of the collector contact diffusion region is provided. An insulating film 107 such as an oxide film or a silicon nitride film is formed. Base region 104, emitter region 10 exposed by base contact hole, emitter contact hole, collector contact hole
6. In the collector contact region 107, a base electrode 107 selectively deposited with a metal material such as aluminum,
The emitter electrode 108, the collector electrode 109, and the wiring A extending from each of the electrodes as necessary are arranged and formed up to predetermined positions. In the present embodiment, the collector electrode wiring 1
The reference numeral 09 </ b> A extends to a predetermined position in order to connect to the external connection electrode of the first substrate 60.

The base electrode 107, the emitter electrode 108,
When aluminum is used for the collector electrode 109, a PSG film, SiN, SiNx is formed on the second substrate 100.
Is formed on the base electrode 107, the emitter electrode 108, the collector electrode 109 or / and, if necessary, the respective electrodes 107.
The passivation film 110 on a predetermined position of the wiring A extending from 108 and 109 is selectively removed, and each electrode 10
7, 108, 109 or / and the surface of the wiring A is exposed. Further, chromium, copper, or the like is selectively plated in the exposed region to form a plating layer 111, thereby preventing a problem due to corrosion of each electrode and the like.

Further, on the second substrate 100, the electrodes of the first active element formed in the active element forming region 61 of the first substrate 60 and the external connection electrodes formed from the first substrate 60 are formed. Redundant pattern wiring 11 for connecting to electrodes
2 are formed. The pattern wiring 112 is formed by using a general multilayer wiring technique, for example, by selectively depositing a metal on aluminum or the like, and forming a PSG film,
A passivation film 113 made of an insulator such as SiN or SiNx is formed, the passivation film on a predetermined position of the pattern wiring is selectively removed, and the surface of the wiring 112 is exposed. Further, as described above, chromium, copper, or the like is selectively plated in the exposed region to form a plating layer 114, thereby preventing a problem due to corrosion of the exposed pattern wiring 112.

On the plating layers 111 and 114 formed on the second substrate 100, a bump electrode 115 made of a metal such as gold having a height of about 3 to 25 μ is formed. The electrodes of the first active element formed on the substrate 60 and the connection electrodes 77 formed on the external connection electrode region are brought into contact with each other, and the first and second electrodes formed on both the substrates 60 and 100 are made. Electrical conduction of the active element will be achieved.

Although not evident from FIG. 1, a bipolar IC having a plurality of elements such as transistors and diodes and having a predetermined function is formed on the second substrate 100. Further, the bump electrodes 115 are formed on the second substrate 10.
Instead of being formed only on 0, it may be formed on the first substrate 60 side. As described above, the resin layer 78 for fixing and integrating the two semiconductor substrates 60 and 100 includes various materials. For example, a photocurable resin such as an acrylic resin that is cured by ultraviolet rays and a thermosetting resin such as an epoxy resin are used. It is assumed that a hybrid type photothermosetting resin mixed with a conductive resin is used. A photo-thermosetting resin is applied on the substrate 60, for example, and the base electrode 75, the emitter electrode 76, and the external connection electrode regions 63A, 64A. . . Connection electrode 7 formed on top
The substrates 60 and 100 are aligned and brought into close contact with each other so that 7 and the bump electrodes 115 formed on the second substrate 100 match.

Thereafter, a heat treatment at about 80 ° C. to 100 ° C. is performed to thermally cure the resin layer 78.
Is fixedly integrated. At this time, each of the electrodes 75, 76, and 77 and the bump electrode 115 are in contact with each other and are electrically connected, but are not in a sufficiently conductive state. Thereafter, by irradiating ultraviolet rays, curing of the photocurable resin in the resin layer 78 starts,
Both substrates 60, 10
0 are attracted to each other, the contacts between the electrodes 75, 76, 77 on the first substrate 60 and the bump electrodes 115 are sufficiently maintained, and electrical conduction is reliably performed. The resin layer 78 allows the electrodes 75, 76, 77 and the bump electrodes 115 to conduct well and simultaneously bonds the substrates 60, 100 together.

When the height of the bump electrode 115 formed on the second substrate 100 is low, the first substrate 6
It is preferable to form another bump electrode on each of the formed electrodes on zero. If the height of the bump electrode 115 formed on the second substrate 100 is too low, the distance between the two substrates 60 and 100, that is, the thickness of the resin layer 78 becomes thin, and when the slit hole 80 described later is formed, There is a possibility that the tip of the slit hole 80 reaches the surface of the second substrate 100 and cuts the wiring pattern 112 or the second active element.
It is necessary to sufficiently consider the distance between the two substrates 60 and 100.

The active element formation region 61 formed on the first substrate 60 and the external connection electrode regions 63A, 64A. . . Are electrically separated from each other by slit holes 80 formed from the back surface side of the first substrate 60, and the individual regions 61, 63A, 64A. . . Are the external connection electrodes 62, 63, 64. . . . Becomes For example, as shown in FIG. 2, in the case of a semiconductor device having an equivalent circuit including a transistor Q and a control circuit having four input terminals for controlling the transistor Q, the transistor Q is formed on the first substrate 60, The circuit is formed on the second substrate 100. At this time, the control circuit is configured by, for example, a bipolar IC. FIG. 3 shows the back surface of the first substrate 60 serving as an external connection electrode. The external connection electrodes of the semiconductor device of this equivalent circuit can be arranged, for example, as shown in FIG. The external connection electrode 62 for the VCC (collector terminal) of the transistor Q is arranged at the center of the upper stage, and the external connection electrode 63 for output is arranged at the lower left. The external connection electrodes 64, 65, 66 for three inputs of the control circuit and the external connection electrode 67 for grounding are arranged at the remaining positions. Here, 65A. . . 67A shows an electrode region before separation.

More specifically, the active element forming region 61
The first substrate 60 of the semiconductor device has the external connection electrode 62 for VCC of the semiconductor device, and the first substrate 60 of the external connection electrode region 63A has the input external connection electrode 63 and the external connection electrode region 64A. . . The substrate 60 has an external connection electrode 64. . . , And the external connection electrodes 62, 63, 64,... For each input / output of the semiconductor device are formed on the same plane using the same first semiconductor substrate 60. . . Is formed.

The external connection electrode region 64A of the semiconductor device,
63A. . . As described above, the high concentration diffusion layer 81
Are formed, and the external connection electrode 64. . . . . And the loss due to the wiring resistance connecting the electrodes is reduced. The high-concentration diffusion layer 81 has electrode regions 64A, 63A. . .
When the thickness of the epitaxial layer 66 is relatively small, the epitaxial layer 66 is formed in the diffusion step of forming the emitter region 72 as described above.

When the thickness of the epitaxial layer 60 is relatively large, before forming the epitaxial layer 60, the electrode regions 63A, 64A. . . If an N + type impurity is deposited thereon, then an epitaxial layer 60 is formed, and a thermal diffusion process is further performed to grow the high concentration diffusion region 81 from the first substrate 60 side. When forming the emitter region 72, the high concentration diffusion regions 81, 81
Contact the electrode regions 63A, 64A. . . The high concentration diffusion layer 81 can be formed therein.

Each external connection electrode 62, 63, 6
4. . . . As described above, the slit hole 80 that electrically separates the resin layer 7 from the back side of the first semiconductor substrate 60 is formed.
8, for example, an ion beam,
It is formed by an optical method of irradiating a laser or the like, a chemical method by dry etching or wet etching, or a mechanical method using a dicing blade by a dicing device. The slit hole 80 can be formed by any of the above methods.

It is important to note that when the depth of the slit hole 80 becomes shallower, the external connection electrodes 62, 63, 6
4. . . Of the external connection electrodes 62, 63, 6
4. . . . The tip (bottom) of the slit hole 80 is approximately 2 μm to 6 μm
It is formed so that it can enter. The external connection electrodes 62, 63, 64. . . Are completely separated from each other, but are supported and fixed on the same plane by the resin layer 78. In addition, each of the external connection electrodes 62, 63, 6
4. . . . A plating layer such as solder plating is formed on the surface of the first substrate 60 to improve the solder connection with the conductive pattern formed on the mounting substrate.

A thermosetting resin such as an epoxy resin is filled in the slit hole 80 to form an insulating resin layer 95. The resin layer 95 is formed of the separated external connection electrodes 62 and 6.
3, 64. . . Electrical separation of By filling the resin layer 95 into the slit holes 80, the external connection electrodes 62, 63, 64. . . The adhesive strength between them is improved, and adverse effects on external stress such as stress can be prevented. Since the width of the slit hole 80 is as small as several tens of μ, the inside of the slit hole 80 can be easily filled by using an impregnating thermosetting resin.

Each of the external connection electrodes 62, 63, 64. . . Is formed with a tapered portion 91. When the semiconductor device of the present invention is mounted on a mounting board, as shown in FIG.
2, 63, 64. . . And a pad (land) formed on the mounting board are formed in order to optimize the shape of the solder fillet at the solder joint and to improve the strength of the solder joint against external stress due to, for example, thermal contraction. is there.

The tapered portion 91 and the insulating resin layer 95 are formed as follows. As shown in FIG. 5, slit holes 80 for separately forming the external connection electrodes 62, 63, 64 are formed. After forming the slit holes 80, an impregnating thermosetting resin is applied on the surface of the substrate 60, and the insulating resin layer 95 of the impregnating material is filled in the slit holes 80. At this time, the applied impregnating material remains on the substrate surface to ensure that the slit hole 80 is filled with the impregnating material, and remains in a thin film state even after the heat treatment.

Next, as shown in FIG.
The surface of the first substrate 60 is polished and removed using a polishing device such as a back glider, and the surface of the first substrate 60 is removed.
Expose the surface. Thereafter, as shown in FIG. 7, the substrate 6 is formed with a trapezoidal dicing blade using a dicing apparatus in a region where the slit hole 80 is formed in the semiconductor substrate 60.
0 is subjected to a dicing process (shaving the surface of the substrate 60) at a predetermined depth. In this dicing process, the tapered portion 91 is formed.
A concave portion 92 having a shape is formed on the substrate 60. The angle of the tapered portion 91 is determined by the shape of the dicing blade, and can be arbitrarily set according to the size of the solder joint and the amount of solder.

After forming the concave portion 92 in the first substrate 60,
As shown in FIG. 8, a metal plating layer 93 such as solder is formed on the surface of the first substrate 60. Since the plating layer 93 is formed on the entire surface of the substrate 60 other than the surface of the resin layer 95 filled in the slit holes 80, it is also formed on the surface of the tapered portion 91 of the concave portion 92. Therefore, in this embodiment, two types of dicing steps are performed with the plating step interposed.

As described above, by forming the slit hole 80 after forming the concave portion 92, the tapered portion 91 of the concave portion 92 remains, and the external connection electrodes 62, 63, 6 are formed.
4. . . Can be tapered. When the plating layer 93 is formed after forming the concave portion 92 and the slit hole 80 is formed, the plating layer can be formed on the tapered portion 91 in the same plating process.

The semiconductor device in which the slit holes 80 are provided in the first semiconductor substrate 60 and the external connection electrodes 62, 63, 64 are electrically separated and formed is a ceramic substrate, a glass epoxy substrate, a phenol substrate, an insulation treatment, and the like. Is fixedly mounted on a pad of a conductive pattern formed on a wiring substrate such as a metal substrate subjected to the above. A solder layer on which solder cream is pre-printed is formed on the pad. If the semiconductor device of the present invention is mounted by melting the solder, the semiconductor device can be fixedly mounted on the pad of the mounting board. .

At this time, as described above, each of the external connection electrodes 62, 63, 64. . . Tapered section 9 at the edge
With the formation of 1, the solder fillet at the solder joint with the conductive pad (land) of the mounting board can be optimized, the joint strength at the solder joint can be improved, and the connection reliability can be improved. . Although not shown, this fixed mounting process can be performed in the same process as the mounting process of other circuit elements to be solder-mounted such as chip capacitors and chip resistors mounted on a mounting board.

When the semiconductor device of the present invention is mounted on a mounting substrate, the external connection electrodes 62, 63, and 64 are separated by the interval of the slit holes 80, so that the solder fixed to the mounting substrate does not External connection electrodes 62 arranged adjacent to each other,
There is no short circuit between 63 and 64. By the way, as shown in FIG. 9, in the semiconductor device of the present embodiment, for example, an active element active element forming region 61 having almost the same function as the semiconductor device described in the conventional example is set to a size of 0.5 mm × 0.5 mm. Connection electrode regions 63A serving as base and emitter electrodes,
64A is 0.3mm x 0.2mm size, and slit hole 8
In a semiconductor device in which the width of 0 is 0.1 mm, the effective area ratio is as follows. That is, since the element area is 0.25 mm and the area of the semiconductor device which is the mounting area is 1.28 mm, the effective area ratio is about 19.53%.

0.40 mm × 0.40 mm explained in the conventional example
Since the effective area ratio of the semiconductor device having the chip size of 6.25% is 6.25% as described above, the effective area ratio of the semiconductor device of the present invention is about 3.12 times larger, and the semiconductor device of the present invention is mounted on a mounting substrate. The dead space of the area can be reduced, which can contribute to downsizing of the mounting substrate.

As described above, the first semiconductor substrate 60 on which the first active element is formed and the second semiconductor substrate 100 on which the second active element is formed are integrated to form the first active element. And the second active element are electrically connected, and the first,
The external connection electrode of the second active element uses the first semiconductor substrate 60 which is electrically separated and divided into a plurality of parts, so that the metal lead terminal connected to the external electrode and the protection can be provided as in the conventional semiconductor device. This eliminates the need for a sealing mold for the semiconductor device, and can significantly reduce the external dimensions of the semiconductor device. Further, a highly functional semiconductor device in which a first active element such as a transistor and a second active element such as a bipolar IC are combined can be provided.

Further, as described above, since the metal lead terminals for external connection and the mold for resin sealing are unnecessary, the manufacturing cost of the semiconductor device can be significantly reduced. Further, in the present invention, since the semiconductor device is provided using the first and second semiconductor substrates 60 and 100,
First, existing semiconductor manufacturing equipment can be used as it is, and there is no need to newly introduce equipment. Secondly, if both substrates 60 and 100 are silicon substrates, they have the same thermal expansion coefficient α, so that even when heat is generated by external heating or self-heating, the same stress is applied to the upper and lower sides to cancel each other. Can be suppressed from being adversely affected by distortion.

In the present embodiment, the transistor is formed in the active element formation region 61 of the first substrate 60. However, the present invention is not limited to this, as long as it is a vertical device or a horizontal device having a relatively small amount of heat generation. , IGBT, HB
It goes without saying that a device such as T can be formed in the active element formation region 61. Further, devices such as MOSIC and BiCMOS may be formed on the second substrate 100.

Incidentally, in the above embodiment, the resin layer 7
8, the electrical conduction between each electrode of the substrate 60 and the electrode and the wiring pattern of the second substrate 100 was performed using a photo-thermosetting resin. For example, even if an anisotropic conductive resin is used as the resin layer 78 as shown in FIG.
Can easily be connected to the electrodes of the second substrate 100 and the wiring patterns.

The anisotropic conductive resin includes a resin in which a conductive material 81 having a particle size is mixed in a resin paste and a resin in which a conductive material having a particle size is dispersed in a resin sheet. It is also possible. Anisotropic conductive resin is used for both substrates 6
A region where electrodes, wiring patterns, and the like formed on 0 and 100 overlap with each other is electrically connected via a conductor 81 having a particle size. When using an anisotropic conductive resin,
The bump electrodes 115 are provided on the electrodes 75, 76, 77 on the first substrate 60 and on the electrodes and the wiring patterns on the second substrate 100, that is, on the plating layers 79, 111, 114, respectively.
A and 115B are preferably formed.

For example, an anisotropic conductive sheet is applied to the first substrate 6
0, and the bump electrodes 115A on the substrate 60 and the bump electrodes 115B on the second substrate 100 are aligned with each other. A heat treatment is performed to a degree to melt the conductive sheet to form a resin layer 78, and the electrodes 75, 76 formed on the first substrate 60 by the conductive material 81 having a particle size.
The connection between 77 and the electrodes and the wiring pattern formed on the second substrate 100 is performed. By forming the bump electrodes 115A and 115B on both substrates 60 and 100, the conductive material of the anisotropic conductive resin does not come into contact with the electrode or the like overlapping with the wiring pattern A, so that the first substrate is securely connected. The bump electrodes 115A of the upper electrodes 75, 76, and 77 come into contact with the bump electrodes 115B on the second substrate 100, and electrical conduction is performed.

As another method of electrical conduction, as shown in FIG. 11, bumps 115A and 115B formed on both
Alignment of the bump electrodes 115A, 1
15B, the electrodes 75 on the first substrate 60,
Electrical conduction between the electrodes 76 and 77 and the electrodes and wiring patterns on the second substrate 100 is performed. Thereafter, both substrates 60, 1
While applying pressure to 00, an impregnating material made of a liquid thermosetting resin is poured into the gap between the substrates 60 and 100, and heat treatment is performed to form the resin layer 78, and the slit holes 80 are formed.

According to the present invention, an external connection electrode of a semiconductor device in which a first semiconductor substrate on which an active element such as a transistor is formed and a second semiconductor substrate on which a bipolar IC or the like is formed is opposed to each other is used. Slit hole 80 formed in
Is characterized in that the first semiconductor substrate separated by the above is used as an electrode for external connection.
The means for connecting to 00 is not limited to the above-mentioned means for connection, and it is needless to say that the present invention can be achieved using any structure and any material.

[0065]

As described in detail above, according to the present invention, a first semiconductor substrate on which a first active element is formed;
Integrating a second semiconductor substrate on which a second active element is formed, electrically connecting the first active element and the second active element, and externally connecting the first and second active elements The use of the first semiconductor substrate, which is electrically separated and divided into a plurality of electrodes, eliminates the need for a metal lead terminal connected to an external electrode and a protective sealing mold as in a conventional semiconductor device. In addition, the external dimensions of the semiconductor device can be significantly reduced. Further, a highly functional semiconductor device in which a first active element such as a transistor and a second active element such as a bipolar IC are combined can be provided.

Further, according to the present invention, as described above, the metal lead terminal for external connection and the resin sealing mold are not required, so that the manufacturing cost of the semiconductor device can be significantly reduced. Furthermore, in the present invention, the first and second
Since semiconductor devices are provided using semiconductor substrates of
First, existing semiconductor manufacturing equipment can be used as it is, and there is no need to newly introduce equipment. Secondly, if both substrates are silicon substrates, the thermal expansion coefficient α is equal, so even when heat is generated by external heating or self-heating, the same stress is applied to the upper and lower sides to cancel each other, so that the adverse effect due to the distortion of the substrate is suppressed. Can be performed without reducing the reliability.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 2 is a diagram showing a back surface of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 6 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 7 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 8 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 9 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 10 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 11 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 12 is a cross-sectional view illustrating a conventional semiconductor device.

FIG. 13 is a cross-sectional view of a general transistor.

FIG. 14 is a cross-sectional view in which a conventional semiconductor device is mounted on a wiring board.

FIG. 15 is a plan view of a conventional semiconductor device.

FIG. 16 is a plan view of a conventional semiconductor device.

FIG. 17 illustrates a conventional semiconductor device.

FIG. 18 illustrates a conventional semiconductor device.

Claims (5)

[Claims] 1. A semiconductor device in which a first semiconductor substrate on which a first active element is formed and a second semiconductor substrate on which a second active element is formed are integrated, wherein the first active element is The element and the second active element are electrically connected, and the external connection electrodes of the first and second active elements use the first semiconductor substrate that is electrically separated and divided into a plurality. Characteristic semiconductor device. 2. An external connection electrode region in which a first active element is formed in a predetermined active element formation region of a substrate, and wherein the substrate in the active element formation region has at least one electrode of the active element. A first semiconductor substrate having at least a plurality of other external connection electrode regions electrically connected to another electrode of the active element and being a part of the substrate, and at least the other electrode and the other A second semiconductor substrate on which a wiring pattern for electrically connecting an external connection electrode and a second active element are formed, the first semiconductor substrate and the second semiconductor substrate are integrated, The first pattern via the wiring pattern formed on the second semiconductor substrate;
Other electrodes of the active element and the other external connection electrode area,
And an electrode of the second active element is connected to the other external connection electrode region, and the one external connection electrode region and the other external connection are formed by a slit provided in the first semiconductor substrate. A semiconductor device characterized in that the electrode region is electrically separated from the electrode region. 3. The semiconductor device according to claim 1, wherein said first semiconductor substrate and said second semiconductor substrate are arranged via an insulating adhesive resin layer. 4. The semiconductor device according to claim 1, wherein said first active element is a transistor or a power MOSFET. 5. The semiconductor device according to claim 1, wherein said second active element is a bipolar IC, a MOSIC, or a composite IC thereof.