JPH11261001A - Manufacture of three dimensional semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of three dimensional semiconductor integrated circuit device rapidly and accurately capable of reducing the process to manufacture the device for laminating to improve the reliability. SOLUTION: In the manufacture of a three dimensional semiconductor integrated circuit device, vertical mutual connectors 17 are buried in a trench while the steps in clude the step of setting an LSI wafer 11 as an upper layer formed of a semiconductor integrated circuit, the step of forming bumps 19 on the ends of the vertical mutual connectors 17, the step of laminating the upper layer LSI wafer 11 on a wafer 1 as a substrate formed of lower layer semiconductor integrated circuit through the intermediary of the bumps 19, and the step of injecting insulating adhesives 20 between the upper and lower layers wafers 1 and laminated by the bumps 19 only.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a three-dimensional semiconductor integrated circuit device by bonding using a micro-integration technique.

[0002]

2. Description of the Related Art LSI (Large Scale In)
(Circuited Circuit) has been improved in integration and performance due to advances in microfabrication technology. However, with the miniaturization of elements, problems such as an increase in wiring resistance and parasitic capacitance have occurred. Furthermore, recently, the limit of miniaturization of the element has been discussed, and it is considered that it is difficult to achieve high performance simply by miniaturizing the element.

As a solution to such a problem, there is a three-dimensional semiconductor integrated circuit. In this three-dimensional semiconductor integrated circuit, by using vertical interlayer wiring, the degree of freedom in wiring and the length of wiring are reduced, so that parallel transfer of data using vertical wiring becomes possible.

[0004]

However, three-dimensional semiconductor integrated circuits which have been studied in the past employ a method in which an element is formed, an insulating film is formed, and a single crystal is formed on the insulating film. . Since this method is repeated to produce devices and sequentially form integrated circuits, the process (step) becomes longer, and the yield is remarkably reduced.

In order to solve the problems of the conventional three-dimensional integrated circuit, research on a three-dimensional semiconductor integrated circuit device by bonding has been advanced, but a technically satisfactory one has not been manufactured. is the current situation. The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a three-dimensional semiconductor integrated circuit device by bonding, which can reduce the number of steps, rapidly and accurately manufacture, and improve reliability.

[0006]

According to the present invention, there is provided a method for manufacturing a three-dimensional semiconductor integrated circuit device by laminating: (a) forming a vertical interconnect to be embedded in a trench; Forming and setting an upper wafer on which a semiconductor integrated circuit is formed; (b) forming a bump on an end face of a vertical interconnect of the upper wafer; and (c) via the bump. Bonding a wafer on a substrate on which a lower semiconductor integrated circuit is formed; and (d) injecting an insulating adhesive between the upper and lower two-layer wafers bonded and laminated using only the bumps. Is applied.

[2] In the method for manufacturing a three-dimensional semiconductor integrated circuit device according to the above [1], a portion other than the inlet of the insulating adhesive is sealed with a wall, and the insulating adhesive is injected using a pressure difference. It is something to do. [3] The method for manufacturing a three-dimensional semiconductor integrated circuit device according to [1] or [2], wherein a plurality of the upper wafers are stacked.

[4] The method for manufacturing a three-dimensional semiconductor integrated circuit device according to the above [3], wherein a step of injecting an insulating adhesive at one time between the bumps on which the plurality of laminated wafers are bonded is performed. It is like that. [5] The method for manufacturing a three-dimensional semiconductor integrated circuit device according to [1], wherein an epoxy-based adhesive is used as the insulating adhesive.

[6] In the method for manufacturing a three-dimensional semiconductor integrated circuit device according to [1], in the step (a), the upper and lower two-layer wafers are positioned after being thinned by a chemical mechanical polishing method. It is like that. [7] In the method for manufacturing a three-dimensional semiconductor integrated circuit device according to the above [1], the bump is a bump made of one or more kinds of metals.

[8] The method of manufacturing a three-dimensional semiconductor integrated circuit device according to [1], wherein a conductive adhesive layer is formed on all or a part of the surface of the bump.

[9] In the method for manufacturing a three-dimensional semiconductor integrated circuit device according to [1], the wall and the bump are made of Cu. [10] In the method for manufacturing a three-dimensional semiconductor integrated circuit device according to [1], the bumps are made of Au / In.

It should be understood that the wafer includes a large-scale and large-area chip.

[0012]

Embodiments of the present invention will be described below in detail. FIG. 1 is a cross-sectional view of a bonded three-dimensional semiconductor integrated circuit device showing an embodiment of the present invention, FIG. 2 is a cross-sectional view of a manufacturing process of the three-dimensional semiconductor integrated circuit device showing an embodiment of the present invention, and FIG. FIG. 13 is a sectional view of an adhesive injecting step in the manufacturing process of the three-dimensional semiconductor integrated circuit device showing the example of FIG.

In FIG. 1, 1 is an LSI wafer of a first layer, 11 is an LSI wafer of a second layer, and 21 is an LSI wafer of a third layer.
LSI wafers 1, 11, 21 of each layer
Are MOSFET3,1 on silicon substrates 2,12,22
3, 23, etc. are formed. This three-dimensional semiconductor integrated circuit uses a manufacturing method in which a thin layer is formed from a back surface of a wafer on which elements are manufactured by a chemical mechanical polishing (CMP) method, and then laminated by laminating the layers. .
The stacked integrated circuits are electrically connected to each other by micro-bumps formed in advance and embedded wirings in the vertical direction.

That is, a vertical interconnect 17 is formed on the field oxide film 16, and a micro bump (Cu or Au / In) 19 is formed on an end surface of the vertical interconnect 17, and a micro bump of a laminated wafer is formed. Join with the bump. An insulating adhesive (epoxy-based adhesive) 20 is injected between the joined microbumps 19 to bury the microbumps 19.

This three-dimensional semiconductor integrated circuit has a manufacturing method in which a thin layer is formed from the back surface of a wafer on which elements are manufactured by a chemical mechanical polishing (CMP) method, and the thin layers are laminated to form a multilayer. Used. The stacked integrated circuits are electrically connected to each other by micro-bumps formed in advance and embedded wirings in the vertical direction. Here, the formation of the buried interconnect, thinning of the wafer, wafer alignment, and wafer bonding using an adhesive injection method are important technologies.

Here, it is necessary to make a deep silicon trench to form a vertical buried interconnect. A silicon trench having a depth of more than 50 μm can be formed by using a high-speed inductively coupled plasma (ICP) etching apparatus and optimizing etching conditions. It is also possible to form a deep silicon trench with a depth of 100 μm.

The thickness of the wafer is reduced to 50 μm by grinding and chemical mechanical polishing (CMP). 10 μm thickness
It is also easy to make it less than. For wafer alignment, the alignment tolerance can be set to ± 0.5 μm. When a Cu bump is used as a metal bump, it is necessary to apply a conductive adhesive such as an epoxy-based silver paste to the surface of the bump in advance in order to bond the upper and lower Cu bumps to each other. A printing method was used to apply a silver paste to the Cu bump surface. When the conductive adhesive is applied to the surface of the bump, the conductive adhesive is formed on all or a part of the surface of the bump.

Hereinafter, a method of manufacturing a three-dimensional semiconductor integrated circuit device according to an embodiment of the present invention will be described with reference to FIG. (1) First, as shown in FIG. 2A, first, a second-layer LSI wafer 1 which is a thinned two-dimensional LSI wafer
In order to make a vertical interconnect, a buried vertical interconnect 17 is deposited in a trench (groove) by depositing n ⁺ polysilicon. It is needless to say that the buried vertical interconnect 17 is not limited to n ⁺ polysilicon but may be a conductor such as a metal.

(2) Next, as shown in FIG. 2 (b), a two-dimensional LSI wafer having a vertical interconnect 17 is bonded to quartz glass 18 and ground and chemically and mechanically polished. Thin until 50 μm. (3) Next, as shown in FIG.
Microbumps 19 are formed on the end surfaces of the embedded vertical interconnect 17 of the wafer 11. (4) Next, as shown in FIG. 2D, the thin second-layer LSI wafer 11 is carefully aligned with the first-layer LSI wafer substrate 1 via the micro bumps 19, and the thick first
The layer is bonded to the LSI wafer substrate 1.

This procedure is repeated, and several thin wafers are stacked on the LSI wafer substrate 1 of the first layer. (5) Finally, as shown in FIG. 2E, the insulating adhesive 20 is injected into the gap between the wafers to enhance the bonding property of the wafers. Next, an adhesive injection step in a manufacturing process of a three-dimensional semiconductor integrated circuit device according to an embodiment of the present invention will be described in detail with reference to FIG. Here, Cu bumps were used as the bumps, and an insulating epoxy adhesive was used as the insulating adhesive.

(1) First, as shown in FIG. 3A, a Cu wall 4 is formed on each wafer so as to surround a Cu bump 42.
3 is formed. A small entrance 4 in a part of this Cu wall 43
Make 4. A wafer group 41 in which such wafers are stacked
Is placed in a vacuum chamber evacuated to about 10 ⁻³ Torr. Here, the Cu wall can be formed simultaneously with the formation of the Cu bump, which is advantageous in the manufacturing process. However, instead of the Cu wall, the wall may be formed of an insulator or the like.

(2) Next, as shown in FIG. 3B, the portion including the entrance 44 of the Cu wall 43 of the stacked wafer group 41 is immersed in an insulating epoxy adhesive 45 in a vacuum state. (3) Next, as shown in FIG. 3C, the vacuum state is broken. For example, N ₂ gas is leaked. (4) Then, as shown in FIG. 3D, when the vacuum state is broken and the atmospheric pressure is reached, the pressure in the gap between the wafers in the Cu bump area is lower than the atmospheric pressure. The insulating epoxy adhesive 45 is injected by capillary action.

Therefore, the insulating epoxy adhesive 45 is 2
It is also possible to inject not only between two wafers but also simultaneously into a gap between many wafers (see FIG. 1). FIG. 4 is a view showing a plane after bonding a glass substrate to a silicon substrate having Cu bumps by using the adhesive injection method, and FIG. 4A is a plan view of a wafer having the Cu bumps. 4 (b) is an enlarged view of a portion A (near the Cu wall) in FIG. 4 (a), and FIG. 4 (c) is an enlarged view of a portion B (inside the Cu wall) of FIG. 4 (a).

As is clear from these figures, the Cu wall 4
In FIG. 3, the insulating epoxy adhesive 45 is uniformly filled except for the Cu bumps 42, and does not generate voids as shown in FIG. On the other hand, insulating epoxy adhesive 45
Is injected into the gap between the outer wafers of the Cu wall 43 by capillary action, but this injection is not uniform. That is, voids 46 were observed in the insulating epoxy adhesive 45.

FIG. 5 is a diagram showing a cross section of FIG. As is apparent from FIG. 5, an insulating epoxy adhesive 45 is formed between the Cu bumps. In other words, it can be seen that the insulating epoxy adhesive 45 has entered into places other than the Cu bumps. Since the insulating epoxy adhesive mixes the main component and the curing agent and cures by a chemical reaction, the volume change after curing is small.

For the microbumps, Au / In may be used instead of Cu. Au / I
In the case of n-bumps, after bonding the bumps, the temperature can be raised to near 150 ° C., which is the melting point of In, so that an alloy can be formed by bonding the bumps. Therefore, the bump could be produced without having to consider the size of the silver filler contained in the adhesive, which had been a problem when producing the Cu bump.

Hereinafter, a method of forming an Au / In bump and a method of bonding the same will be described, and experimental results will be shown. After applying a positive resist on the entire surface of the wafer on which the silicon oxide film has been formed by spin coating, patterning of bumps to be formed is performed.
Then, In (3 μm) and Au (30 μm) were
(00 °)). Thereafter, the silicon wafer on which the Au / In bumps have been formed is put into acetone and subjected to ultrasonic cleaning (lift-off method), whereby Au / I is obtained.
N bumps can be made.

FIG. 6 is a diagram showing a cross section of an Au / In bump (40 μm square, 3 μm height) bonded between two layers using an adhesive injection method according to another embodiment of the present invention.
In FIG. 6, 61 is an upper wafer, 62 is a lower wafer,
63 and 64 are Au / In bumps, 71 is an insulating epoxy adhesive, and the very narrow upper wafer 61 and lower wafer 6
An insulating epoxy adhesive 71 is injected between the two without voids. Until now, Au / I of 5 μm square at 2 μm height
Adhesive injection using n bumps has also been successful.

Next, test chips of the Au / In bumps 63 and 64 were manufactured in order to examine the electrical characteristics of the Au / In bumps 63 and 64. The method and Au / I
The results of the electrical characteristics of the n bumps 63 and 64 are shown. Au / I
In order to investigate the electrical characteristics of the n bumps, a test chip capable of passing a current through an Al wiring and a plurality of bumps was manufactured. In this test chip, Au
/ In bumps are prepared, and polyimide is applied as a wiring protective film to locations other than the bumps. The pad for applying the probe is located outside the wafer to which the Al wiring is extended and bonded so that the pad can be used even when the wafers are bonded to each other. Using this test chip, an experiment was conducted in which a current was passed through the Al wiring to measure the resistance of the Au / In bump.

FIG. 7 is a diagram showing the measurement results. This is the result of 42 Au / In bumps (20 μm
(Electrical characteristic results obtained when a current is passed through a corner and a height of 3 μm). From this result, the resistance per Au / In bump is about 12Ω, but the
A calculated from the depth, length, and specific resistance of the u and In bump layers
The resistance value per u / In bump is about 1Ω. Therefore, the measured value is higher than the calculated value,
Low resistance is expected due to process improvement.

As described above, the micro bumps required for the three-dimensional integration technology were manufactured, and the adhesive injection method was used.
A three-dimensional semiconductor integrated circuit device can be manufactured. Using this adhesive injection method, it was confirmed that an insulating adhesive could be injected void-free between wafers bonded by Au / In or Cu bumps. As a result, an adhesive injection technique was established as a wafer bonding method.

A test chip for measuring the electrical characteristics of the Au / In bump was prepared and connected in series.
Current can flow through the bumps of the step. It should be noted that the present invention is not limited to the above embodiment, and various modifications can be made based on the gist of the present invention, and these are not excluded from the scope of the present invention.

[0033]

As described above, according to the present invention, the following effects can be obtained. (1) According to the first aspect of the present invention, in the method of manufacturing a three-dimensional semiconductor integrated circuit device, the number of steps can be reduced, the manufacturing can be performed quickly and accurately, and the reliability can be improved.

(2) According to the second aspect of the present invention, the assembly of the LSI wafer can be strengthened by injecting the insulating adhesive between the bumps of the wafer. (3) According to the third aspect of the invention, it is possible to easily assemble a plurality of layers of LSI wafers and to improve the degree of integration. (4) According to the fourth aspect of the invention, a plurality of stacked wafers can be easily and reliably assembled at once.

(5) According to the fifth aspect of the present invention, since the epoxy-based adhesive is mixed with the main agent and the curing agent and cured by a chemical reaction, the volume change after curing is small. (6) According to the sixth aspect of the present invention, accurate positioning can be performed since the upper and lower LSI wafers are positioned after being thinned by a chemical mechanical polishing method.

(7) According to the present invention, the upper and lower LSI wafers can be firmly joined. (8) According to the invention described in claim 8, electrical connection between the upper and lower LSI wafers can be ensured. (9) According to the ninth aspect of the present invention, the process can be simplified using a typical material, and stable walls and bumps can be formed.

(10) According to the tenth aspect of the present invention,
An alloy can be made by bonding the bumps together, and strong temporary fixing can be performed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a bonded three-dimensional semiconductor integrated circuit device showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the three-dimensional semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 3 is a sectional view showing an adhesive injection step in a manufacturing process of the three-dimensional semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 4 is a view showing a plane after bonding a glass substrate to a silicon substrate having Cu bumps by using an adhesive injection method in a manufacturing process of a three-dimensional semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 5 is a diagram showing a cross section of FIG. 4;

FIG. 6 is a view showing a cross section of an Au / In bump bonded between two layers by using an adhesive injection method according to another embodiment of the present invention.

FIG. 7 is a view showing a measurement result of resistance of a bonded Au / In bump showing another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 First-layer LSI wafer 2, 12, 22 Silicon substrate 3, 13, 23 MOSFET 4, 14 Wiring 11 Second-layer LSI wafer 16 Field oxide film 17 Vertical interconnect 18 Quartz glass 19 Micro bump (metal bump: Cu or Au / I
n) 20 Insulating adhesive (epoxy adhesive) 21 Third-layer LSI wafer 41 Wafer group 42 Cu bump 43 Cu wall 44 Entrance 45, 71 Insulating epoxy adhesive 46 Void 61 Upper wafer 62 Lower wafer 63, 64 Au / In bump

 ──────────────────────────────────────────────────の Continuation of the front page (72) Inventor Hiroyuki Kurino 3-1-403 3-1 Migamimine, Taihaku-ku, Sendai-shi, Miyagi Prefecture

Claims (10)

[Claims] 1. A method of manufacturing a three-dimensional semiconductor integrated circuit device by bonding, comprising: (a) forming a vertical interconnect to be embedded in a trench and setting an upper wafer on which the semiconductor integrated circuit is formed; , (B)
Forming a bump on an end face of the vertical interconnect of the upper wafer, and (c) bonding the lower semiconductor integrated circuit via the bump onto a wafer serving as a substrate on which the lower semiconductor integrated circuit is formed; d) a step of injecting an insulating adhesive between the upper and lower two-layer wafers bonded and laminated only with the bumps. 2. A method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein a portion other than the inlet of the insulating adhesive is sealed with a wall, and the insulating adhesive is injected using a pressure difference. A method for manufacturing a three-dimensional semiconductor integrated circuit device, comprising: 3. The method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein a plurality of the upper wafers are stacked. 4. A method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 3, further comprising the step of injecting an insulating adhesive at one time between the bumps on which the plurality of laminated wafers are bonded. A method for manufacturing a three-dimensional semiconductor integrated circuit device. 5. The method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein an epoxy-based adhesive is used as the insulating adhesive. 6. The method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein in the step (a), the upper and lower two-layer wafers are positioned after being thinned by a chemical mechanical polishing method. A method for manufacturing a three-dimensional semiconductor integrated circuit device. 7. The method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein said bump is a bump made of one or more kinds of metals. Method. 8. The method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein a conductive adhesive layer is formed on all or a part of the surface of the bump. Production method. 9. The method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein said walls and bumps are made of Cu. 10. The method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein said bumps are made of Au / In.