JPS60140850A - Manufacture of laminated integration type semiconductor circuit device - Google Patents

Abstract

PURPOSE:To obtain a new method of forming a semiconductor chip having a through hole coated with an insulation film with a structure more suitable for laminated integration, by a method wherein the through hole is formed by two steps. CONSTITUTION:An SiO2 film 601 is formed on the surface of an Si crystal substrate 600, which is then provided with an aperture 602, and a fine hole 603 is formed by using the oxide film 601 as a mask. An insulation film 604 is formed on the inner wall of this fine hole 603 and coated with polycrystalline Si605, and the Si605 is removed with the fine hole part left. Next, an Al607 is formed on the back, and a fine hole 608 is provided by etching until the bottom of the hole 603 is exposed. Then, a CVD-SiO2 609 is deposited, and the bottom of the fine hole is provided with an aperture 610. A multilayer metal film 614 is patterned by vapor deposition, and a solder layer is formed by plating and then patterned again with the same shape as the metal film 614 of the base; then, the solder layer becomes spherical by heating, resulting in the formation of solder bumps 611 and 612.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for manufacturing a chip structure suitable for constructing a stacked integrated semiconductor circuit device formed by stacking semiconductor integrated circuit chips, and particularly relates to the basics of the stacked structure. The present invention relates to a method for manufacturing a wiring through hole.

[Background of the invention]

Advanced electronic circuit systems such as computers have traditionally been made up of high-density integrated circuit (LSI) packages, which are arranged in large numbers on printed wiring boards, and then printed circuit boards. It was constructed using a mounting method that connects Jj numbers.

In more advanced systems.

Configuring a multi-chip module as illustrated in FIG. 1,
In addition to shortening the wiring length to improve the degree of integration, wiring delays were also reduced to increase speed.

In the multi-chip module shown in FIG. 1, each LSI chip 11, 11', 11' has the layer 12 on which the element is formed facing downward, and the bonding pad 13 provided at the periphery of the chip is connected to the multilayer wiring ceramic substrate. The bonding pad 15 is opposed to the bonding pad 15 provided on the top of the bonding pad 14, and is connected by the known Fester run bonding technique.

This multi-chip module does not require metal wire +W for bonding, and each chip is fixed to the multilayer wiring board by solder, which has many advantages such as packaging density and system reliability.

However, in these conventional hidden methods, the starting point is a completed LSI chip, bonding pads are provided only on the periphery of each chip, and connections between chips are not made through a multilayer wiring board. Therefore, there was a limit to the reduction in wiring length. That is, with this method, it was not possible to transmit signals between chips over a distance shorter than the wiring length that could be obtained by arranging the chips in a planar manner.

There is a chip stacking type integration technique illustrated in FIG. 2 as a method for transmitting signals between chips over a distance shorter than the wiring length obtained by arranging the chips in a plane. In this example,
On one side of the LSI chips 21.21', 21'', etc., layers 22.22', -22'', etc. on which element groups are formed are provided,
The bonding pad 26 provided on the element layer 22 and the bonding pad 24 provided on the back surface of the chip 21' are connected, and the chips are sequentially stacked and stacked in this manner.
are connected and mounted on the substrate 25.

In order to form a stacked integrated circuit with such a configuration,
A structure for transmitting signals from both the front and back surfaces of the chip is required, and for this purpose a structure as shown in FIG. 3 has been proposed. That is, in the semiconductor substrate 30.30', element groups are formed in the shape FJ'Z on the front main surface 31.31', and passive element groups, for example, are also formed on the back main surface 32.32'. Power supply or signal wiring between the element groups, through hole 3
3.33', the inner wall of the through hole is doped with a high a degree of conductivity type opposite to that of the substrate, and the low resistance region 34-. 34. ', 3db, 34b', etc. Conductive layers 35-. 35b, 35c, 35a, 35a'
.

35 b', 35 c', 35 d', etc., to enable wiring connections between the front and back surfaces. Here, the difference between the cross-sectional shapes (A) and (0) is due to the method of forming the through hole; (A) is obtained by drilling from the back side by sputtering with argon, etc.; The openings were made by etching or the like.

However, such a structure had several drawbacks. First, the conductor passing through the through hole is a highly concentrated diffusion layer.

Moreover, it has a structure in which the junction is separated from the substrate, so
There are some restrictions to make full use of such a structure. 1. In other words, when using a through-hole, it must always be used in a reverse biased state with respect to the substrate, and the arrangement of the through-hole must be carefully arranged to prevent latch-up caused by parasitic bipolar elements. This has hindered high integration. Also, since the insulation isolation uses the entire depletion layer of the junction, the parasitic capacitance is large, and if it is used for signal wiring, there will be a significant signal delay. Because this is a prerequisite, it was not very effective in speeding up the process.

In order to overcome all of these drawbacks, a structure in which the through hole is covered with an insulating film as shown in FIG. 4 has been proposed. FIG. 4 shows a cross section of an individual chip before interconnection between the chips is made. Semiconductor substrate 41 that makes up the entire chip.
Element groups are provided on the surface of each of 41' by selective doping, and chip through holes 112, 42', etc. are provided in some parts.

Through hole 42. The surface of B' is an insulating film 43 made of an oxide film or the like.
43' etc. are provided, and conductive coatings 44, 4 . , i' and the substrate 1.41' are electrically isolated. Solder bumps 45, 45' used for interconnection between chips are formed on the wiring layer, and the bumps 45' of the lower chip are connected to bonding pads 44 extending from the openings of the upper chip. is facing directly. The size of the solder bump shown in this example is approximately 20 μm in diameter, which is larger than the multilayer wiring, the surface unevenness existing on the K-chip, and the warpage of the chip. Care has been taken to ensure that the pads are in contact with the opposing bonding pads. The volume of the through hole was designed to be larger than the total volume of the solder bump so that the solder would not come into contact with the solder pressed out from the bonding pad when melting the solder by hot pressure welding.

In such a structure, the inner wall of the through hole is covered with an insulating film such as 8102, which has a dielectric constant of about 1A of 81, and its thickness can be set arbitrarily. Stray capacitance parasitic to wiring can be significantly reduced. Furthermore, since it is completely separated from the substrate by the insulating film, it is possible to design a multilayer device without paying too much attention to voltage or polarity, making it an extremely advantageous structure from an application standpoint.

However, in the illustrated structure, in order to take up the entire internal volume of the through hole, for example, in the case of a 50 μm thick semiconductor substrate, it is necessary to form all the through holes with a diameter of 10 μm or more, which improves the concentration of VR. It was totally inhibited. In addition, since the solder bumps are formed only on one side of the semiconductor substrate, a connection failure may occur during thermal IE bonding depending on the surface condition of the opposing bonding pad, which may cause some reliability problems. [Objective of the Invention] The present invention provides a semiconductor chip having all through holes covered with such an insulating film, which can be assembled into an agitated layer! *The aim is to provide a new manufacturing method to provide a more suitable structure.

[Summary of the invention]

The present invention uses solder bumps on both opposing bonding pads to ensure reliable and self-aligned chip-to-chip connection. In order to completely prevent lateral leakage of bumps, we provide a complete method for manufacturing a bump that reliably forms a tip rail having a structure in which a larger opening is provided on the back side of the bump than on the front side with respect to the through hole. It is.

[Embodiments of the invention]

The following will explain one embodiment of the present invention.

FIG. 5 is a schematic cross-sectional structure diagram of a chip obtained by applying the present invention. Note that in order to simplify the drawing, only a portion including one trap hole is shown. This structure will be briefly explained below.

Element groups are formed on the surface of the semiconductor substrate 500 by selective doping or the like. A through hole is provided in a part of the substrate, and the through hole has a detail 51. and a thick portion 52. The inner surface of the through hole is covered with a relatively thick insulating film 56 such as an oxide film, which provides electrical insulation between the conductor layer 54 formed inside the through hole and the semiconductor substrate 50, and at the same time completely reduces parasitic capacitance. are doing. The conductor layer inside the through hole is the through hole detail 51
A bonding pad 55 is connected to the lower surface of the chip at the boundary between the thick portion 52 of the through hole and a downward solder bump 56 is formed on the bonding pad. The conductive five-body layer 54 in the through hole is connected to a bonding pad 58 on the top surface of the chip via a multilayer wiring layer 57 on the element group forming surface side, and an upward solder bump 59 is formed on the bonding pad 58. . C and D shown in FIG. 5 indicate all conductor portions within the multilayer wiring layer for transmitting signals to the gate of the element. In the example of FIG. 5, the K through-hole wiring connects the upper solder bump 59 and the lower solder bump 56, and is also connected to one output of the element, but of course such a configuration Although not limited to, the multilayer wiring layer 5
It is no secret that any input/output can be connected to the upper and lower solder bumps through the 7 pins.

Although FIG. 5 shows one through hole and one set of upper and lower solder bumps, in reality, a large number of these east through holes and bumps are formed.

The manufacturing method of the present invention, which can be used to completely form such a through-hole wiring structure, will be explained with reference to FIG. 6. One of the features of the invention is that the through-holes are formed in two stages.

First, in the same figure (A), the thickness of the Tsutomu is about 4DOμm and the first
Using a silicon crystal substrate 600' of conductivity type, for example p-type (rloo) plane of p-type 10 cTL, as a starting material, S Io 2+16% with a thickness of about 1 μm is deposited on the surface by a known thermal oxidation method.
601i is formed. The 5i02 film in the area where the through hole should be formed is removed by photolithography to form the opening 602.
Set up a meeting. The size of the opening can be determined arbitrarily, but it is usually 2μ.
Appropriately, it has a square size of 5 μm to 5 μm. Then, using this oxide film 601 as a mask as shown, the well-known CF4
By the parallel plate plasma etching method using the mixed gas of
Form 5 μm. The vertical cross-sectional shape of micropores is not necessarily (b)
Although it does not have to be vertical as shown in the figure, it is convenient to have a structure with a wide bottom surface in order to make contact from the back side in the future.
If necessary, the entire side wall and bottom of the micropore 603 may be etched and enlarged using a mixed solution of HF and HNO3. Although the depth of the microholes may be deeper, it is not advisable to use a thicker mask material to form all the through-holes over the entire wafer thickness, and it also takes time. Mask material and Si
Taking into consideration the etching resistance ratio between the
μm Hodgawa.

is the business.

Next, an insulating film is formed on the inner walls of the micropores, particularly on the side walls. Several methods are possible for this method, depending on the process of forming element clusters on the surface of the semiconductor substrate, but here is one example. show.

First, in the state (B), heat was applied at 1150°C for 2 hours in a humid oxygen stream, and SiO
'5- form. Then, using a known dry etching method, 5
Etch the i02 membrane until the bottom of the micropores is exposed. The purpose of this etching is to leave 5i02+Ig only on the regular wall, and even if some oxide film remains at the bottom of the micropore, etching is continued until Sj on the surface is exposed. Even if you do this, it will not interfere with later steps.

Next, as shown in Hvc, the entire structure was subjected to low pressure vapor phase epitaxy (LPC).
Si3N4 film'! j780 nm is formed. Here, the side wall of the micropore [which is broken and bonded] is not shown in the figure because it is integrated with the oxide film as an insulating film 2.

Next, as shown in (d) 19I, the polycrystalline Si layer is sputter-etched and ruptured alternately in several steps using the CVD method.

By doing this, the inside of the micropores is filled with Sl and the surface is filled with Sl. It can be flattened. Although the above-described shape of polycrystalline St 2 can be obtained by breaking, etching, and alternately greening, the same effect can be obtained by breaking and bonding by a known bias sputtering method. Note that the polycrystalline S1 filled inside the a pore is as follows.

Since there are some materials that will be used as part of the through-hole conductor in the future, it is necessary to dope the material with a dopant such as P to a high degree of 11xlO20/solder 3 or more.

It is more effective for this purpose to temporarily attach a thin layer of phosphor glass (PSG) to the entire surface before temporarily attaching polycrystalline St.

Next, the polycrystal 81 is removed, leaving only the micropores, and the shape shown in (e) is obtained. In addition, since the high temperature oxidation process is included in the subsequent steps, polycrystalline S+ thin Si3N4
It is preferable to slightly protect the polycrystalline S+ from oxidation with a film and then perform the above-mentioned etching in the shape of a wing (although this is not shown in the figure).

The state in (e) is the same as the first step in the conventional LSI manufacturing process, where a Si3N4 mask is formed for selective oxidation of Sl. It is already in a processed form. Therefore, by applying the conventional LSIN fabrication process (i-), elements are formed on the surface.

In this way, it is assumed that a part of the multilayer wiring is connected to a portion extending to the surface of the high-concentration polycrystalline St filled in the direct hole, and that this situation is not realized within the dotted line 606 in (). Continue the explanation below.

Next, in order to complete the through hole, processing is carried out from the back surface, but before that, the back surface of the substrate is reduced by 606 to reduce the overall thickness as shown in (H) K-. There are two reasons for this. One is to reduce the noise due to the thickness of the stacked chips and increase the overall stacking density, and the other is to make all the through holes as short as possible to make processing easier. This is also to shorten the machining time.

This method involves mechanically cutting the plane by 1vf, and then
There are two methods, including a method in which the entire mechanically damaged layer is removed by etching the St layer with a diameter of less than .mu.m, and a method in which a combination of mechanochemical polishing and etching is used, and any of these methods may be used.

The final finished St substrate thickness i-1 is preferably about 50 μm. If the thickness is at this level, when it is formed into a chip, it will not be significantly deformed due to distortion caused by LSI processing, and it will be easy to handle. The thickness of the thinned substrate must be within 5 μm and flat, and if necessary, monitor the thickness using infrared V-za interference, etc.) Adjust the thickness of the substrate one by one using ion silling, etc. Sir, fix it? Add.

Next, an At607 layer of about 1 μm thickness is formed on the back surface, and an opening with a size of 20 μm square is provided at a position opposite to the fine hole on the front surface. Due to the size of this opening.

A positioning error of approximately ±7 μm is acceptable. Next, I dry-etched Si as a mask on this person's t607,
The pores 608 are fully formed to a depth of about 35 μm and the bottoms of the aforementioned pores are exposed. (See Figure 6 C) A on the back side
At the same time, the residual oxide film and Si at the bottom of the micropore are removed.
The 3N4 film is sequentially removed by etching to completely expose the polycrystalline Si 605 filled in the micropores.

Next, a4i1VcCV D-8i (h609k, approximately 11 m) was deposited, and 610 14] mouths were provided at the bottom of the micropores.

This can be easily formed by, for example, using a Suto ion beam/micro drilling process.

Furthermore, in order to form solder bumps 611 and 612' in (N), a multilayer metal film such as Cr-Ni-Ag is deposited and patterned into a 5 to 10 μm square shape. Next, the entire solder layer is formed by plating.

Patterning is performed again in the same shape as the underlying multilayer metal film.

By heating above the melting point of the solder, (nu) [
As shown, the solder layer becomes spherical and the solder bumps 6ii and 6i
2 is formed 1. However, this heat treatment will be described later #t) @
It may also be done in a fusion process.

FIG. 7 shows how a large number of semiconductor chips formed according to the present invention are stacked and physically and electrically connected by solder pumps. Semiconductor chip 7 equivalent to Figure 6 (N)
1.17 lb, 71c, 71d, etc. are stacked so that the solder bumps on the surface and the manufacturing part face each other, and the solder bumps on the back surface of the upper layer chip and the solder bumps on the surface of the lower layer chip are bonded at the fused parts 72a, 72b. This is accomplished, for example, by positioning and stacking a large number of these chips while restricting all of their sides using a holding jig, etc., and applying pressure and heating one by one under vacuum. In this case, the height of the solder pump formed in a spherical shape is sufficiently larger than the sum of the side wall height of most of the through hole, the warpage of the chip, the unevenness of the multilayer distribution layer, etc. It is necessary to ensure that the volume of the solder forming the groove in the fused part is smaller than the volume of most of the through-hole, and to prevent the phenomenon of "extrusion" from occurring when pressure is applied.Integrated fusion. Each LS
The I chip has a multilayer wiring layer 73. ．． 73b etc., electrical interconnections are made through the upper and lower chips, other element groups of the same chip, or other fusion parts, and connections with the outside are made through a broken ceramic multilayer wiring board 74, for example. Connections are also made.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the through-hole structure is suitable for forming a chip stacked integrated circuit. can be formed. The through-hole structure formed by the present invention is
Since the through-hole conductor and the substrate are separated by a thick insulating film, and the length of the through hole can be shortened, the parasitic capacitance can be reduced accordingly, and speeding up is not hindered. In addition, in the example, highly doped polycrystalline Si was used for the conductor in all the through-holes, but for example, W'PMo
High melting point gold maple or silicide alloy? It is also possible to use According to the gist of the present invention, the semiconductor in which the through hole should be formed is not limited to St, but can also be applied to ■V compound semiconductors such as GaAa, IIIV compound semiconductors such as ZnS, etc., and these semiconductor materials Needless to say, the present invention can also be applied to composite semiconductor elements.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a conventional flip chip assembly, and FIG. 2 is a sectional view showing a chip stacking assembly to which the present invention is applied. FIG. 6 is a cross-sectional view of a confectionery to explain the conventional through-hole structure, and FIG. 4 is a cross-sectional view of an element showing an improved through-hole structure. FIG. 5 is a partial cross-sectional view of an element having a through-hole structure formed by applying the present invention, and FIG. FIG. 7 is a schematic cross-sectional view showing an example in which semiconductor chips having a through-hole structure formed according to the present invention are stacked and integrated. 50... Semiconductor substrate, 51... Through hole details, 52...
・Thick part of through hole, 56 ・Insulating film on inner wall of through hole, 54・
...Conductor in the through hole, 55.59...Ponding pad, 56.59...Solder bump. Figure 1 Figure 2 Figure 3 <In Figure 4-> If Figure 5 Figure 4 After

Claims (1)

[Claims] 1. In manufacturing a semiconductor integrated circuit chip having through holes for power supply or signal transmission, when forming all the through holes, the depth from one principal surface of the semiconductor wafer to another principal surface is A process of forming micropores that do not reach the surface, a process of coating the inner walls of the micropores with an insulating film, a process of further coating the inner walls of the micropores covered with the insulating film with a conductive material, or a process of completely conducting the micropores. In the step of filling the other main surface of the semiconductor wafer with a pore opposite to the micropore, a pore whose cross section is larger than the cross section of the micropore is formed such that the bottom reaches the micropore. a step of covering the inner wall of the pore with an insulating film; a step of removing a portion of the insulating film at the bottom of the pore so that only the conductor provided inside the pore is exposed; A method for manufacturing a laminated integrated semiconductor circuit device, which includes the step of fully depositing a conductor on the bottom. 2. Prior to forming a group of elements constituting a semiconductor integrated circuit,
Claim 1, characterized in that first, micropores are provided, then the entire element group is formed, and then the micropores are formed.
A method for manufacturing a laminated integrated semiconductor circuit device as described in Section 1. 6. The method for manufacturing a stacked integrated semiconductor circuit device according to claim 2, characterized in that after the formation of the element group, and prior to the formation of the pores, a step of thinning the semiconductor substrate is carried out.