JP2009259898A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP2009259898A
JP2009259898A JP2008104624A JP2008104624A JP2009259898A JP 2009259898 A JP2009259898 A JP 2009259898A JP 2008104624 A JP2008104624 A JP 2008104624A JP 2008104624 A JP2008104624 A JP 2008104624A JP 2009259898 A JP2009259898 A JP 2009259898A
Authority
JP
Japan
Prior art keywords
substrate
reference circuit
potential reference
region
circuit portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008104624A
Other languages
Japanese (ja)
Other versions
JP5092860B2 (en
Inventor
Koji Senda
厚慈 千田
Akira Yamada
山田　　明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2008104624A priority Critical patent/JP5092860B2/en
Publication of JP2009259898A publication Critical patent/JP2009259898A/en
Application granted granted Critical
Publication of JP5092860B2 publication Critical patent/JP5092860B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure that reduces a chip area and eliminates the need of an SOI substrate in a semiconductor device for composing an HVIC. <P>SOLUTION: A high-potential voltage reference circuit section HV and a low-potential reference circuit section LV are formed on first and second substrates 1, 2, respectively, for bonding and integrating. Then, periphery trenches 16, 26 are formed so that trenches 12, 22 for separating elements formed on the first and second substrates 1, 2 are surrounded. At regions 17, 27 outside the periphery trenches 16, 26, the backs of the first and second substrates 1, 2 are bonded, and an element 31 for transmitting signals is arranged at a region outside the periphery trenches 16, 26 in the first and second substrates 1, 2, thus restraining the area of two chips to that of one chip and reducing the chip area of the semiconductor device for composing the HVIC. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、モータ等の機器を駆動させるためのインバータ制御用の素子等に用いられる半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device used for an inverter control element for driving a device such as a motor, and a method for manufacturing the same.

モータ等の負荷を駆動させるためのインバータ制御用の素子等に用いられる半導体装置として、ＨＶＩＣ（High Voltage Integrated Circuit）がある。このＨＶＩＣにより、負荷を駆動するためのインバータ内に備えられるパワーデバイスを制御する。   As a semiconductor device used for an inverter control element or the like for driving a load such as a motor, there is an HVIC (High Voltage Integrated Circuit). The HVIC controls the power device provided in the inverter for driving the load.

このようなＨＶＩＣとして、特許文献１に開示されているものがある。具体的には、この特許公報１では、ＨＶＩＣを１チップにレイアウトすることにより、２チップ以上のＩＣを１つに実装したマルチチップにてＨＶＩＣを構成する場合と比較して、チップ小型化が図れるようにしている。
特開２００６−１４８０５８号公報 One such HVIC is disclosed in Patent Document 1. Specifically, in this patent publication 1, the chip size can be reduced by laying out the HVIC on one chip as compared with the case where the HVIC is configured by a multichip in which two or more chips are mounted on one chip. I am trying to figure it out.
JP 2006-148058 A

しかしながら、特許文献１に開示されているようにＨＶＩＣを１チップにレイアウトすると、チップ自体の面積が大きくなり、結果的に実装後の装置のサイズが大型化してしまうという問題がある。また、ウェハとしてＳＯＩ（Silicon on insulator）基板を用いなければならず、結果的にチップコストが高くなるという問題がある。   However, when the HVIC is laid out on one chip as disclosed in Patent Document 1, there is a problem that the area of the chip itself increases, resulting in an increase in the size of the device after mounting. In addition, an SOI (Silicon on insulator) substrate must be used as the wafer, resulting in a problem that the chip cost increases.

本発明は上記点に鑑みて、ＨＶＩＣを構成する半導体装置において、チップ面積を小さくでき、かつ、ＳＯＩ基板を用いなくてもよい構造を提供することを目的とする。   In view of the above points, an object of the present invention is to provide a structure in which a chip area can be reduced and an SOI substrate is not required in a semiconductor device constituting an HVIC.

上記目的を達成するため、請求項１に記載の発明では、高電位基準回路部（ＨＶ）が備えられる単層の半導体層にて構成された第１の基板（１）と、第１の基板（１）とは別チップであって、低電位基準回路部（ＬＶ）が備えられる単層の半導体層にて構成された第２の基板（２）と、を備え、第１の基板（１）には、高電位基準回路部（ＨＶ）が形成される素子領域（１３〜１５）と、該素子領域（１３〜１５）を囲み、かつ、該素子領域（１３〜１５）とその外部とを絶縁分離する外周トレンチ（１６）とが備えられていると共に、該第１の基板（１）のうち外周トレンチ（１６）よりも外側の領域（１７）に信号伝達用素子（３１）の少なくとも一部が備えられており、第２の基板（２）には、低電位基準回路部（ＬＶ）が形成される素子領域（２３〜２５）と、該素子領域（２３〜２５）を囲み、かつ、該素子領域（２３〜２５）とその外部とを絶縁分離する外周トレンチ（２６）とが備えられていると共に、該第２の基板（２）のうち外周トレンチ（２６）よりも外側の領域（２７）に信号伝達用素子（３１）の少なくとも一部が備えられており、第１の基板（１）と第２の基板（２）は、高電位基準回路部（ＨＶ）や低電位基準回路部（ＬＶ）が形成された表面側に対して反対側となる裏面同士が、外周領域（１７）に配置された接合部材（３０、３４）を介して接合させることで一体化されていることを特徴としている。   To achieve the above object, according to the first aspect of the present invention, a first substrate (1) constituted by a single semiconductor layer provided with a high potential reference circuit portion (HV), and a first substrate And a second substrate (2) configured by a single semiconductor layer provided with a low-potential reference circuit unit (LV). The first substrate (1 ) Includes an element region (13 to 15) where the high potential reference circuit portion (HV) is formed, the element region (13 to 15), and the element region (13 to 15) and the outside thereof. And an outer peripheral trench (16) for insulating and isolating at least a signal transmitting element (31) in a region (17) outside the outer peripheral trench (16) of the first substrate (1). A part of the low potential reference circuit portion (LV) is formed on the second substrate (2). A child region (23-25) and an outer peripheral trench (26) surrounding the element region (23-25) and isolating and separating the element region (23-25) and the outside thereof are provided. In the second substrate (2), at least a part of the signal transmission element (31) is provided in a region (27) outside the outer trench (26), and the first substrate (1) and As for the 2nd board | substrate (2), the back surfaces which become the other side with respect to the surface side in which the high potential reference circuit part (HV) and the low potential reference circuit part (LV) were formed are arrange | positioned in an outer peripheral area | region (17). It is characterized by being integrated by joining through the joined members (30, 34).

このように構成された半導体装置では、高電位基準回路部（ＨＶ）と低電位基準回路部（ＬＶ）とを第１、第２の基板（１、２）という別々の基板に形成し、これらを互いに貼り合せることで一体化している。このため、２チップ分を１チップ分の面積に抑えることが可能となり、ＨＶＩＣを構成する半導体装置のチップ面積を小さくすることが可能となる。   In the semiconductor device configured as described above, the high potential reference circuit portion (HV) and the low potential reference circuit portion (LV) are formed on separate substrates, the first and second substrates (1, 2). Are integrated by sticking together. For this reason, it is possible to suppress the area for two chips to the area for one chip, and it is possible to reduce the chip area of the semiconductor device constituting the HVIC.

例えば、請求項２に記載したように、接合部材を絶縁膜（３０）とし、信号伝達用素子（３１）として、絶縁膜（３０）を挟んで第１の基板（１）における外側の領域（１７）と第２の基板（２）における外側の領域（２７）とにより構成されるキャパシタを備えることができる。   For example, as described in claim 2, the bonding member is an insulating film (30), and the signal transmission element (31) is an outer region (first substrate (1)) with the insulating film (30) interposed therebetween ( 17) and a capacitor formed by the outer region (27) in the second substrate (2).

また、請求項３に記載したように、信号伝達用素子（３１）を縦型の半導体素子とすることにより、第１の基板（１）の裏面のうち外側の領域（１７）に配置された金属層（３３）を通じて電流を流すと共に、第２の基板（２）の裏面のうち外側の領域（２７）に配置された金属層（３３）を通じて電流を流すように構成し、かつ、接合部材を導電性接着剤（３４）とし、第１の基板（１）における外側の領域（１７）に備えられた金属層（３３）と第２の基板（２）における外側の領域（２７）に備えられた金属層（３３）とを電気的に接合することができる。   In addition, as described in claim 3, the signal transmission element (31) is a vertical semiconductor element, so that the signal transmission element (31) is disposed in the outer region (17) of the back surface of the first substrate (1). A current is passed through the metal layer (33), and a current is passed through the metal layer (33) disposed in the outer region (27) of the back surface of the second substrate (2). Is a conductive adhesive (34), and the metal layer (33) provided in the outer region (17) of the first substrate (1) and the outer region (27) of the second substrate (2) are provided. The formed metal layer (33) can be electrically joined.

上記のような半導体装置は、例えば請求項４に記載した製造方法により製造できる。具体的には、バルク基板もしくはエピ基板にて構成される半導体ウェハを用意する第１工程と、半導体ウェハの表面から所定深さのトレンチ（１０、２０）を形成すると共に、該トレンチ（１０、２０）内を絶縁膜（１１、２１）にて埋め込むことにより素子分離を行う素子分離用トレンチ（１２、２２）を形成すると共に、素子分離される素子領域（１３〜１５）を囲む外周トレンチ（１６、２６）を形成することで、該外周トレンチ（１６、２６）よりも外側の領域（１７、２７）を素子領域（１３〜１５）と分離する第２工程と、素子領域（１３〜１５）に対して、高電位基準回路部（ＨＶ）もしくは低電位基準回路部（ＬＶ）を構成する回路素子を形成する第３工程と、回路素子を形成した後の半導体ウェハを裏面から素子分離用トレンチ（１２、２２）および外周トレンチ（１６、２６）が露出するように研削する第４工程と、研削後の半導体ウェハをチップ単位に分割する第５工程と、第１〜第５工程を１つの半導体ウェハもしくは２つの半導体ウェハに対して行うことにより、高電位基準回路部（ＨＶ）が形成された第１の基板（１）および低電位基準回路部（ＬＶ）が形成された第２の基板（２）を形成する第６工程と、第１の基板（１）と第２の基板（２）とを、高電位基準回路部（ＨＶ）や低電位基準回路部（ＬＶ）が形成された表面側に対して反対側となる裏面同士で、該第１、第２の基板（２）における外側の領域（１７、２７）に接合部材（３０、３４）を配置することにより接合する第７工程と、を含んだ製造方法にて、上記した半導体装置を製造することができる。   The semiconductor device as described above can be manufactured, for example, by the manufacturing method described in claim 4. Specifically, a first step of preparing a semiconductor wafer composed of a bulk substrate or an epi substrate, a trench (10, 20) having a predetermined depth from the surface of the semiconductor wafer, and the trench (10, 20) An element isolation trench (12, 22) for element isolation is formed by embedding the inside with an insulating film (11, 21), and an outer peripheral trench (13-15) surrounding an element region (13-15) to be element isolated. 16, 26) to form a second step of separating the regions (17, 27) outside the peripheral trenches (16, 26) from the device regions (13-15), and the device regions (13-15). 3) for forming a circuit element constituting the high potential reference circuit portion (HV) or the low potential reference circuit portion (LV), and for separating the semiconductor wafer after forming the circuit element from the back surface. G 4th step of grinding so that the inches (12, 22) and the outer peripheral trenches (16, 26) are exposed, a fifth step of dividing the ground semiconductor wafer into chips, and a first to a fifth step. By performing the process on one semiconductor wafer or two semiconductor wafers, the first substrate (1) on which the high potential reference circuit portion (HV) is formed and the second substrate on which the low potential reference circuit portion (LV) is formed. The sixth step of forming the substrate (2) and the first substrate (1) and the second substrate (2) are formed into a high potential reference circuit portion (HV) and a low potential reference circuit portion (LV). The first and second substrates (2) are joined to each other by disposing the joining members (30, 34) in the outer regions (17, 27) on the back surfaces opposite to the front surface side. The above-described semiconductor device is manufactured by a manufacturing method including seven steps. It is possible.

なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。   In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、図中、同一符号を付してある。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

（第１実施形態）
本発明の第１実施形態について説明する。図１は、本実施形態にかかる半導体装置（ＨＶＩＣ）の断面図である。また、図２（ａ）、（ｂ）は、それぞれ、図１に示す半導体装置を上面側から見た時のレイアウト図と、裏面側から見た時のレイアウト図である。なお、図１は、図２（ａ）、（ｂ）のＡ−Ａ断面に相当する図である。 (First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view of a semiconductor device (HVIC) according to the present embodiment. 2A and 2B are a layout diagram when the semiconductor device shown in FIG. 1 is viewed from the upper surface side and a layout diagram when viewed from the rear surface side, respectively. FIG. 1 is a view corresponding to the AA cross section of FIGS. 2 (a) and 2 (b).

以下、これらの図を参照して、本実施形態の半導体装置の構成について説明する。なお、以下の説明では、図１の紙面上方を半導体装置の表面側、紙面下方を半導体装置の裏面側として説明する。   Hereinafter, the configuration of the semiconductor device of this embodiment will be described with reference to these drawings. In the following description, the upper side in FIG. 1 is described as the front side of the semiconductor device, and the lower side in FIG. 1 is described as the back side of the semiconductor device.

図１に示すように、本実施形態にかかる半導体装置は、共に単層の半導体層にて構成された第１の基板１と第２の基板２を貼り合せることにより構成されている。これら第１、第２の基板１、２は、例えばｎ型シリコンにて構成されており、ｎ型シリコンに各種素子が形成された構成とされている。   As shown in FIG. 1, the semiconductor device according to the present embodiment is configured by bonding a first substrate 1 and a second substrate 2 each formed of a single semiconductor layer. The first and second substrates 1 and 2 are made of, for example, n-type silicon, and various elements are formed on the n-type silicon.

第１の基板１は、高電位（後述する第１の電によりも高電位である第２の電位）が印加される回路素子が形成された高電位基準回路部ＨＶを構成するための基板として用いられる。第１の基板１には、第１の基板１の表裏を貫通するように形成されたトレンチ１０およびトレンチ１０内に配置された側壁酸化膜およびＰｏｌｙ−Ｓｉなどで構成された絶縁膜１１による素子分離用トレンチ１２が形成されており、図２（ａ）に示されるように素子分離用トレンチ１２によって複数の素子領域１３〜１５に分離されている。複数の素子領域１３〜１５には、高電位基準回路部ＨＶを構成する各種素子が形成され、例えば素子領域１３には高耐圧ＬＤＭＯＳ、素子領域１４にはＣＭＯＳ、素子領域１５にはバイポーラトランジスタが形成される。なお、ここでは高電位基準回路部ＨＶを構成する各種素子の一例を挙げたが、これら以外の素子を形成することもできる。   The first substrate 1 is a substrate for forming a high potential reference circuit portion HV on which a circuit element to which a high potential (a second potential that is higher than a first power described later) is applied is formed. Used. The first substrate 1 includes a trench 10 formed so as to penetrate the front and back of the first substrate 1, and an element made of an insulating film 11 composed of a sidewall oxide film disposed in the trench 10, Poly-Si, or the like. Isolation trenches 12 are formed, which are separated into a plurality of element regions 13 to 15 by the element isolation trenches 12 as shown in FIG. Various elements constituting the high potential reference circuit unit HV are formed in the plurality of element regions 13 to 15. For example, a high breakdown voltage LDMOS is formed in the element region 13, a CMOS is formed in the element region 14, and a bipolar transistor is formed in the element region 15. It is formed. Although an example of various elements constituting the high potential reference circuit portion HV has been described here, other elements may be formed.

一方、第２の基板２は、低電位（第１の電位）が印加される回路素子が形成された低電位基準回路部ＬＶを構成するための基板として用いられる。第２の基板２には、第２の基板２の表裏を貫通するように形成されたトレンチ２０およびトレンチ２０内に配置された側壁酸化膜およびＰｏｌｙ−Ｓｉなどで構成された絶縁膜２１による素子分離用トレンチ２２が形成されており、図２（ｂ）に示されるように素子分離用トレンチ２２によって複数の素子領域２３〜２５に分離されている。複数の素子領域２３〜２５には、低電位基準回路部ＬＶを構成する各種素子が形成され、例えば素子領域２３には高耐圧ＬＤＭＯＳ、素子領域２４にはＣＭＯＳ、素子領域２５にはバイポーラトランジスタが形成される。なお、ここでは低電位基準回路部ＬＶを構成する各種素子の一例を挙げたが、これら以外の素子を形成することもできる。   On the other hand, the second substrate 2 is used as a substrate for constituting a low potential reference circuit portion LV on which a circuit element to which a low potential (first potential) is applied is formed. The second substrate 2 includes a trench 20 formed so as to penetrate the front and back of the second substrate 2, an element made of an insulating film 21 made of a sidewall oxide film disposed in the trench 20, Poly-Si, or the like. Isolation trenches 22 are formed, which are separated into a plurality of element regions 23 to 25 by the element isolation trenches 22 as shown in FIG. Various elements constituting the low potential reference circuit portion LV are formed in the plurality of element regions 23 to 25. For example, a high breakdown voltage LDMOS is formed in the element region 23, a CMOS is formed in the element region 24, and a bipolar transistor is formed in the element region 25. It is formed. Although an example of various elements constituting the low potential reference circuit portion LV has been described here, elements other than these can also be formed.

また、第１、第２の基板１、２に形成された素子分離用トレンチ１２、２２を囲むように、外周トレンチ１６、２６が形成されている。外周トレンチ１６、２６も素子分離用トレンチ１２、２２と同様の構成とされている。この外周トレンチ１６、２６よりも外側の領域１７、２７において、第１、第２の基板１、２が接合部材に相当する絶縁膜３０を介して裏面同士（各種素子が形成された表面と反対側の面同士）で貼り合わされている。この貼り合せは、例えば第１の基板１と第２の基板２のそれぞれに絶縁膜３０として酸化膜を形成しておき、酸化膜同士を接合することにって行われている。   Further, outer peripheral trenches 16 and 26 are formed so as to surround the element isolation trenches 12 and 22 formed in the first and second substrates 1 and 2. The peripheral trenches 16 and 26 have the same configuration as the element isolation trenches 12 and 22. In the regions 17 and 27 outside the outer peripheral trenches 16 and 26, the first and second substrates 1 and 2 are opposite to each other through the insulating film 30 corresponding to a bonding member (opposite to the surface on which various elements are formed). Side surfaces). This bonding is performed, for example, by forming an oxide film as the insulating film 30 on each of the first substrate 1 and the second substrate 2 and bonding the oxide films together.

このように第１、第２の基板１、２における外周トレンチ１６、２６よりも外側の領域に、絶縁膜３０を挟み込むように配置されたｎ型シリコンによるキャパシタにて構成される信号伝達用素子３１が構成されている。すなわち、第１の基板１と第２の基板２にそれぞれキャパシタの一部が備えられ、第１、第２の基板１、２が貼り合わされたことでキャパシタが構成されている。この信号伝達用素子３１を構成するキャパシタは、高電位基準回路部ＨＶと低電位基準回路部ＬＶとのレベルシフトの際の信号伝達を行うために用いられる。すなわち、立ち上がりが急峻な信号（例えば小信号）を低電位基準回路部ＬＶ側から入力することにより、信号伝達用素子３１を構成するキャパシタを通過して高電位基準回路部ＨＶに信号伝達が行われるようにしている。   In this way, the signal transmission element composed of the n-type silicon capacitor disposed so as to sandwich the insulating film 30 in the region outside the outer peripheral trenches 16 and 26 in the first and second substrates 1 and 2. 31 is configured. That is, a part of the capacitor is provided on each of the first substrate 1 and the second substrate 2, and the first and second substrates 1 and 2 are bonded together to form a capacitor. The capacitor constituting the signal transmission element 31 is used for signal transmission at the time of level shift between the high potential reference circuit unit HV and the low potential reference circuit unit LV. That is, when a signal having a steep rise (for example, a small signal) is input from the low potential reference circuit unit LV side, the signal is transmitted to the high potential reference circuit unit HV through the capacitor constituting the signal transmission element 31. It is supposed to be.

そして、このように第１、第２の基板１、２を貼り合せた構造において、絶縁膜３０を外周トレンチ１６、２６よりも外側にだけ配置することで、第１の基板１のうち高電位基準回路部ＨＶが形成された領域と第２の基板２のうち低電位基準回路部ＬＶが形成された領域との間に間隙３２が形成されるようにしている。この間隙３２内は空気であっても構わないが、高電位基準回路部ＨＶで使用される高電圧が低電位基準回路部ＬＶに影響を与えないようにするために、低誘電率であることが望ましく、本実施形態では真空としている。   In the structure in which the first and second substrates 1 and 2 are bonded together as described above, the insulating film 30 is disposed only outside the outer peripheral trenches 16 and 26, so that the high potential of the first substrate 1 is increased. A gap 32 is formed between the region where the reference circuit unit HV is formed and the region where the low potential reference circuit unit LV is formed in the second substrate 2. The gap 32 may be air, but has a low dielectric constant so that the high voltage used in the high potential reference circuit unit HV does not affect the low potential reference circuit unit LV. In this embodiment, a vacuum is used.

以上のようにして本実施形態にかかる半導体装置が構成されている。このように構成された半導体装置では、高電位基準回路部ＨＶと低電位基準回路部ＬＶとを第１、第２の基板１、２という別々の基板に形成し、これらを互いに貼り合せることで一体化している。このため、２チップ分を１チップ分の面積に抑えることが可能となり、ＨＶＩＣを構成する半導体装置のチップ面積を小さくすることが可能となる。   The semiconductor device according to the present embodiment is configured as described above. In the semiconductor device configured as described above, the high potential reference circuit unit HV and the low potential reference circuit unit LV are formed on separate substrates, the first and second substrates 1 and 2, and these are bonded to each other. It is integrated. For this reason, it is possible to suppress the area for two chips to the area for one chip, and it is possible to reduce the chip area of the semiconductor device constituting the HVIC.

続いて、上記のように構成された本実施形態にかかる半導体装置の製造方法について、図３を参照して説明する。   Next, a method for manufacturing the semiconductor device according to the present embodiment configured as described above will be described with reference to FIG.

図３は、図１に示す半導体装置の製造工程を示した断面図である。まず、図３（ａ）に示すように、第１の基板１や第２の基板２を形成するためのｎ型シリコンなどで構成された半導体ウェハを用意する。このとき用意する半導体ウェハとしては、シリコンインゴットを切り出して作製したバルク基板であっても良いし、バルク基板上にｎ型シリコン層をエピタキシャル成長させたエピ基板であっても良い。   FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. First, as shown in FIG. 3A, a semiconductor wafer made of n-type silicon or the like for forming the first substrate 1 and the second substrate 2 is prepared. The semiconductor wafer prepared at this time may be a bulk substrate manufactured by cutting out a silicon ingot, or may be an epi substrate obtained by epitaxially growing an n-type silicon layer on the bulk substrate.

次に、図３（ｂ）に示すように、半導体ウェハのうち、第１、第２の基板１、２における素子分離用トレンチ１２、２２および外周トレンチ１６、２６の形成予定領域に、トレンチ１０、２０を形成すると共に、トレンチ１０、２０内を熱酸化して側壁酸化膜を形成したのち、トレンチ１０、２０内をＰｏｌｙ−Ｓｉにて埋め込み、さらにＰｏｌｙ−Ｓｉをエッチバックすることでトレンチ１０、２０内にのみ残す。これにより、素子分離用トレンチ１２、２２および外周トレンチ１６、２６が形成される。   Next, as shown in FIG. 3B, in the semiconductor wafer, the trench 10 is formed in the region where the element isolation trenches 12 and 22 and the outer trenches 16 and 26 are to be formed in the first and second substrates 1 and 2. , 20 are formed, and the trenches 10 and 20 are thermally oxidized to form a sidewall oxide film. Then, the trenches 10 and 20 are filled with Poly-Si, and the Poly-Si is etched back to thereby etch the trench 10. , 20 only. Thus, element isolation trenches 12 and 22 and outer peripheral trenches 16 and 26 are formed.

さらに、半導体ウェハのうち、第１、第２基板１、２における素子領域１３〜１４にデバイス形成プロセスを実施することにより、高耐圧ＬＤＭＯＳやＣＭＯＳおよびバイポーラトランジスタ等の高電位基準回路部ＨＶや低電位基準回路部ＬＶを構成する各種素子を作り込む。また、素子分離用トレンチ１２、２２や外周トレンチ１６、２６を研磨ストッッパーとして、これらが露出するまで半導体ウェハの裏面を研削することで、素子分離用トレンチ１２、２２や外周トレンチ１６、２６により半導体ウェハ内部において各素子領域１３〜１５、２３〜２５および外側の領域１７、２７を完全に絶縁分離させる。そして、第１、第２の基板１、２を形成するための半導体ウェハの裏面それぞれに酸化膜などで構成される絶縁膜３０を形成したのち、パターニングすることで、絶縁膜３０を外周トレンチ１６、２６の外側にのみ残す。このとき、絶縁膜３０をＣＶＤ法にて形成するようにすれば、第１、第２の基板１、２を形成するための半導体ウェハそれぞれに１μｍ以上の厚さで絶縁膜３０を形成することができるため、間隙３２を確保することが可能となる。   Further, by performing a device formation process on the element regions 13 to 14 in the first and second substrates 1 and 2 of the semiconductor wafer, a high potential reference circuit unit HV such as a high breakdown voltage LDMOS, a CMOS, and a bipolar transistor is reduced. Various elements constituting the potential reference circuit unit LV are formed. Further, by using the element isolation trenches 12 and 22 and the outer peripheral trenches 16 and 26 as polishing stoppers, the semiconductor wafer is ground by grinding the back surface of the semiconductor wafer until they are exposed. The element regions 13 to 15 and 23 to 25 and the outer regions 17 and 27 are completely insulated and separated inside the wafer. And after forming the insulating film 30 comprised by an oxide film etc. in each back surface of the semiconductor wafer for forming the 1st, 2nd board | substrates 1 and 2, by patterning, the insulating film 30 is made into the outer periphery trench 16. , 26 only outside. At this time, if the insulating film 30 is formed by the CVD method, the insulating film 30 is formed with a thickness of 1 μm or more on each of the semiconductor wafers for forming the first and second substrates 1 and 2. Therefore, the gap 32 can be secured.

その後、各種素子を作り込んだ半導体ウェハをチップ単位に分割して第１、第２の基板１、２を形成したのち、真空装置内に第１、第２の基板１、２を配置し、第１、第２の基板１、２の裏面同士を向かい合わせ、絶縁膜３０を介してこれらを貼り合せる。例えば、絶縁膜３０を酸化膜で構成すれば、酸化膜同士を直接接合させることができるため、容易に第１、第２の基板１、２を貼り合せることが可能となる。これにより、図１に示した半導体装置が完成する。   Then, after dividing the semiconductor wafer in which various elements are formed into chip units to form the first and second substrates 1 and 2, the first and second substrates 1 and 2 are arranged in a vacuum apparatus, The back surfaces of the first and second substrates 1 and 2 are faced to each other, and these are bonded together via an insulating film 30. For example, if the insulating film 30 is composed of an oxide film, the oxide films can be directly bonded to each other, so that the first and second substrates 1 and 2 can be easily bonded together. Thereby, the semiconductor device shown in FIG. 1 is completed.

このようにして構成された半導体装置は、例えばリードフレームに対して電気的に接続されたのち、リードフレームの一部と共に樹脂封止されることにより、樹脂封止型半導体装置とされる。図４（ａ）は、図１に示す半導体装置を含む樹脂封止型半導体装置の一例を示した断面図、図４（ｂ）は、図４（ａ）に示す樹脂封止型半導体装置の上面レイアウトの概略図である。   The semiconductor device configured as described above is, for example, electrically connected to a lead frame and then resin-sealed together with a part of the lead frame, thereby forming a resin-encapsulated semiconductor device. 4A is a cross-sectional view showing an example of a resin-encapsulated semiconductor device including the semiconductor device shown in FIG. 1, and FIG. 4B is a diagram of the resin-encapsulated semiconductor device shown in FIG. It is the schematic of an upper surface layout.

図４（ａ）に示されるように、第１の基板１における所望部位がボンディングワイヤ４０を介してリードフレーム４１に電気的に接続されていると共に、第２の基板２における所望部位がはんだボール４２を介してリードフレーム４１に電気的に接続されている。そして、リードフレーム４１の一部と共に、半導体装置およびボンディングワイヤ４０やはんだボール４２を樹脂部４３にて封止することにより、樹脂封止型半導体装置が構成されている。このような構成とすることで、重ね合わせて貼り合せた第１の基板１と第２の基板２のそれぞれの所望部位をリードフレーム４１に電気的に接続することが可能である。   As shown in FIG. 4A, the desired portion of the first substrate 1 is electrically connected to the lead frame 41 via the bonding wire 40, and the desired portion of the second substrate 2 is a solder ball. It is electrically connected to the lead frame 41 via 42. A resin-encapsulated semiconductor device is configured by sealing the semiconductor device and the bonding wires 40 and solder balls 42 together with a part of the lead frame 41 with a resin portion 43. By adopting such a configuration, it is possible to electrically connect each desired portion of the first substrate 1 and the second substrate 2 that are overlapped and bonded to the lead frame 41.

（第２実施形態）
本発明の第２実施形態について説明する。本実施形態の半導体装置は、第１実施形態に対して外周トレンチ１６、２６の外側に備えるレベルシフトの際の信号伝達を行うため信号伝達用素子３１として、キャパシタではなく他の素子を備えた点が異なっており、その他に関しては第１実施形態と同様であるため、第１実施形態と異なる部分についてのみ説明する。 (Second Embodiment)
A second embodiment of the present invention will be described. The semiconductor device of this embodiment includes other elements instead of capacitors as the signal transmission element 31 for performing signal transmission at the time of level shift provided outside the outer peripheral trenches 16 and 26 with respect to the first embodiment. Since the points are different and the other points are the same as those of the first embodiment, only the parts different from the first embodiment will be described.

図５は、本実施形態にかかる半導体装置の断面図である。本実施形態では、外周トレンチ１６、２６の外側に備える信号伝達用素子３１として、キャパシタに代えて他の縦型構造の素子を備えている。信号伝達用素子３１は、第１、第２の基板１、２のそれぞれに備えられ、各信号伝達用素子３１が裏面に形成された電極もしくは配線パターンを構成する金属層３３が導電性接着剤３４を介して電気的に接続された構造とされている。このような信号伝達用素子３１としては、例えば縦型のＤＭＯＳ等を挙げることができる。   FIG. 5 is a cross-sectional view of the semiconductor device according to the present embodiment. In the present embodiment, as the signal transmission element 31 provided outside the outer peripheral trenches 16 and 26, an element having another vertical structure is provided instead of the capacitor. The signal transmission element 31 is provided on each of the first and second substrates 1 and 2, and each of the signal transmission elements 31 is formed on the back surface. The metal layer 33 constituting the wiring pattern is a conductive adhesive. It is configured to be electrically connected through 34. Examples of such a signal transmission element 31 include a vertical DMOS.

このように、レベルシフトの際の信号伝達を行うための信号伝達用素子３１として、縦型のＬＤＭＯＳ等の縦型半導体素子を形成することもできる。このような構成としても、第１実施形態と同様の効果を得ることができる。   As described above, a vertical semiconductor element such as a vertical LDMOS can be formed as the signal transmission element 31 for transmitting a signal at the time of level shift. Even with such a configuration, the same effect as in the first embodiment can be obtained.

なお、このような構造とする場合、上述した第１実施形態の半導体装置の製造方法に対して、半導体ウェハの裏面に絶縁膜３０を形成する工程に代えて、金属層３３の形成およびパターニング工程を行い、さらにパターニングした金属層３３の表面に導電性接着剤３４を塗布し、これらを貼り合せるようにすれば良い。また、金属層３３とのオーミックを取るためには下地となる半導体ウェハ裏面側の不純物濃度が濃い必要があるため、好ましくは金属層３３を形成する前に研磨後の半導体ウェハの裏面にｎ型もしくはｐ型不純物をドーピングしておくと良い。   In the case of such a structure, instead of the step of forming the insulating film 30 on the back surface of the semiconductor wafer, the formation and patterning steps of the metal layer 33 with respect to the semiconductor device manufacturing method of the first embodiment described above. Then, the conductive adhesive 34 may be applied to the surface of the patterned metal layer 33 and bonded together. Further, in order to take ohmic contact with the metal layer 33, it is necessary that the impurity concentration on the back surface side of the semiconductor wafer as a base is high, and therefore, preferably n-type is formed on the back surface of the semiconductor wafer after polishing before the metal layer 33 is formed. Alternatively, p-type impurities may be doped.

（他の実施形態）
上記第１実施形態では、信号伝達用素子３１をキャパシタとする場合において、絶縁膜３０を介して第１、第２の基板１、２が貼り合わされるようにしたが、絶縁膜３０同士を導電性接着剤３４にて貼り合せるようにしても良い。 (Other embodiments)
In the first embodiment, when the signal transmission element 31 is a capacitor, the first and second substrates 1 and 2 are bonded to each other via the insulating film 30, but the insulating films 30 are electrically connected to each other. Alternatively, the adhesive may be bonded with the adhesive 34.

また、第１実施形態では、間隙３２を形成するために絶縁膜３０の一部を除去するようにしているが、間隙３２を形成しなくても第１、第２の基板１、２の絶縁を確保できるため、絶縁膜３０を除去しなくても構わない。ただし、これらの間に寄生容量が形成されることになるため、寄生容量を通じて高電位基準回路部ＨＶで使用される高電圧が低電位基準回路部ＬＶに影響を与えることが懸念される。このため、間隙３２を形成するために絶縁膜３０の一部を除去するようにした方が好ましい。   In the first embodiment, a part of the insulating film 30 is removed in order to form the gap 32. However, the insulation of the first and second substrates 1 and 2 is not required even if the gap 32 is not formed. Therefore, the insulating film 30 may not be removed. However, since a parasitic capacitance is formed between them, there is a concern that a high voltage used in the high potential reference circuit unit HV through the parasitic capacitance affects the low potential reference circuit unit LV. For this reason, it is preferable to remove a part of the insulating film 30 in order to form the gap 32.

本発明の第１実施形態にかかる半導体装置（ＨＶＩＣ）の断面図である。1 is a cross-sectional view of a semiconductor device (HVIC) according to a first embodiment of the present invention. （ａ）、（ｂ）は、それぞれ、図１に示す半導体装置を上面側から見た時のレイアウト図と、裏面側から見た時のレイアウト図である。1A and 1B are a layout diagram when the semiconductor device shown in FIG. 1 is viewed from the top surface side and a layout diagram when the semiconductor device is viewed from the back surface side, respectively. 図１に示す半導体装置の製造工程を示した断面図である。FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. （ａ）は、図１に示す半導体装置を含む樹脂封止型半導体装置の一例を示した断面図、（ｂ）は、（ａ）に示す樹脂封止型半導体装置の上面レイアウトの概略図である。(A) is sectional drawing which showed an example of the resin sealing type semiconductor device containing the semiconductor device shown in FIG. 1, (b) is the schematic of the upper surface layout of the resin sealing type semiconductor device shown in (a). is there. 本発明の第２実施形態にかかる半導体装置（ＨＶＩＣ）の断面図である。It is sectional drawing of the semiconductor device (HVIC) concerning 2nd Embodiment of this invention.

符号の説明Explanation of symbols

１、２ 第１、第２の基板
１２、２２ 素子分離用トレンチ
１６ 外周トレンチ
１７ 外側の領域
３０ 絶縁膜
３１ 信号伝達用素子
３２ 間隙
３３ 金属層
３４ 導電性接着剤
４０ ボンディングワイヤ
４１ リードフレーム
４２ はんだボール
４３ 樹脂部
ＨＶ 高電位基準回路部
ＬＶ 低電位基準回路部 DESCRIPTION OF SYMBOLS 1, 2 1st, 2nd board | substrates 12, 22 Element isolation trench 16 Outer periphery trench 17 Outside area | region 30 Insulating film 31 Signal transmission element 32 Gap | interval 33 Metal layer 34 Conductive adhesive 40 Bonding wire 41 Lead frame 42 Solder Ball 43 Resin part HV High potential reference circuit part LV Low potential reference circuit part

Claims (4)

第１の電位が印加される回路素子を含む低電位基準回路部（ＬＶ）と、前記第１の電位よりも高電位である第２の電位が印加される回路素子を含む高電位基準回路部（ＨＶ）と、前記低電位基準回路部（ＬＶ）と前記高電位基準回路部（ＨＶ）との間でのレベルシフトの際の信号伝達を行うための信号伝達用素子（３１）が備えられたレベルシフト素子形成部とが形成されてなる半導体装置において、
前記高電位基準回路部（ＨＶ）が備えられる単層の半導体層にて構成された第１の基板（１）と、
前記第１の基板（１）とは別チップであって、前記低電位基準回路部（ＬＶ）が備えられる単層の半導体層にて構成された第２の基板（２）と、を備え、
前記第１の基板（１）には、前記高電位基準回路部（ＨＶ）が形成される素子領域（１３〜１５）と、該素子領域（１３〜１５）を囲み、かつ、該素子領域（１３〜１５）とその外部とを絶縁分離する外周トレンチ（１６）とが備えられていると共に、該第１の基板（１）のうち前記外周トレンチ（１６）よりも外側の領域（１７）に前記信号伝達用素子（３１）の少なくとも一部が備えられており、
前記第２の基板（２）には、前記低電位基準回路部（ＬＶ）が形成される素子領域（２３〜２５）と、該素子領域（２３〜２５）を囲み、かつ、該素子領域（２３〜２５）とその外部とを絶縁分離する外周トレンチ（２６）とが備えられていると共に、該第２の基板（２）のうち前記外周トレンチ（２６）よりも外側の領域（２７）に前記信号伝達用素子（３１）の少なくとも一部が備えられており、
前記第１の基板（１）と前記第２の基板（２）は、前記高電位基準回路部（ＨＶ）や前記低電位基準回路部（ＬＶ）が形成された表面側に対して反対側となる裏面同士が、前記外周領域（１７）に配置された接合部材（３０、３４）を介して接合させることで一体化されていることを特徴とする半導体装置。 A low potential reference circuit portion (LV) including a circuit element to which a first potential is applied, and a high potential reference circuit portion including a circuit element to which a second potential that is higher than the first potential is applied. (HV) and a signal transmission element (31) for performing signal transmission at the time of level shift between the low potential reference circuit unit (LV) and the high potential reference circuit unit (HV). In the semiconductor device in which the level shift element forming portion is formed,
A first substrate (1) composed of a single semiconductor layer provided with the high potential reference circuit portion (HV);
A second substrate (2), which is a chip different from the first substrate (1), and is composed of a single semiconductor layer provided with the low potential reference circuit portion (LV),
The first substrate (1) surrounds the element region (13 to 15) in which the high potential reference circuit portion (HV) is formed and the element region (13 to 15), and the element region ( 13-15) and an outer peripheral trench (16) that insulates and isolates the outside from the outside, and a region (17) outside the outer peripheral trench (16) of the first substrate (1). At least a portion of the signal transmission element (31) is provided;
The second substrate (2) encloses the element region (23-25) in which the low potential reference circuit portion (LV) is formed and the element region (23-25), and the element region ( 23 to 25) and an outer peripheral trench (26) that insulates and separates the outside from the outside, and a region (27) outside the outer peripheral trench (26) of the second substrate (2). At least a portion of the signal transmission element (31) is provided;
The first substrate (1) and the second substrate (2) are opposite to the surface side on which the high potential reference circuit portion (HV) and the low potential reference circuit portion (LV) are formed. The back surfaces to be integrated with each other by bonding them through the bonding members (30, 34) disposed in the outer peripheral region (17). 前記接合部材は絶縁膜（３０）であり、前記信号伝達用素子（３１）は、前記絶縁膜（３０）を挟んで前記第１の基板（１）における前記外側の領域（１７）と前記第２の基板（２）における前記外側の領域（２７）とにより構成されるキャパシタであることを特徴とする請求項１に記載の半導体装置。   The bonding member is an insulating film (30), and the signal transmission element (31) includes the outer region (17) and the first region of the first substrate (1) across the insulating film (30). The semiconductor device according to claim 1, wherein the semiconductor device is a capacitor constituted by the outer region (27) of the two substrates (2). 前記信号伝達用素子（３１）は、縦型の半導体素子であり、前記第１の基板（１）の裏面のうち前記外側の領域（１７）に配置された金属層（３３）を通じて電流を流すと共に、前記第２の基板（２）の裏面のうち前記外側の領域（２７）に配置された金属層（３３）を通じて電流を流すように構成され、
前記接合部材は導電性接着剤（３４）であり、前記第１の基板（１）における前記外側の領域（１７）に備えられた前記金属層（３３）と前記第２の基板（２）における前記外側の領域（２７）に備えられた前記金属層（３３）とを電気的に接合していることを特徴とする請求項１に記載の半導体装置。 The signal transmission element (31) is a vertical semiconductor element, and allows a current to flow through a metal layer (33) disposed in the outer region (17) of the back surface of the first substrate (1). And a current is passed through the metal layer (33) disposed in the outer region (27) of the back surface of the second substrate (2).
The bonding member is a conductive adhesive (34), and the metal layer (33) and the second substrate (2) provided in the outer region (17) of the first substrate (1). The semiconductor device according to claim 1, wherein the metal layer (33) provided in the outer region (27) is electrically joined. 第１の電位が印加される回路素子を含む低電位基準回路部（ＬＶ）と、前記第１の電位よりも高電位である第２の電位が印加される回路素子を含む高電位基準回路部（ＨＶ）と、前記低電位基準回路部（ＬＶ）と前記高電位基準回路部（ＨＶ）との間でのレベルシフトの際の信号伝達を行うための信号伝達用素子（３１）が備えられたレベルシフト素子形成部とが形成されてなる半導体装置の製造方法において、
バルク基板もしくはエピ基板にて構成される半導体ウェハを用意する第１工程と、
前記半導体ウェハの表面から所定深さのトレンチ（１０、２０）を形成すると共に、該トレンチ（１０、２０）内を絶縁膜（１１、２１）にて埋め込むことにより素子分離を行う素子分離用トレンチ（１２、２２）を形成すると共に、素子分離される素子領域（１３〜１５）を囲む外周トレンチ（１６、２６）を形成することで、該外周トレンチ（１６、２６）よりも外側の領域（１７、２７）を前記素子領域（１３〜１５）と分離する第２工程と、
前記素子領域（１３〜１５）に対して、前記高電位基準回路部（ＨＶ）もしくは前記低電位基準回路部（ＬＶ）を構成する回路素子を形成する第３工程と、
前記回路素子を形成した後の前記半導体ウェハを裏面から前記素子分離用トレンチ（１２、２２）および前記外周トレンチ（１６、２６）が露出するように研削する第４工程と、
研削後の前記半導体ウェハをチップ単位に分割する第５工程と、
前記第１〜第５工程を１つの半導体ウェハもしくは２つの半導体ウェハに対して行うことにより、前記高電位基準回路部（ＨＶ）が形成された第１の基板（１）および前記低電位基準回路部（ＬＶ）が形成された第２の基板（２）を形成する第６工程と、
前記第１の基板（１）と前記第２の基板（２）とを、前記高電位基準回路部（ＨＶ）や前記低電位基準回路部（ＬＶ）が形成された表面側に対して反対側となる裏面同士で、該第１、第２の基板（２）における前記外側の領域（１７、２７）に接合部材（３０、３４）を配置することにより接合する第７工程と、を含んでいることを特徴とする半導体装置の製造方法。 A low potential reference circuit portion (LV) including a circuit element to which a first potential is applied, and a high potential reference circuit portion including a circuit element to which a second potential that is higher than the first potential is applied. (HV) and a signal transmission element (31) for performing signal transmission at the time of level shift between the low potential reference circuit unit (LV) and the high potential reference circuit unit (HV). In the method of manufacturing a semiconductor device in which the level shift element forming portion is formed,
A first step of preparing a semiconductor wafer composed of a bulk substrate or an epi substrate;
A trench for element isolation is formed by forming trenches (10, 20) having a predetermined depth from the surface of the semiconductor wafer and embedding the trenches (10, 20) with insulating films (11, 21). (12, 22) and forming outer peripheral trenches (16, 26) surrounding the element regions (13-15) to be isolated from each other, a region outside the outer peripheral trenches (16, 26) ( 17, 27) separating the element regions (13 to 15);
A third step of forming circuit elements constituting the high potential reference circuit portion (HV) or the low potential reference circuit portion (LV) with respect to the element regions (13 to 15);
A fourth step of grinding the semiconductor wafer after forming the circuit elements so that the element isolation trenches (12, 22) and the outer peripheral trenches (16, 26) are exposed from the back surface;
A fifth step of dividing the semiconductor wafer after grinding into chips;
The first substrate (1) on which the high potential reference circuit portion (HV) is formed and the low potential reference circuit by performing the first to fifth steps on one semiconductor wafer or two semiconductor wafers. A sixth step of forming the second substrate (2) on which the portion (LV) is formed;
The first substrate (1) and the second substrate (2) are opposite to the surface side on which the high potential reference circuit portion (HV) and the low potential reference circuit portion (LV) are formed. A seventh step of bonding the back surfaces of the first and second substrates (2) by disposing the bonding members (30, 34) in the outer regions (17, 27). A method for manufacturing a semiconductor device, comprising:
JP2008104624A 2008-04-14 2008-04-14 Semiconductor device and manufacturing method thereof Expired - Fee Related JP5092860B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008104624A JP5092860B2 (en) 2008-04-14 2008-04-14 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008104624A JP5092860B2 (en) 2008-04-14 2008-04-14 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2009259898A true JP2009259898A (en) 2009-11-05
JP5092860B2 JP5092860B2 (en) 2012-12-05

Family

ID=41386984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008104624A Expired - Fee Related JP5092860B2 (en) 2008-04-14 2008-04-14 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP5092860B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013011528A (en) * 2011-06-29 2013-01-17 Denso Corp Rotation detector

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05190770A (en) * 1992-01-09 1993-07-30 Fujitsu Ltd Semiconductor device
JPH1032284A (en) * 1996-07-17 1998-02-03 Sanyo Electric Co Ltd Semiconductor device
JP2002270756A (en) * 2001-03-08 2002-09-20 Hitachi Ltd Semiconductor device and communication terminal equipment using the same
JP2007059769A (en) * 2005-08-26 2007-03-08 Honda Motor Co Ltd Method of manufacturing semiconductor device, semiconductor device and wafer
JP2007221078A (en) * 2006-02-20 2007-08-30 Denso Corp Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05190770A (en) * 1992-01-09 1993-07-30 Fujitsu Ltd Semiconductor device
JPH1032284A (en) * 1996-07-17 1998-02-03 Sanyo Electric Co Ltd Semiconductor device
JP2002270756A (en) * 2001-03-08 2002-09-20 Hitachi Ltd Semiconductor device and communication terminal equipment using the same
JP2007059769A (en) * 2005-08-26 2007-03-08 Honda Motor Co Ltd Method of manufacturing semiconductor device, semiconductor device and wafer
JP2007221078A (en) * 2006-02-20 2007-08-30 Denso Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013011528A (en) * 2011-06-29 2013-01-17 Denso Corp Rotation detector

Also Published As

Publication number Publication date
JP5092860B2 (en) 2012-12-05

Similar Documents

Publication Publication Date Title
JP5217348B2 (en) Semiconductor device
JP4858290B2 (en) Load drive device
JP5353016B2 (en) Semiconductor device
US7829971B2 (en) Semiconductor apparatus
JP2011071147A (en) Semiconductor device and method of manufacturing the same
JP2011103429A (en) Method for manufacturing semiconductor device, semiconductor device, and multilayer substrate with the semiconductor device built in
JP4438859B2 (en) Semiconductor device
JP2526786B2 (en) Semiconductor device and manufacturing method thereof
JP4600563B2 (en) Semiconductor device and manufacturing method thereof
US20130285228A1 (en) Glass Frit Wafer Bond Protective Structure
TWI520330B (en) Semiconductor device
JP2012238741A (en) Semiconductor device and manufacturing method for the same
JP2007165693A (en) Semiconductor device
JP5092860B2 (en) Semiconductor device and manufacturing method thereof
JP2979554B2 (en) Method for manufacturing semiconductor device
JP4696152B2 (en) Semiconductor device manufacturing method and semiconductor device
JP2009277851A (en) Semiconductor device, method of manufacturing the same, and power amplifier element
JP4508290B2 (en) Semiconductor device
JP4479823B2 (en) Semiconductor device
JP4508289B2 (en) Semiconductor device
JP2009212438A (en) Semiconductor device, and method of manufacturing the same
JP2010010264A (en) Semiconductor device
JP2007221078A (en) Semiconductor device
JP3838156B2 (en) Semiconductor integrated circuit device
JP2003179131A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100723

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101227

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120821

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120903

R151 Written notification of patent or utility model registration

Ref document number: 5092860

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150928

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees