JP5353016B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a circuit from malfunctioning, by suppressing the occurrence of a displacement current for charging and discharging parasitic capacity composed by an insulation film, such as BOX, disposed between a support substrate and an active layer by dv/dt surge. <P>SOLUTION: A shield layer 3b formed at a low-potential reference circuit section LV is set to GND potential and a shielding layer 3b formed at a high-potential reference circuit section HV is set to be virtual GND potential. When the displacement current occurs, it reaches the support substrate 2 through a displacement current extraction layer 19 and the shielding layer 3b from virtual GND wiring 17b, in a high-potential reference circuit section HV and flows to GND wiring 17a through the shielding layer 3b and the displacement current extraction layer 19 in the low-potential reference circuit section LV. Thus, by preventing the displacement current from flowing to each kind of circuit that the low-potential reference circuit section LV has, malfunctions of the circuit can be prevented. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device used for an inverter control element or the like for driving a device such as a motor.

  As a semiconductor device used for an inverter control element or the like for driving a load such as a motor, there is an HVIC (High Voltage Integrated Circuit). The HVIC controls the power device provided in the inverter for driving the load.

  Conventionally, as shown in FIG. 6, the inverter is driven by a high-voltage reference gate drive circuit 103 corresponding to a high-voltage reference circuit that drives the high-side IGBT 102a of the inverter circuit 101 that drives the motor 100, and the low-side side. A low potential reference gate drive circuit 104 corresponding to a low voltage reference circuit for driving the IGBT 102b is provided, and an HVIC 107 provided with level shift elements 105a and 105b and a control circuit 106 therebetween is used. In the HIVC 107, the level shift of the reference voltage in the high potential reference circuit and the low voltage reference circuit is performed by transmitting a signal through the level shift elements 105a and 105b. In such an HVIC 107, in order to reduce the size of the inverter, one chip (HVIC) is being promoted, and the HVIC 107 shown in FIG. 6 is also configured by one chip.

However, in the HVIC 107 that is made into one chip in this way, there is a problem that potential interference occurs between the high potential reference circuit and the low potential reference circuit, causing the circuit to malfunction. For this reason, conventionally, element isolation is performed by a JI isolation structure, a dielectric isolation structure, a trench isolation structure using an SOI (Silicon on insulator) substrate (see, for example, Patent Document 1), and the like. However, since the potential of the output section for driving the IGBT 102a of the high potential reference circuit needs to be set to a virtual GND potential for use as a reference on the high voltage side, in any of the above element isolation structures, the level shift is low. When switching from a potential (for example, 0 V) to a high potential (for example, 750 V), a high voltage (for example, a voltage exceeding 1200 V) is generated at a fast rising speed of several tens of kV / μsec, and a large potential amplitude is generated. It is difficult to handle this high voltage surge with a fast rise (hereinafter referred to as dv / dt surge because of a high voltage rise with respect to the rise time) without malfunctioning of the circuit.
JP 2006-93229 A

  Among the element isolation structures described above, the trench isolation structure using an SOI substrate is considered to be the most resistant to noise and has the highest potential for element isolation. However, when a level shift element having a high withstand voltage has been developed using this structure, even in an HVIC having a trench isolation structure using an SOI substrate, the potential interferes with the support substrate when a dv / dt surge is applied. In addition, a displacement current that charges and discharges a parasitic capacitor formed by a buried oxide film (BOX) disposed between the support substrate and the active layer (SOI layer) is generated, causing the circuit to malfunction. The problem of end. FIG. 7 is a cross-sectional view of the HVIC showing how the displacement current is generated. As shown in this figure, for example, after flowing from the portion of the high potential reference circuit portion HV set to the virtual GND potential to the support substrate 2 via the buried layer 3 constituted by BOX, the buried layer 3 is again formed. Displacement current is generated through a path that flows into a portion of the low potential reference circuit portion LV that is set to the GND potential via the.

  Such a problem can be suppressed by increasing the BOX film thickness to reduce the parasitic capacitor capacity, or reducing the impurity concentration on the support substrate 2 side to increase the resistance to reduce displacement current propagation. In the case of integrating an amplifier circuit or the like with a high amplification factor, even a slight displacement current causes a malfunction, and a complete countermeasure is difficult.

  In view of the above points, the present invention provides a support substrate by a dv / dt surge when a semiconductor device including a low potential reference circuit, a high potential reference circuit, and a level shift element is formed by a trench isolation structure using an SOI substrate. An object of the present invention is to prevent a circuit from malfunctioning by suppressing the generation of a displacement current that charges and discharges a parasitic capacitance composed of an insulating film (for example, BOX) disposed between the active layer and the active layer.

In order to achieve the above object, according to the invention described in claims 1 to 11 , the buried layer (3) includes a first buried insulating film (3a) in contact with the active layer (1) and a support substrate (2). A second buried insulating film (3c) in contact therewith, and a shield layer (3b) made of a conductor material disposed between the first buried insulating film (3a) and the second buried insulating film (3c); The shield layer (3b) formed in the low potential reference circuit unit (LV) is insulated from the circuit element (10) of the low potential reference circuit unit (LV) in the active layer (1). The shield layer (3b) formed in the high potential reference circuit portion (HV) is electrically connected to the wiring (17a) to which the potential of 1 is applied, and the high potential reference circuit portion of the active layer (1). (HV) wiring for applying a second potential at a portion insulated from the circuit element (10) ( 7b), and the shield layer (3b) of the low potential reference circuit portion (LV) and the shield layer (3b) of the high potential reference circuit portion (HV) are electrically insulated and separated. It is characterized by that.

  Thus, the shield layer (3b) formed in the low potential reference circuit portion (LV) is set to the first potential, and the shield layer (3b) formed in the high potential reference circuit portion (HV) is the second potential. It is assumed to be a potential. Therefore, when a displacement current is generated, for example, after reaching the support substrate (2) through the shield layer (3b) from the wiring (17b) of the high potential reference circuit portion (HV), the low potential reference circuit portion ( LV) flows to the wiring (17a) through the shield layer (3b). Therefore, the displacement current can be prevented from flowing to various circuits provided in the low potential reference circuit portion (LV), and the circuit can be prevented from malfunctioning.

Specifically, in the first aspect of the invention, the ground potential is the first potential, the low potential reference circuit unit (LV) operates with the ground potential as the reference potential, and is a virtual potential that is higher than the ground potential. When the effective ground potential is the second potential and the high potential reference circuit portion (HV) operates with the virtual ground potential as the reference potential, the shield layer (3b) formed in the low potential reference circuit portion (LV) Is electrically connected to a ground line (17a) or a power supply line for applying a power supply voltage to a circuit in the low potential reference circuit portion (LV) to form a high potential reference circuit portion (HV). The shield layer (3b) thus formed is electrically connected to a virtual GND wiring (17b) having a virtual ground potential or a power supply line for applying a power supply voltage to a circuit in the high potential reference circuit portion (HV). I am doing so .

The invention according to claim 2 is characterized in that the first buried insulating film (3a) is thinner than the second buried insulating film (3c).

  If the first buried insulating film (3a) can insulate a potential difference (about 10 to 20 V) in a circuit formed in each of the low potential reference circuit portion (LV) and the high potential reference circuit portion (HV). good. Therefore, the thickness of the first buried insulating film (3a) can be reduced. For example, when the first buried insulating film (3a) is formed of an oxide film, the thickness can be 0.1 μm or less.

In the invention according to claim 4 , a portion of the active layer (1) that is insulated from the circuit element (10) of the low potential reference circuit portion (LV) and a high potential reference circuit portion of the active layer (1). A trench (18) that penetrates the first buried insulating film (3a) and reaches the shield layer (3b) is formed in a portion insulated from the circuit element (10) of (HV), and the trench (18) Further, a displacement current extraction layer (19) made of a conductive material is provided.

  Thus, a displacement current extraction layer (19) can be formed by forming a trench (18) in the active layer (1) and disposing a conductive material in the trench (18). A displacement current can be passed through the wiring (17a) of the low potential reference circuit section (LV) and the wiring (17b) on the high potential reference circuit section (HV) side through the current drawing layer (19).

The invention according to claim 6 is characterized in that the support substrate (2) is in a floating state and has a high resistance of several hundred Ωcm or more.

  As described above, when the support substrate (2) is in a floating state, it is possible to suppress a displacement current from flowing in the support substrate (2) by making the support substrate (2) high resistance. When the displacement current is generated, the current propagation can be reduced.

Further, the invention according to claim 7 is characterized in that the support substrate (2) has a ground potential or a virtual ground potential, and has a low resistance of 1 Ωcm or less.

  Thus, when the support substrate (2) is set to the ground potential or the virtual ground potential, the displacement current flows in the support substrate (2) by lowering the resistance of the support substrate (2). It is possible to suppress the propagation of current when a displacement current is generated.

In the invention according to claim 8 , the first trench isolation part (5b) which reaches the second buried insulating film (3c) through the shield layer (3b) in the active layer (1) and the buried layer (3). The electrical isolation between the shield layer (3b) of the low potential reference circuit portion (LV) and the shield layer (3b) of the high potential reference circuit portion (HV) is performed by the first trench isolation portion (5b). It is characterized by being done in.

  In this way, the first trench isolation part (5b) that reaches the second buried insulating film (3c) through the shield layer (3b) in the active layer (1) and the buried layer (3) has a low potential reference. It is possible to electrically isolate the shield layer (3b) of the circuit portion (LV) and the shield layer (3b) of the high potential reference circuit portion (HV).

The invention according to claim 9 is characterized in that the low potential reference circuit portion (LV) and the high potential reference circuit portion (HV) are surrounded by the first trench isolation portion (5b).

  With such a configuration, even if the shield layer (3b) is short-circuited to the support substrate (2) or the like at the end of the SOI substrate (4) during dicing cut or the like, the first trench isolation portion ( 5b), the low potential reference circuit portion (LV) and the high potential reference circuit portion (HV) can be prevented from being short-circuited with the support substrate (2) and the like.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view of a semiconductor device (HVIC) including a low potential reference circuit unit LV, a high potential reference circuit unit HV, and a level shift element formation unit LS according to the present embodiment. 2 is a layout diagram when the semiconductor device shown in FIG. 1 is viewed from the upper surface side, and FIG. 1 corresponds to a cross-sectional view taken along the line AA of FIG.

  Hereinafter, the configuration of the semiconductor device of this embodiment will be described with reference to these drawings.

  As shown in FIG. 1, the semiconductor device of this embodiment is formed using an SOI substrate 4 in which an SOI layer 1 made of, for example, n-type silicon and a support substrate 2 are bonded via a buried layer 3. ing. However, in the present embodiment, as the SOI substrate 4, the buried layer 3 is not composed of a single buried oxide film as in the prior art, but the buried layer 3 is made of a buried insulating film (first buried insulating film). Film) 3a, shield layer 3b, and buried insulating film (second buried insulating film) 3c having a three-layer structure, that is, five-layer structure of SOI layer 1, three-layer buried layer 3 and support substrate 2 A semiconductor device is formed using the substrate.

  The buried insulating films 3a and 3c are made of an insulating film such as an oxide film (BOX) or a nitride film, and have a general role of insulating the SOI layer 1 and the support substrate 2 and a shield sandwiched between them. It plays the role of insulating the layer 3b from the SOI layer 1 and the support substrate 2. The buried insulating film 3a is formed so as to be in contact with the SOI layer 1, and has a potential difference (about 10 to 20V) in a circuit formed in each of the low potential reference circuit unit LV and the high potential reference circuit unit HV. What is necessary is just to be able to insulate. For this reason, the thickness of the buried insulating film 3a can be reduced. For example, when the buried insulating film 3a is formed of an oxide film, the thickness can be 0.1 μm or less. The buried insulating film 3c is formed so as to be in contact with the support substrate 2 and needs to receive a potential difference between the low potential reference circuit portion LV and the high potential reference circuit portion HV. For this reason, the thickness of the buried insulating film 3c must be thicker than that of the buried insulating film 3a. For example, when the buried insulating film 3a is formed of an oxide film, it is preferably 2 to 4 μm.

  The shield layer 3b is for forming a displacement current extraction path, and is made of a material that easily allows current to flow, for example, a metal or a low-resistance semiconductor material such as doped Poly-Si or doped Si that has a high concentration of impurities. Has been. The details of the displacement current extraction path by the shield layer 3b will be described later.

  The SOI layer 1 is disposed on the surface side of the semiconductor device, and is configured by grinding a silicon substrate to a predetermined film thickness. The SOI layer 1 is element-isolated by a plurality of trench isolation parts 5a and 5b. The trench isolation parts 5a and 5b are configured with different depths. Specifically, as described above, the buried layer 3 has a structure in which two buried insulating films 3a and 3c are provided, but the trench isolation portion (second trench isolation portion) 5a is formed in the SOI layer 1. The trench isolation portion (first trench isolation portion) 5b is formed so as to reach the first-layer buried insulating film 3a on the side, and the second-layer buried insulation on the support substrate 2 side through the shield layer 3b. It is formed so as to reach the film 3c. Then, element isolation in the SOI layer 1 is performed in the trench isolation part 5a, and in addition to element isolation in the SOI layer 1 in the trench isolation part 5b, two buried insulating films of the buried layer 3 are provided. The shield layer 3b sandwiched between 3a is insulated and separated. Each of these trench isolation parts 5a and 5b is constituted by, for example, trenches 6a and 6b formed from the surface of the SOI layer 1, insulating films 7a and 7b disposed in the trenches 6a and 6b, and non-doped Poly-Si 8a and 8b. The trench isolation portion 5b is wider than the trench isolation portion 5a.

  The trench isolation portion 5 a is formed so as to surround each element scattered in the SOI layer 1. The trench isolation portion 5b has a multi-frame structure, and the region formed between the outermost trench isolation portion 5b and the inner trench isolation portion 5b (that is, the region on the left side of FIG. 1 and FIG. 2) is low. The potential reference circuit portion LV and the region in the innermost trench isolation portion 5b (that is, the region on the right side of the drawing) are formed between the high potential reference circuit portion HV and the low potential reference circuit portion LV and the high potential reference circuit portion HV. This region is the level shift element forming portion LS.

  The low potential reference circuit unit LV in the SOI layer 1 is configured with a signal processing circuit such as a logic circuit driven with a small potential. The low potential reference circuit unit LV is isolated from other parts of the semiconductor device by the trench isolation unit 5b, and the elements provided in the low potential reference circuit unit LV are electrically connected by the trench isolation unit 5a. Separated.

The low potential reference circuit unit LV includes various elements constituting a signal processing circuit such as a CMOS 10. Specifically, the region surrounded by the trench isolation portion 5a in the SOI layer 1 is isolated by an insulating film 11 for element isolation such as STI (Shallow Trench Isolation) or LOCOS oxide film. Each separated region is an n-well layer 12a or a p-well layer 12b. A p ⁺ type source region 13a and a p ⁺ type drain region 14a are formed in the n well layer 12a, and an n ⁺ type source region 13b and an n ⁺ type drain region 14b are formed in the p well layer 12b. The surface of the n well layer 12a located between the p ⁺ type source region 13a and the p ⁺ type drain region 14a and the p well layer located between the n ⁺ type source region 13b and the n ⁺ type drain region 14b. Gate electrodes 16a and 16b are formed on the surface of 12b via gate insulating films 15a and 15b. Thus, a CMOS 10 composed of an n-channel MOSFET and a p-channel MOSFET is configured.

  Incidentally, on the surface side of the SOI layer 1, gate electrodes 16a and 16b constituting the CMOS 10, wiring portions electrically connected to the source regions 13a and 13b or the drain regions 14a and 14b, an interlayer insulating film, and the like are formed. However, the illustration is omitted here. In addition to the CMOS 10, a bipolar transistor, a diffused resistor, and a memory are also provided. Since these structures are well known, only the CMOS 10 is shown here as a representative.

A predetermined portion of the low potential reference circuit portion LV configured as described above, for example, the p ⁺ type source region 13a and the n ⁺ type source region 13b is electrically connected to the GND wiring 17a to obtain the GND potential. In the embodiment, the shield layer 3b of the low potential reference circuit unit LV is also set at the GND potential. Specifically, a trench 18 is formed in a portion of the SOI layer 1 surrounding each element, and a displacement current extraction layer 19 is provided by embedding the trench 18 with metal, doped Poly-Si, or the like. By electrically connecting the displacement current extraction layer 19 to the GND wiring 17a, the shield layer 3b is set to the GND potential. The trench 18 and the displacement current extraction layer 19 may be of any type, but in this embodiment, the top surface has a circular shape as shown in FIG. A plurality of portions are arranged around the portion 5a.

  On the other hand, the high potential reference circuit unit HV in the SOI layer 1 includes a signal processing circuit such as a logic circuit driven at a high potential. The high potential reference circuit unit HV is element-isolated from other parts of the semiconductor device by the trench isolation unit 5b, and the elements provided in the high potential reference circuit unit HV are also electrically connected by the trench isolation unit 5a. Separated.

  The high potential reference circuit portion HV is also provided with a CMOS 10 having a structure similar to that of the low potential reference circuit portion LV, and is also provided with a bipolar transistor, a diffused resistor, and a memory (not shown).

As for the high potential reference circuit unit HV configured as described above, the p ⁺ type source region 13a and the n ⁺ type source region 13b are electrically connected to the virtual GND wiring 17b, similarly to the low potential reference circuit unit LV. Thus, the virtual GND potential serving as a reference on the high voltage side (that is, the potential when a voltage higher than the GND potential (potential zero) is virtually positioned as the ground potential) is set, and the shield layer 3b is also set to the virtual GND potential.

  As described above, both the low potential reference circuit portion LV and the high potential reference circuit portion HV have a structure in which the shield layer 3b and the GND wiring 17a are electrically connected through the displacement current extraction layer 19. However, the shield layer 3b of the high potential reference circuit unit HV and the shield layer 3b of the low potential reference circuit unit LV are insulated and separated by the trench isolation unit 5b reaching the second buried insulating film 3c. The part electrically connected to the GND wiring 17a through the layer 3b and the part electrically connected to the virtual GND wiring 17b are not short-circuited.

In the level shift element forming portion LS in the SOI layer 1, a high breakdown voltage LDMOS 20 is formed as a level shift element. The high breakdown voltage LDMOS 20 includes an n-type drain region 21, a p-type channel region 22, and an n ⁺ -type source region 23 that are located on the surface layer of the SOI layer 1. An n ⁺ -type contact layer 24 is formed on the surface layer of the n-type drain region 21, and a p-type contact layer 25 is formed on the surface layer of the p-type channel region 22. The n-type drain region 21 and the p-type channel region 22 are separated by a so-called LOCOS oxide film 26. A gate electrode 28 is disposed on the p-type channel region 22 via a gate insulating film 27. Thereby, a high breakdown voltage LDMOS 20 is configured.

On the surface side of the SOI layer 1, there are a gate electrode 28, an n ⁺ -type source region 23 and a p-type contact layer 25, or a wiring portion and an interlayer insulating film that are electrically connected to the n ⁺ -type contact layer 24. Although formed, illustration is omitted here.

  The support substrate 2 is composed of, for example, an n-type or p-type silicon substrate. The support substrate 2 is in a floating state, or is set to a GND potential or a virtual GND potential. When the support substrate 2 is in a floating state, the impurity concentration is set low so that the support substrate 2 has a high resistance (for example, several hundred Ωcm or more). When the GND potential or the virtual GND potential is set, the impurity concentration is set high so that the support substrate 2 has a low resistance (for example, 1 Ωcm or less). With this configuration, it is possible to suppress the displacement current from flowing through the support substrate 2, and it is possible to reduce current propagation when the displacement current is generated.

  In the semiconductor device of the present embodiment described above, the shield layer 3b formed in the low potential reference circuit unit LV is set to the GND potential, and the shield layer 3b formed in the high potential reference circuit unit HV is set to the virtual GND potential. Yes. For this reason, when a displacement current occurs, it flows, for example, along the path shown in FIG. That is, after reaching the support substrate 2 from the virtual GND wiring 17b of the high potential reference circuit unit HV through the displacement current extraction layer 19 and the shield layer 3b, the GND is transmitted through the shield layer 3b and the displacement current extraction layer 19 of the low potential reference circuit unit LV. It flows to the wiring 17a. Therefore, the displacement current can be prevented from flowing to various circuits provided in the low potential reference circuit unit LV, and the circuit can be prevented from malfunctioning.

  In such a semiconductor device, the outermost trench isolation portion 5b is formed so as to surround both the low potential reference circuit portion LV and the high potential reference circuit portion HV. For this reason, even if the shield layer 3b is short-circuited to the support substrate 2 or the like at the end of the SOI substrate 4 at the time of dicing cut or the like, the low-voltage reference circuit is insulated and isolated by the trench isolation portion 5b. The part LV and the high potential reference circuit part HV can be prevented from being short-circuited with the support substrate 2 or the like.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to the manufacturing process of the semiconductor device according to the present embodiment shown in FIGS. However, since the manufacturing method of each element in the semiconductor device according to the present embodiment is the same as a well-known one, here, the manufacturing process of the SOI substrate 4 and the process of forming the trench isolation portions 5a and 5b on the SOI substrate 4 Only will be described. 4 shows the manufacturing process of the entire SOI substrate 4, but FIG. 5 shows an enlarged manufacturing process of only a part of the SOI substrate 4, specifically, the trench isolation portions 5a and 5b. is there.

  First, as shown in FIG. 4A, after preparing a support substrate 2 composed of, for example, an n-type or p-type silicon substrate, the surface of the support substrate 2 is oxidized by, for example, thermal oxidation or CVD. A buried insulating film 3c is formed by forming a film. Next, a shield layer 3b is formed by depositing doped Poly-Si or doped Si on the surface of the buried insulating film 3c on the surface side of the support substrate 2 by a CVD method or a metal layer.

  Subsequently, as shown in FIG. 4B, a buried insulating film 3a is formed on the surface of the shield layer 3b. For example, if the shield layer 3b described above is composed of doped Poly-Si or doped Si, the buried insulating film 3a can be formed by forming a silicon oxide film by thermal oxidation. If the metal layer is used, the buried insulating film 3a can be formed by forming a silicon oxide film or the like by the CVD method.

  Thereafter, as shown in FIG. 4C, an SOI substrate 4 is formed by bonding, for example, an n-type silicon substrate 30 to the surface of the buried insulating film 3a, and then as shown in FIG. Further, the SOI layer 1 is formed by grinding and thinning the outer peripheral portion and the surface of the silicon substrate 30. Thereby, the SOI substrate 4 is completed. At this stage, the silicon oxide film or the like when the buried insulating film 3c is formed also remains on the back side of the support substrate 2, but it may be removed after the device is formed.

  Next, in the step shown in FIG. 5A, a mask layer 31 is formed by, for example, forming a silicon oxide film on the surface of the SOI layer 1 by a CVD method. Then, the formation positions of the trench isolation portions 5a and 5b in the mask layer 31 are opened by photo-etching. At this time, the opening width of the trench isolation part 5b deeper than that of the shallow trench isolation part 5a is set to be wider.

  Subsequently, as shown in FIG. 5B, trenches 6a and 6b are formed from the surface of the SOI layer 1 by etching using the mask layer 31 as a mask. At this time, the etching rate of the trenches 6a and 6b depends on the opening width of the mask layer 31, and the etching increases as the opening width increases. For this reason, by forming the trench 6b deeper than the trench 6a, the trench 6a reaches the first buried insulating film 3a, and the trench 6b reaches the second buried insulating film 3c. The trenches 6a and 6b having different depths can be formed at the same time in one trench formation step so as to have the depth.

  Thereafter, as shown in FIG. 5C, after the insulating films 7a and 7b are formed on the inner walls of the trenches 6a and 6b by performing thermal oxidation or forming a silicon oxide film or the like by the CVD method. After the trenches 6a and 6b are filled by forming non-doped Poly-Si 8a and 8b on the surfaces of the insulating films 7a and 7b, the mask layer 31 is removed. Thereby, trench isolation parts 5a and 5b are formed. Although the subsequent steps are not illustrated, the semiconductor device of this embodiment is completed by forming each element by a known method.

(Other embodiments)
In the above-described embodiment, an example of elements constituting the low potential reference circuit unit LV, the high potential reference circuit unit HV, and the level shift element forming unit LS is described. However, the types of elements constituting these can be changed as appropriate. It is. Of course, the layout of the trench isolation parts 5a and 5b and the displacement current extraction layer 19 can be appropriately changed.

  In the above-described embodiment, the case where the first potential applied to the low potential reference circuit unit LV is the GND potential and the second potential applied to the high potential reference circuit unit HV is the virtual GND potential has been described. However, the driving potential of the circuit elements provided in the low potential reference circuit unit LV and the high potential reference circuit unit HV (that is, the power supply line for applying the power supply voltage to the circuits in the circuit units LV and HV) is the first potential. Alternatively, the second potential can be used. That is, the driving potentials of the circuit elements provided in the low potential reference circuit unit LV and the high potential reference circuit unit HV are about 10 to 20 V higher than the GND potential and the virtual GND potential, respectively, but the virtual GND potential And the potential difference between the GND potential and the GND potential are sufficiently small. Therefore, the potential applied to the circuit elements of the low potential reference circuit unit LV and the high potential reference circuit unit HV can be set to the first potential or the second potential instead of the GND potential or the virtual GND potential. .

  Moreover, although the said embodiment gave and demonstrated an example of the manufacturing method of the semiconductor device concerning the said embodiment, it does not restrict to this. For example, in the above, the buried insulating film 3c, the shield layer 3b, and the buried insulating film 3a are sequentially formed on the surface of the support substrate 2, and then the silicon substrate 30 for forming the SOI layer 1 is bonded. However, any one or more of the buried insulating film 3c, the shield layer 3b, and the buried insulating film 3c may be formed on the silicon substrate 30 side, and then bonded to the support substrate 2. . Moreover, although the case where trenches 6a and 6b are formed simultaneously has been described, these may be formed in separate trench forming steps.

1 is a cross-sectional view of a semiconductor device (HVIC) according to a first embodiment of the present invention. FIG. 2 is a layout diagram when the semiconductor device shown in FIG. 1 is viewed from the upper surface side. FIG. 2 is a cross-sectional view showing an example of a path of a displacement current in the semiconductor device shown in FIG. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 4; It is a schematic diagram of the inverter drive circuit using HVIC. It is sectional drawing of HVIC which showed a mode that a displacement current generate | occur | produced.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 SOI layer 2 Support substrate 3 Embedded layer 3a, 3b Embedded insulating film 3b Shield layer 4 SOI substrate 5a, 5b Trench isolation part 6a, 6b Trench 7a, 7b Insulating film 10 CMOS
17a GND wiring 17b Virtual GND wiring 18 Trench 19 Displacement current extraction layer 20 High breakdown voltage LDMOS
30 Silicon substrate 31 Mask layer HV High potential reference circuit part LS Level shift element formation part LV Low potential reference circuit part

Claims (11)

An SOI substrate (4) in which an active layer (1) and a supporting substrate (2) are bonded together via an embedded film (3);
A low potential reference circuit portion (LV) including a circuit element (10) to which a first potential is applied to the active layer (1) in the SOI substrate (4), and a potential higher than the first potential. A high potential reference circuit section (HV) including a circuit element (10) to which a second potential is applied, and between the low potential reference circuit section (LV) and the high potential reference circuit section (HV). In a semiconductor device formed with a level shift element forming portion (LS) provided with a level shift element (20) for performing level shift of a reference potential,
The buried layer (3) includes a first buried insulating film (3a) in contact with the active layer (1), a second buried insulating film (3c) in contact with the support substrate (2), and the first A shield layer (3b) made of a conductor material disposed between the buried insulating film (3a) and the second buried insulating film (3c);
In the portion of the active layer (1) where the shield layer (3b) formed in the low potential reference circuit portion (LV) is insulated from the circuit element (10) of the low potential reference circuit portion (LV). The shield layer (3b) formed in the high potential reference circuit portion (HV) is electrically connected to the wiring (17a) for applying the first potential, and is included in the active layer (1). Electrically connected to the wiring (17b) for applying the second potential at a portion insulated from the circuit element (10) of the high potential reference circuit portion (HV);
The shield layer (3b) of the low potential reference circuit portion (LV) and the shield layer (3b) of the high potential reference circuit portion (HV) are electrically insulated and separated ,
The ground potential is the first potential, and the low potential reference circuit unit (LV) operates with the ground potential as a reference potential.
A virtual ground potential that is higher than the ground potential is set as the second potential, and the high potential reference circuit unit (HV) operates using the virtual ground potential as a reference potential.
The shield layer (3b) formed in the low potential reference circuit portion (LV) applies a power supply voltage to the GND wiring (17a) to which the ground potential is applied or to a circuit in the low potential reference circuit portion (LV). A virtual GND wiring (17b) that is electrically connected to the power supply line and the shield layer (3b) formed in the high potential reference circuit portion (HV) is set to the virtual ground potential, or A semiconductor device characterized by being electrically connected to a power supply line for applying a power supply voltage to a circuit in a high potential reference circuit portion (HV) . An SOI substrate (4) in which an active layer (1) and a supporting substrate (2) are bonded together via an embedded film (3);
A low potential reference circuit portion (LV) including a circuit element (10) to which a first potential is applied to the active layer (1) in the SOI substrate (4), and a potential higher than the first potential. A high potential reference circuit section (HV) including a circuit element (10) to which a second potential is applied, and between the low potential reference circuit section (LV) and the high potential reference circuit section (HV). In a semiconductor device formed with a level shift element forming portion (LS) provided with a level shift element (20) for performing level shift of a reference potential,
The buried layer (3) includes a first buried insulating film (3a) in contact with the active layer (1), a second buried insulating film (3c) in contact with the support substrate (2), and the first A shield layer (3b) made of a conductor material disposed between the buried insulating film (3a) and the second buried insulating film (3c);
In the portion of the active layer (1) where the shield layer (3b) formed in the low potential reference circuit portion (LV) is insulated from the circuit element (10) of the low potential reference circuit portion (LV). The shield layer (3b) formed in the high potential reference circuit portion (HV) is electrically connected to the wiring (17a) for applying the first potential, and is included in the active layer (1). Electrically connected to the wiring (17b) for applying the second potential at a portion insulated from the circuit element (10) of the high potential reference circuit portion (HV);
The shield layer (3b) of the low potential reference circuit portion (LV) and the shield layer (3b) of the high potential reference circuit portion (HV) are electrically insulated and separated,
The first buried insulating film (3a), the semi-conductor device you characterized in that it is thinner than the second buried insulating film (3c). The shield layer (3b) A semiconductor device according to claim 1 or 2 Poly-Si or impurities metal layer or impurity-doped, characterized in that it is constituted by doped Si. An SOI substrate (4) in which an active layer (1) and a supporting substrate (2) are bonded together via an embedded film (3);
A low potential reference circuit portion (LV) including a circuit element (10) to which a first potential is applied to the active layer (1) in the SOI substrate (4), and a potential higher than the first potential. A high potential reference circuit section (HV) including a circuit element (10) to which a second potential is applied, and between the low potential reference circuit section (LV) and the high potential reference circuit section (HV). In a semiconductor device formed with a level shift element forming portion (LS) provided with a level shift element (20) for performing level shift of a reference potential,
The buried layer (3) includes a first buried insulating film (3a) in contact with the active layer (1), a second buried insulating film (3c) in contact with the support substrate (2), and the first A shield layer (3b) made of a conductor material disposed between the buried insulating film (3a) and the second buried insulating film (3c);
In the portion of the active layer (1) where the shield layer (3b) formed in the low potential reference circuit portion (LV) is insulated from the circuit element (10) of the low potential reference circuit portion (LV). The shield layer (3b) formed in the high potential reference circuit portion (HV) is electrically connected to the wiring (17a) for applying the first potential, and is included in the active layer (1). Electrically connected to the wiring (17b) for applying the second potential at a portion insulated from the circuit element (10) of the high potential reference circuit portion (HV);
The shield layer (3b) of the low potential reference circuit portion (LV) and the shield layer (3b) of the high potential reference circuit portion (HV) are electrically insulated and separated,
A portion of the active layer (1) insulated from the circuit element (10) of the low potential reference circuit portion (LV), and a portion of the high potential reference circuit portion (HV) of the active layer (1). A trench (18) that penetrates the first buried insulating film (3a) and reaches the shield layer (3b) is formed in a portion insulated from the circuit element (10), and is formed in the trench (18). conductive displacement current sink layer made of a material (19) semi-conductor device you characterized in that is provided. 5. The semiconductor device according to claim 4 , wherein the displacement current extraction layer (19) is made of a metal layer, Poly-Si doped with impurities, or Si doped with impurities. The supporting substrate (2) is in a floating state, and the semiconductor device according to any one of claims 1 to 5, characterized in that is several hundred Ωcm or more high resistance. The support substrate (2) has a ground potential or a virtual ground potential applied to the high potential reference circuit portion (HV), and has a low resistance of 1 Ωcm or less. 6. The semiconductor device according to any one of 5 to 5 . A first trench isolation part (5b) that reaches the second buried insulating film (3c) through the shield layer (3b) in the active layer (1) and the buried layer (3); The electrical isolation between the shield layer (3b) of the low potential reference circuit unit (LV) and the shield layer (3b) of the high potential reference circuit unit (HV) is performed by the first trench isolation unit (5b). that it has been made in the semiconductor device according to any one of claims 1 to 7, characterized in. 9. The semiconductor device according to claim 8 , wherein the first trench isolation part (5b) surrounds the low potential reference circuit part (LV) and the high potential reference circuit part (HV). A second trench isolation portion (5a) reaching the first buried insulating film (3a) in the active layer (1) and the buried layer (3), and the low potential reference circuit portion (LV) or the according to claim 8 or 9 isolation between the circuit element formed on the high potential reference circuit (HV) (10) is characterized in that it is performed in the second trench isolation (5a) Semiconductor device. 11. The semiconductor device according to claim 10 , wherein the first trench isolation part (5b) is wider than the second trench isolation part (5a).

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