JP2001015590A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dielectric isolation type semiconductor integrated circuit in which an adverse effect of noise current generated upon high-voltage and high-speed switching can be reduced. SOLUTION: A dielectric isolation layer 12 is formed on a support substrate 11. An active layer 13 connected to a first potential end is formed on the dielectric isolation layer 12. Furthermore, an active layer 14 connected to a second potential end having a potential lower than that of the first potential end is formed on the dielectric isolation layer 12. Furthermore, an active layer 15 disposed between the active layers 13 and 14 and connected to a third potential end having a potential lower than that of the second potential end is formed on the dielectric isolation layer 12. Dielectric isolation layers 16 for isolating these active layers are formed between the active layers 13, 14, 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric isolation type semiconductor integrated circuit which performs a switching operation.

[0002]

2. Description of the Related Art A conventional dielectric isolation type semiconductor integrated circuit has the following structure.

FIG. 4 is a sectional view showing the structure of the dielectric isolation type semiconductor integrated circuit.

On a supporting substrate 101, a dielectric isolation layer 10 is provided.
2, separated active layers 103 and 104 are formed. On both sides of these active layers 103 and 104, dielectric isolation layers 105 are formed. A switching element is formed on the active layer 103, and a control circuit for controlling the switching element and the like are formed on the active layer 104. In the semiconductor integrated circuit having such a structure, a parasitic capacitor is formed between the active layer 103 and the active layer 104.

[0005]

In the dielectric isolation type semiconductor integrated circuit, since a parasitic capacitor exists between the active layer 103 and the active layer 104, a noise current due to a displacement voltage during switching operation of the switching element is reduced. It flows from the active layer 103 to the active layer 104. The control circuit formed in the active layer 104 may be adversely affected by the noise current. In particular, in the case where a circuit using a minute current, a circuit for comparing a minute voltage, or the like is formed in the active layer 104, the noise current causes a malfunction or a deterioration in accuracy.

The present invention has been made in view of the above problems, and provides a semiconductor integrated circuit of a dielectric isolation type which can reduce the adverse effect of noise current generated during high-voltage, high-speed switching operation. The purpose is to do.

[0007]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention has a first active layer formed separately by a dielectric layer and connected to a first potential terminal. And a second active layer formed by a dielectric layer and connected to a second potential terminal lower in potential than the first potential terminal, and a second active layer formed by a dielectric layer and separated by a dielectric layer. A third active layer disposed between the first active layer and the second active layer and connected to a third potential terminal having a lower potential than the second potential terminal. And

Further, a semiconductor integrated circuit device according to the present invention is formed by being separated by a dielectric layer, and is formed by being separated by a dielectric layer from a first active layer connected to a first potential terminal. A second active layer connected to a second potential terminal having a lower potential than the first potential terminal, and a second active layer separated by a dielectric layer, the first active layer and the second active layer being separated from each other; And a third active layer connected to a third potential terminal lower in potential than the second potential terminal and separated by a dielectric layer, the first active layer And a fourth active layer disposed between the third active layer and the third active layer.

Further, a semiconductor integrated circuit according to the present invention comprises:
A dielectric layer formed on the substrate, a first active layer formed on the dielectric layer and connected to a first potential terminal, and a first active layer formed on the dielectric layer; A second active layer connected to a second potential end having a lower potential than the end, formed on the dielectric layer, disposed between the first active layer and the second active layer; Forming a third active layer connected to a third potential terminal having a lower potential than the second potential terminal, and the first and third active layers, and the second and third active layers, respectively. And a dielectric layer separating the active layer.

Further, a semiconductor integrated circuit according to the present invention comprises:
A dielectric layer formed on the substrate, a first active layer formed on the dielectric layer and connected to a first potential terminal, and a first active layer formed on the dielectric layer; A second active layer connected to a second potential end having a lower potential than the end, formed on the dielectric layer, disposed between the first active layer and the second active layer; A third active layer connected to a third potential terminal having a lower potential than the second potential terminal; and a first active layer and a third active layer formed on the dielectric layer. A fourth active layer disposed between the first and fourth active layers, the third and fourth active layers, and the second and third active layers, respectively. And a dielectric layer separating the layers.

According to the present invention, an active layer is formed between an active layer having a switching element block and an active layer having a control circuit block, and a diffusion layer is provided on the active layer to ground. By connecting to a low voltage side such as a potential terminal, a noise current generated at the time of switching operation is absorbed from the diffusion layer to a ground potential terminal (low voltage side). As a result, the adverse effect of the noise current on the control circuit block, in particular, a circuit using a small current, a circuit for comparing a small voltage, and the like is reduced, and malfunction and deterioration of operation accuracy are prevented.

Further, according to the present invention, a plurality of active layers are formed between an active layer having a switching element block, which is dielectrically separated, and an active layer having the control circuit block. By providing a diffusion layer in the active layer and connecting it to a low voltage side such as a ground potential end, a noise current generated during the switching operation is absorbed from the diffusion layer to the ground potential end (low voltage side). As a result, the noise current flowing is reduced, and the adverse effect of the noise current on the control circuit block, particularly a circuit using a small current or a circuit for comparing a small voltage is reduced, thereby preventing malfunction and deterioration of operation accuracy.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a sectional view showing the structure of a dielectric isolation type semiconductor integrated circuit according to a first embodiment.

On the supporting substrate 11, active layers (n layers) 13, 14, separated from each other via a dielectric separation layer 12,
15 are formed. On both sides of the active layer 13 and the active layer 14, a dielectric isolation layer 16 is formed so as to sandwich them. An active layer 15 is arranged between the dielectric layers 16 between the active layers 13 and 14.

The active layer 13 includes a switching element,
For example, IGBT (Insulated Gate Bipolar Transisto)
r) or a power MOS or the like is formed. The active layer 1
In 4, a control circuit for controlling the switching element is formed. The active layer 15 includes a diffusion layer (n + layer) 1
7 is formed. The diffusion layer 17 is connected to a ground potential (GND) terminal by a metal wiring or the like. The dielectric isolation layers 12 and 16 are made of an oxide film or the like.

In the semiconductor integrated circuit having such a structure, a parasitic capacitor is formed between the active layers 13 and 15, and between the active layers 14 and 15. Active layer 1
5 includes a diffusion layer 17 connected to a ground potential (GND) terminal.
Is provided, one electrode of the parasitic capacitor is connected to the ground potential terminal.

Next, the circuit configuration of the semiconductor integrated circuit will be described.

FIG. 2 is a circuit diagram showing a configuration of the semiconductor integrated circuit. Here, an IGBT, which is one of the semiconductor integrated circuits for switching, and a drive circuit thereof will be described as an example.

An IGBT 23 as a switching element and a regenerating diode 24 are connected between the high voltage (VB) terminal 21 and the output unit 22, respectively. The upper arm control circuit 25 is connected to the gate of the IGBT 23, and the internal power supply VINT and the output unit 22 are connected to the upper arm control circuit 25.

Further, a lower arm control circuit 27 and a lower arm driver 28 are connected between the low voltage (VDD) terminal 26 and the ground potential (GND) terminal. The input signal terminal 29 is connected to the lower arm control circuit 27, and the output terminal of the lower arm control circuit 27 is connected to the gate of the transistor 30. The collector of the transistor 30 is connected to the upper arm control circuit 25, and the emitter is connected to the ground potential terminal.

Further, between the output unit 22 and the ground potential terminal,
The IGBT 31 and the regenerative diode 32 are respectively connected. The lower arm driver 28 is connected to the gate of the IGBT 31.

In such a circuit, the IGBT 2
3, the diode 24, and the upper arm control circuit 25 are formed in the active layer 13. The lower arm control circuit 2
7, transistor 30, lower arm driver 28, IGB
T31 and the diode 32 are formed in the active layer 14.

Next, the operation of the semiconductor integrated circuit according to the first embodiment will be described.

First, a drive signal is input from the input signal terminal 29, and a signal for turning on the transistor 30 is output from the lower arm control circuit 27. When the transistor 30 is turned on, a signal flows to the upper arm control circuit 25, whereby the upper arm control circuit 25 outputs a signal for turning on the IGBT 23.

When the IGBT 23 is turned on, a current flows from the high voltage VB terminal 21 to the output section 22, and the output section 22 changes to the high voltage VB side with a displacement voltage (dv / dt). At this time, IG
From the active layer 13 side where the BT 23 and the output unit 22 are formed, a noise current caused by the displacement voltage flows into the active layer 15 side via a parasitic capacitor. Since the diffusion layer 17 connected to the ground potential (GND) terminal is provided on the active layer 15 side, the noise current flowing into the active layer 15 passes through the diffusion layer 17 and is absorbed by the ground potential terminal. .

As described above, the noise current caused by the displacement voltage at the time of the switching operation can be suppressed from flowing into the active layer 14 via the parasitic capacitor between the active layer 15 and the active layer 14. 14 can be prevented from adversely affecting the control circuit and other circuits formed therein.

That is, an active layer is formed between an active layer having a switching element block which is dielectrically isolated and an active layer having its control circuit block, and a diffusion layer is provided on this active layer to form a ground potential terminal or the like. , The noise current generated during the switching operation is absorbed from the diffusion layer to the ground potential end (low voltage side). As a result, the adverse effect of the noise current on the control circuit block, in particular, a circuit using a small current, a circuit for comparing a small voltage, and the like is reduced, and malfunction and deterioration of operation accuracy are prevented. In addition,
Although the IGBT is used in the above embodiment, a power MOS may be used instead.

As described above, according to the first embodiment, in the dielectric isolation type switching semiconductor integrated circuit, the noise current generated due to the displacement voltage at the time of high-voltage, high-speed switching operation is generated. An adverse effect on a control circuit and the like can be reduced.

[Second Embodiment] Next, a second embodiment of the present invention will be described.
A semiconductor integrated circuit of a dielectric isolation type according to the embodiment will be described.

FIG. 3 is a sectional view showing the structure of a dielectric isolation type semiconductor integrated circuit according to the second embodiment. The second embodiment is different from the first embodiment in the active layer 1.
An active layer and a dielectric layer are added between the active layer 3 and the active layer 15.

On the support substrate 11, active layers (n layers) 13, 14 separated from each other via a dielectric separation layer 12.
15 and an active layer (n-layer) 41 are formed. On both sides of the active layer 13 and the active layer 14, a dielectric isolation layer 16 is formed so as to sandwich them. And the active layer 1
The active layer 15, the dielectric isolation layer 16, and the active layer 41 are arranged between the dielectric isolation layer 16 between the active layer 3 and the active layer 14.

As in the first embodiment, a switching element, for example, an IGBT (Insu
lated Gate Bipolar Transistor) is formed. In the active layer 14, a control circuit for controlling a switching element is formed. The active layer 15 includes a diffusion layer (n
(+ Layer) 17 is formed. The diffusion layer 17 is connected to a ground potential (GND) terminal by a metal wiring or the like.
The dielectric isolation layers 12 and 16 are made of an oxide film or the like.

In the semiconductor integrated circuit having such a structure, a parasitic capacitor is provided between the active layers 13 and 41, between the active layers 41 and 15, and between the active layers 15 and 14. Are respectively formed. In the active layer 15,
Since the diffusion layer 17 connected to the ground potential (GND) terminal is provided, one electrode of the parasitic capacitor is connected to the ground potential terminal.

Next, the circuit configuration of the semiconductor integrated circuit is configured as shown in FIG.
The description is omitted because it is the same as that of the embodiment.

In such a circuit, the IGBT 2
3, the diode 24, and the upper arm control circuit 25 are formed in the active layer 13. The lower arm control circuit 2
7, transistor 30, lower arm driver 28, IGB
T31 and the diode 32 are formed in the active layer 14.

Next, the operation of the semiconductor integrated circuit according to the second embodiment will be described.

A signal for turning on the IGBT 23 is output from the upper arm control circuit 25, and when the IGBT 23 is turned on, a current flows from the high voltage VB terminal 21 to the output section 22, and the output section 22 moves the displacement voltage (dv) to the high voltage VB side. / dt). At this time, a noise current caused by the displacement voltage flows from the active layer 13 side where the IGBT 23 and the output unit 22 are formed to the active layer 41 side via the parasitic capacitor, and further flows to the active layer 15 side via the parasitic capacitor. . Since the diffusion layer 17 connected to the ground potential (GND) terminal is provided on the active layer 15 side, the noise current flowing into the active layer 15 passes through the diffusion layer 17 and is absorbed by the ground potential terminal. .

As described above, it is possible to suppress the noise current caused by the displacement voltage during the switching operation from flowing into the active layer 14 via the parasitic capacitor between the active layer 15 and the active layer 14. Further, the active layer 13 and the active layer 41
During this time, a parasitic capacitor is connected in series between the active layer 41 and the active layer 15, and its capacitance is reduced. Therefore, the active layer 13
, The noise current flowing to the active layer 15 can be reduced. Therefore, in the second embodiment, it is possible to further prevent the adverse effect of the noise current on the control circuit and other circuits formed in the active layer 14 as compared with the first embodiment. it can.

That is, a plurality of active layers are formed between an active layer having a switching element block which is dielectrically separated and an active layer having a control circuit block, and a diffusion layer is formed in an active layer close to the control circuit block. Is provided and connected to a low voltage side such as a ground potential terminal, thereby absorbing a noise current generated during the switching operation from the diffusion layer to the ground potential terminal (low voltage side). As a result, the noise current flowing is reduced, and the adverse effect of the noise current on the control circuit block, particularly a circuit using a small current or a circuit for comparing a small voltage is reduced, thereby preventing malfunction and deterioration of operation accuracy. Although the IGBT is used in the above embodiment, a power MOS may be used instead.

As described above, according to the second embodiment, in the dielectric isolation type switching semiconductor integrated circuit, the noise current generated due to the displacement voltage at the time of high voltage and high speed switching operation is generated. An adverse effect on a control circuit and the like can be reduced.

[0042]

As described above, according to the present invention, in a dielectric isolation type semiconductor integrated circuit, it is possible to provide a semiconductor integrated circuit which can reduce the adverse effect of noise current generated at the time of high-voltage, high-speed switching operation. It is possible.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a dielectric isolation type semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of a semiconductor integrated circuit according to first and second embodiments.

FIG. 3 is a sectional view showing a structure of a dielectric isolation type semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a structure of a conventional dielectric isolation type semiconductor integrated circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Support substrate 12 ... Dielectric separation layer 13, 14, 15 ... Active layer (n layer) 16 ... Dielectric separation layer 17 ... Diffusion layer (n + layer) 21 ... High voltage (VB) end 22 ... Output part 23 ... IGBT (Insulated Gate Bipolar Transisto)
r) 24 diode 25 upper arm control circuit 26 low voltage (VDD) terminal 27 lower arm control circuit 28 lower arm driver 29 input signal terminal 30 transistor 31 IGBT (Insulated Gate Bipolar Transisto)
r) 32: diode 41: active layer (n-layer) 101: support substrate 102: dielectric separation layer 103, 104: active layer 105: dielectric separation layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F032 AA03 CA17 CA18 CA23 CA24 5F110 AA02 CC09 NN62

Claims (9)

[Claims] A first dielectric layer formed by a dielectric layer;
A first active layer connected to a potential end of the first active layer, a second active layer formed separately from the dielectric layer and connected to a second potential end lower in potential than the first potential end, It is formed separated by a dielectric layer, is disposed between the first active layer and the second active layer, and is connected to a third potential terminal lower in potential than the second potential terminal. A semiconductor integrated circuit, comprising: a third active layer. 2. The method according to claim 1, wherein the first and second dielectric layers are separated by a dielectric layer.
A first active layer connected to a potential end of the first active layer, a second active layer formed separately from the dielectric layer and connected to a second potential end lower in potential than the first potential end, It is formed separated by a dielectric layer, is disposed between the first active layer and the second active layer, and is connected to a third potential terminal lower in potential than the second potential terminal. A third active layer, and a fourth active layer formed by being separated by a dielectric layer and disposed between the first active layer and the third active layer. Semiconductor integrated circuit. 3. A dielectric layer formed on the substrate, a first active layer formed on the dielectric layer and connected to a first potential terminal, and formed on the dielectric layer; A second active layer connected to a second potential terminal having a lower potential than the first potential terminal; and a second active layer formed on the dielectric layer and between the first active layer and the second active layer. A third active layer connected to a third potential terminal lower in potential than the second potential terminal, the first and third active layers, and the second and third active layers. And a dielectric layer formed between the active layers and separating the active layers. 4. A dielectric layer formed on the substrate, a first active layer formed on the dielectric layer and connected to a first potential terminal, and formed on the dielectric layer; A second active layer connected to a second potential terminal having a lower potential than the first potential terminal; and a second active layer formed on the dielectric layer and between the first active layer and the second active layer. A third active layer connected to a third potential terminal lower in potential than the second potential terminal; and a third active layer formed on the dielectric layer, the first active layer and the third active layer being formed on the dielectric layer. A third active layer disposed between the first and fourth active layers, the third and fourth active layers, and the second and third active layers, respectively. And a dielectric layer formed to separate the active layer. 5. The semiconductor integrated circuit according to claim 1, wherein a switching element is formed on said first active layer. 6. The semiconductor integrated circuit according to claim 5, wherein a control circuit for controlling said switching element is formed in said second active layer. 7. A diffusion layer is formed on the third active layer,
7. The semiconductor integrated circuit according to any one of 1 to 6, wherein the diffusion layer is connected to a ground potential terminal. 8. The switching device according to claim 1, wherein the switching element is an IGBT (Insu
7. The semiconductor integrated circuit according to 5 or 6, wherein the semiconductor integrated circuit is a lated gate bipolar transistor. 9. The semiconductor integrated circuit according to claim 1, wherein said dielectric layer has an oxide film.