JP3519226B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a power integrated circuit in which a push-pull type output circuit for driving a plasma display or the like is integrated.

[0002]

2. Description of the Related Art FIG. 5 shows an output circuit per dot in an example of a plasma display panel driving IC. An output terminal DO of a data driver IC 51 and an output terminal DO of a scan driver IC 52, which form a push-pull type driver IC, are connected to both ends of a discharge tube 53 which is a display cell. The output circuits of the driver ICs 51 and 52 are n
It is a push-pull type in which channel MOSFETs are connected in series, and an output terminal DO is taken out between these two MOSFETs (N1 and N2, N3 and N4) connected in series. Elements connected to the high potential terminals (power supply terminals: VDH) of the power supplies 54 and 55 are high-side elements (here, N2 and D2 and N4 and D4 are referred to), and the power supply 5
Elements connected to the low-potential terminals (ground terminals: GND) of the reference numerals 4, 55 are called low-side elements (here, N1 and D1 and N3 and D3 are referred to). Data driver IC5
In No. 1, a high-side diode D2 and a low-side diode D1 are connected in parallel to the high-side transistor N2 and the low-side transistor N1, respectively. A high side diode D4 and a low side diode D3 are connected in parallel to the high side transistor N4 and the low side transistor N3 of the scan driver IC 52, respectively. Incidentally, the diodes D2, D1, which are connected in parallel,
D4 and D3 are parasitic pn diodes.

Signals from the control circuits 56 and 57 turn on and off the high side transistors N2 and N4 and the low side transistors N1 and N3 to output the output terminal D.
A general method is to control the potential of O to charge and discharge the display cell 53 to emit light. FIG. 6 shows a data driver IC5
FIG. 3 is a cross-sectional view of essential parts in the case where the high side transistor N2 and the low side transistor N1 in the output section of No. 1 are constituted by a CMOS structure. In the following description, layers and regions having n and p crowns mean layers and regions in which electrons and holes serve as majority carriers, respectively.

Usually, a CMOS structure (Complimen) is used.
n-channel MOSFET, p-channel MOS
The structure of the FET and the n-channel MOSFET) is formed by forming the n-well region 102 in the surface layer of the p-type semiconductor substrate 101 and p-type in the surface layer of the n-well region 102.
^{The +} source region 103 and the p ⁺ drain region 104 are formed, and the n ⁺ region 10 is in contact with the p ⁺ source region 103.
5, the gate electrode 107 is formed on the n well region 102 sandwiched between the p ⁺ source region 103 and the p ⁺ drain region 104 via the gate insulating film 106, and on the p ⁺ source region 103 and the n ⁺ region. Source electrode 108 on 105
Is formed, a drain electrode 109 is formed on the p ⁺ drain region 104, and a p-channel high-side transistor N2 is formed. On the other hand, the n ⁺ source region 110 and the n ⁺ drain region 11 are formed on the surface layer of the p-type semiconductor substrate 101.
1 is formed, p ⁺ region 112 in contact with n ⁺ source region 110 is formed, via the n ⁺ source region 110 and n ⁺ drain region 111 and the gate insulating film 113 on the p-type semiconductor substrate 101 sandwiched between the A gate electrode 114 is formed, a source electrode 115 is formed on the n ⁺ source region 110 and the p ⁺ region 112, and a drain electrode 116 is formed on the p ⁺ drain region 111 to form an n-channel low-side transistor N1. Is formed. The source electrode 108 of the high side transistor N2 is connected to the power supply VDH, and the drain electrode 109 of the high side transistor N2.
And the drain electrode 116 of the low-side transistor N1 are connected to the output terminal DO, and the source electrode 115 of the low-side transistor N1 is connected to the ground terminal GND.

[0005]

As shown in FIG. 6, in this structure, a parallel diode D1 is formed between the output terminal DO and the ground terminal GND by the p-type semiconductor substrate 101 and the n ⁺ drain region 111. , The n-well region 102 and the p ⁺ drain region 104 form a parallel diode D2 between the output terminal DO and the power supply terminal VDH, and the ground terminal GND and the high-side transistor N2 connected to the output terminal DO are connected to each other. In between, the p ⁺ drain region 10
4, the n-well region 102 and the p-type semiconductor substrate 101 form a parasitic pnp transistor T1.

FIG. 7 shows one of the circuits shown in FIG. 5, and shows an equivalent circuit in which a parasitic pnp transistor is connected to the high side diode D2. The emitter and base of the parasitic pnp transistor T1 are connected in parallel with the high side diode D2 as shown by the dotted line. Data driver I shown in FIG.
The output terminals DO of the C51 and the scan driver IC 52 are connected to the discharge tube 53 and electrically capacitively coupled. Therefore, depending on the charging / discharging timing of the discharge tube 53, the potential of the output terminal DO may be higher than that of the power supply terminal VDH. In that case, as shown in FIG. A current Id flows through the power supply terminal VDH via the via.

As described above, in the data driver IC 51, when the potential of the output terminal DO becomes higher than the power supply terminal VDH, the current Id flows from the output terminal DO to the power supply terminal VDH through the high side diode D2. Part of this current Id becomes the base current of the parasitic pnp transistor T1 and the collector current of the parasitic pnp transistor T1 becomes a large value obtained by multiplying this base current by the current amplification factor of the parasitic pnp transistor T1. It becomes a parasitic current Il and flows out. When the parasitic current Il is large, the power consumption increases and the data driver IC51 generates heat. Further, if the parasitic current Il becomes excessive, the data driver IC 51 may be destroyed. Of course, the same phenomenon also occurs in the scan driver IC 52.

An object of the present invention is to solve the above-mentioned problems and to use a parasitic pn diode current as a base current to generate a parasitic p
It is an object of the present invention to provide a semiconductor device in which a parasitic current flowing due to the operation of an np transistor is reduced, heat generation is small, and thermal breakdown does not easily occur.

[0009]

In order to achieve the above object, a first region of a first conductivity type and a second region of a second conductivity type are selectively formed on a semiconductor substrate of a first conductivity type. And a third region of the second conductivity type and a fourth region of the first conductivity type are separated and selectively formed in the surface layer of the second region,
A fifth region of the first conductivity type and a sixth region of the second conductivity type are respectively formed in the surface layer of the fourth region, and on the first region, the third region, the fifth region and the sixth region. A first electrode, a third electrode, a fifth electrode and a sixth electrode are respectively formed,
The diode and the electrode and the sixth electrode are connected by a conductor.

A sixth region may be formed in contact with the fifth region, and an eighth electrode common to the fifth region and the sixth region may be formed. Further, a sixth region is formed in contact with the fifth region so as to surround the fifth region,
It is also effective to form a common ninth electrode on the fifth region and the sixth region.

Further, a first region of the first conductivity type and a second region of the second conductivity type are selectively formed on the semiconductor substrate of the first conductivity type, and the second conductivity type is formed on the surface layer of the second region. The third
The region and the fourth region and the seventh region of the first conductivity type are respectively separated and selectively formed, and the surface layer of the fourth region is in contact with the fifth region of the first conductivity type, and the region of the second conductivity type is formed. A sixth region is formed, a seventh electrode (source electrode) is formed on the seventh region, and a second region is sandwiched between the seventh region and the fourth region with an insulating film (gate insulating film) interposed therebetween. 10 electrodes (gate electrode)
Are formed, and the first electrode and the third electrode are formed on the first region and the third region.
MOSFET in which electrodes are respectively formed and an eighth electrode (drain electrode) common to the fifth region and the sixth region is formed
May be

A first region of the first conductivity type and a second region of the second conductivity type are selectively formed on the first conductivity type semiconductor substrate, and the second conductivity type is formed on the surface layer of the second region. The third region and the fourth and seventh regions of the first conductivity type are separately formed and selectively formed, and the first layer is formed on the surface layer of the fourth region.
A fifth region of conductivity type is formed, a seventh electrode (emitter electrode) is formed on the seventh region, and an insulating film (gate insulating film) is formed on the second region sandwiched between the seventh region and the fourth region. A tenth electrode (gate electrode) is formed through the third electrode
A first electrode and a third electrode are formed on the area, and
A first insulated gate bipolar transistor (IGBT) in which an eighth electrode (collector electrode) is formed in a region, and a second conductivity type 31st region and a first conductivity type 41st region in a surface layer of the second region. The region and the 71st region are separated from each other and selectively formed, and the 61st region of the 2nd conductivity type is formed in contact with the 51st region of the 1st conductivity type on the surface layer of the 41st region. A 71st electrode (source electrode) is formed on the region, and a 101st electrode (gate electrode) is formed on the second region sandwiched between the 71st region and the 41st region via an insulating film (gate insulating film). , A 31st electrode is formed on the 31st region, an 81st electrode (collector electrode) common to the 51st region and the 61st region is formed, and a 101st electrode and a 71st electrode are connected to each other. Insulated gate bipolar transistor (IGBT) But parallel connection (in this case, the source electrodes are connected collector electrodes are respectively, the gate electrodes each other refers to a state of not being connected) may be configured to be.

With the above structure, when the semiconductor device is used for a capacitive load such as a plasma display, the first conductivity type semiconductor substrate and the second conductivity type semiconductor substrate are provided.
A parasitic current flowing through the parasitic transistor formed by the region and the fourth region can be reduced. The reason is that the sixth region is formed in the fourth region, and the second region and the fourth region are formed.
A load transistor is formed in the region and the sixth region, and the base current of the parasitic transistor partially flows through the load transistor, so that the parasitic current is reduced. Further, for example, when the first conductivity type is p-type and the second conductivity type is n-type, n is formed on the surface layer of the p-drain region of the p-channel MOSFET of CMOS.
By forming the ⁺ region, the parasitic current can be reduced. Further, the p-channel MOSFET is replaced by connecting two p-channel IGBTs (insulated gate bipolar transistors) in parallel, and the gate electrode and the source electrode of one IGBT are short-circuited to function as an IGBT. I kill it and use it as a diode.
By operating the GBT as an IGBT,
The current capacity can be made larger than in the case of T.

The connection with a push-pull type output circuit such as a plasma display in which the above-mentioned parasitic current is a problem is
As described in the prior art, the output terminal DO of the push-pull type output circuit is connected to the conductor connecting the fifth electrode and the sixth electrode, and the low potential terminal GND of the power source is connected to the first electrode. This is a case where the high potential terminal VDH is connected to the third electrode.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of the essential parts of a first embodiment of the present invention. This figure shows a high-side diode (parasitic diode D2) formed in parallel with a high-side transistor of a semiconductor device integrating a push-pull type output circuit.
Sectional drawing of a part is shown. First on the surface layer of the p-type silicon substrate 1.
An n ⁻ well region 3 is formed by diffusion or the like on the surface layer of the p-type silicon substrate 1 so as to be separated from the p ⁺ region 2 and the first p ⁺ region 2, and n ⁻
A p region 4 and a first n ⁺ region 5 are formed on the surface layer of the well region 3, and a second n ⁺ region 6 and a second p ⁺ region 7 are formed on the surface layer of the p region 4. The 1p ⁺ on area 2, to a 1n ⁺ region on the 5 to form a first metal wiring 8 and the second metal wiring 9, common third metal wiring and the upper second 2p ⁺ region 7 and the upper first 2n ⁺ region 6 Form 10. Incidentally, the 2n ⁺ region 6 at the same time as the formation of the 1n ⁺ region 5 is also formed. In addition, each metal wiring 8,
After forming 9 and 10, a surface protective film such as a P-CVD film is formed on the exposed silicon.

The low-potential terminal GND of the power supply of the push-pull type output circuit is connected to the first metal wiring 8, the high-potential terminal VDH of the power supply is connected to the second metal wiring 9, and the output terminal D is connected.
O and the third metal wiring 10 are connected. In this structure,
As shown by an equivalent circuit, a parasitic pn diode D2 formed by the p region 4 and the n ^- well region 3 (parasitic means that the parasitic region is formed at the same time when other regions are formed. Is a diode that positively allows a current to flow and is essential for the circuit. At the same time, a parasitic pnp transistor formed by the p region 4, the n ^- well region 3 and the p-type silicon substrate 1 (this transistor is unnecessary) Is literally a parasitic diode)
Is present, and further, the second n ⁺ region 6, so as to short-circuit the base and collector of this parasitic pnp transistor T1,
An additional npn transistor T2 is formed in p region 4 and n ^- well region 3. Therefore, when the potential of the output terminal DO becomes higher than the high potential terminal VDH of the power source of the push-pull output circuit, the parasitic current Il flows through the parasitic pnp transistor T1. However, by forming the additional npn transistor T2, the base current of the parasitic pnp transistor T1 is absorbed as the collector current of the additional npn transistor, and the base current decreases. Further, from a different point of view, it can be said that the emitter injection efficiency of the parasitic pnp transistor T1 is suppressed by the additional npn transistor T2, and as a result the current amplification factor decreases. As a result, the parasitic current Il flowing from the output terminal DO through the parasitic pnp transistor T1 to the low potential terminal GND is reduced to 1/10 to 1/20 of that of the conventional structure, and the heat generation of the silicon chip is suppressed. To be done.

Here, the semiconductor device in which the push-pull type output circuit is integrated has been described as an example, but other semiconductor devices having a parasitic diode that is simultaneously formed when forming a power IC (integrated circuit) are also described. Of course it applies. FIG. 2 is a sectional view of the essential portions of the second embodiment of the present invention. The difference from FIG. 1 is that the second p ⁺ region 7 is in contact with and surrounded by the second n ⁺ region 6, and the third metal wiring 10 is p.
The exposed area of the n-junction and the p-region 4 are first n
⁺ It is the point surrounded by area 5. For the effect,
By short-circuiting the pn junction and surrounding the p region 4 by the first n ⁺ region 5, the emitter current of the additional npn transistor T2 is made easier to flow, thereby further increasing the above effect and reducing the parasitic current Il. .

FIG. 3 is a sectional view of the essential portions of the third embodiment of the present invention. In the surface layer of the n ^- well region 3, the p region 4 and the first n
^{The +} region 5 and the third p ⁺ region 21 are formed, and the second n ⁺ region 23 and the second p ⁺ region 24 are formed in contact with the surface layer of the p region 4 so as to contact the first n ⁺ region 5 and the third p ⁺ region. Second metal wiring 9 and fourth metal wiring 11 are formed on
^A common third metal wiring 10 is formed on the ⁺ region 6 and the second p ⁺ region 7. Further, a gate electrode 24 is formed on the surface of the n ⁻ well region 3 sandwiched between the third p ⁺ region 21 and the p region 4 via a gate insulating film 23, and a drain short type p channel MOSFE serving as a high side transistor.
Form T. When the output terminal DO of the push-pull output circuit becomes higher in potential than the high potential terminal VDH,
A second p ⁺ region 7, a p region 4 and an n ⁻ well region 3,
The emitter current of the parasitic pnp transistor T1 formed with the p-type silicon substrate 1 is controlled by the second n ⁺ region 6 and the p region 4
By bypassing with the additional npn transistor T2 formed in the n ^- well region 3, the base current of the parasitic pnp transistor T1 can be reduced and the parasitic current Il flowing through the p-type silicon substrate can be reduced.

FIG. 4 is a sectional view of the essential portions of the fourth embodiment of the present invention. The difference from FIG. 3 is that the p-channel MOSFET is replaced by two p-channel IGBTs. The same figure (a)
In the first IGBT shown in (1), the third metal wiring 10 which is the collector electrode is connected only to the second n ⁺ region 22 which is the collector region, and this IGBT is used as a high side transistor. On the other hand, the second IGB shown in FIG.
The third metal wiring 10a, which is a collector electrode, is commonly connected to the second n ⁺ region 27, which is a collector region, and the second p ⁺ region 28, which is a high-concentration layer in the base region.
Is connected to the fourth metal wiring 11a, which is an emitter electrode,
The p-channel MOSFET does not function as a MOSFET but functions similarly to the above-mentioned parasitic diode D2 and constitutes a diode necessary for the circuit. Fourth metal wiring 11 and second IGBT as emitter electrode of first IGBT
The fourth metal wiring 11a serving as the emitter electrode of T is connected to the second metal wiring 11 serving as the collector electrode of the first IGBT and the second metal wiring serving as the emitter electrode of the second IGBT.
The metal wiring 11a is connected. That is, the first IGB
T and the second IGBT are connected in parallel. The third metal wirings 10 and 10a, which are collector electrodes, are connected to the output terminal DO of the push-pull type output circuit, and the second metal wirings 9 and 9a are connected.
And the fourth metal wirings 11 and 11a, which are emitter electrodes, are connected to the high potential terminal VDH of the power source, and the first metal wiring 8 is connected to the low potential terminal GND of the power source.

In this structure, the high-side transistor can have a larger current capacity than the MOSFET of FIG. 3 in the first IGBT. The high side diode is a parasitic diode, and the second IGBT plays its role. Then become structure first 2n ⁺ region 27 is the collector region is short-circuited at the 2p ⁺ region 28, by forming the first 2p ⁺ region 28, although the parasitic pnp transistor is formed, the 2n ⁺ The additional transistor T2 is formed in the region 23, and the parasitic current Il flowing through the parasitic pnp transistor is formed.
Is suppressed. The second IGBT is structurally similar to the p-channel MOSFET of FIG. Further, in this example, the n ⁻ well region 3 is common, and the first and second IGBTs are formed therein. At this time, of course, the first n ⁺ regions 5 and 5a may be common.

[0021]

According to the present invention, when the high side transistor is formed of a p-channel MOSFET,
By providing an n ⁺ region in the p ⁺ drain region of the channel MOSFET and connecting these regions with a conductor, additional np
An n-transistor is formed to reduce the parasitic current. In addition, the high-side transistor is a p-channel MOSFET
In order to reduce the parasitic current, the same function as the additional npn transistor is performed. Furthermore, p-channel MOSF
By connecting two p-channel IGBTs in parallel instead of ET and using one as a diode and the other as an IGBT, the current capacity can be made larger than that of the MOSFET.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of a first embodiment of the present invention.

FIG. 2 is a sectional view of a main part of a second embodiment of the present invention.

FIG. 3 is a sectional view of the essential parts of a third embodiment of the present invention.

FIG. 4 is a sectional view of the essential parts of a fourth embodiment of the present invention.

FIG. 5 is an output circuit diagram per dot in an example of a plasma display panel driving IC.

FIG. 6 is a sectional view of a main part of a conventional structure.

FIG. 7 shows a parasitic p on the high side diode D2 in the conventional structure.
Equivalent circuit diagram with np transistor connected

[Explanation of symbols]

1 p-type semiconductor substrate 2 first p ⁺ region 3 n ^- well region 4 p region 5 first n ⁺ region 6 second n ⁺ region 7 second p ⁺ region 8 first metal wiring 8a first metal wiring 9 second metal wiring 9a 2 metal wiring 10 third metal wiring 10a third metal wiring 11 fourth metal wiring 11a fourth metal wiring 12 gate electrode 21 third p ⁺ region 22 second n ⁺ region 23 gate insulating film 24 gate electrode 25 gate insulating film 26 gate electrode 27 third n ⁺ region 28 fourth p ⁺ region 51 data driver IC 52 scan driver IC 53 discharge tube 54 power supply 55 power supply 56 control circuit 57 control circuit 101 p-type semiconductor substrate 102 n-well region 103 p ⁺ source region 104 p ⁺ drain region 105 n ⁺ region 106 gate insulating film 107 gate electrode 108 source electrode 109 drain electrode 110 n ⁺ source region 111 n ⁺ drain region 112 p ⁺ region 113 gate insulating film 114 gate electrode 115 source electrode 116 drain electrode GND ground terminal DO output terminal VDH power supply terminal T1 parasitic pnp transistor T2 additional npn transistor D2 high side diode Il parasitic current D1 low side diode D2 high Side diode D3 Low side diode D2 High side diode N1 Low side transistor N2 High side transistor N3 Low side transistor N4 High side transistor

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-3-155156 (JP, A) JP-A-62-217664 (JP, A) JP-A-5-283622 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 29/861 H01L 29/78 H01L 27/08 H01L 27/06 H01L 29/73

Claims (5)

(57) [Claims] 1. A first conductivity type first region and a second conductivity type second region are selectively formed on a first conductivity type semiconductor substrate, and a second conductivity type is formed on a surface layer of the second region. The third region and the fourth region of the first conductivity type are separated and selectively formed, and a fifth region of the first conductivity type and a sixth region of the second conductivity type are formed on the surface layer of the fourth region. Are formed respectively, and a first electrode, a third electrode, a fifth electrode and a sixth electrode are respectively formed on the first region, the third region, the fifth region and the sixth region,
A diode in which the fifth electrode and the sixth electrode are connected by a conductor.
There is a semiconductor device. 2. A sixth region is formed in contact with the fifth region,
The semiconductor device according to claim 1, wherein a common eighth electrode is formed on the fifth region and the sixth region. 3. A sixth region is formed in contact with the fifth region so as to surround the fifth region, and a common ninth electrode is formed on the fifth region and the sixth region. Claim 1
The semiconductor device described. 4. A first conductivity type first region and a second conductivity type second region are selectively formed on a first conductivity type semiconductor substrate, and a second conductivity type is formed on a surface layer of the second region. Of the first conductivity type and the fourth region and the seventh region of the first conductivity type are respectively separated and selectively formed, and the surface layer of the fourth region is in contact with the fifth region of the first conductivity type, A sixth region of conductivity type is formed, a seventh electrode is formed on the seventh region, and a seventh region and a fourth region are formed.
A tenth electrode is formed on a second region sandwiched by the region and an insulating film, a first electrode and a third electrode are formed on the first region and the third region, respectively. A semiconductor device comprising a MOSFET having an eighth electrode common to six regions. 5. A first conductivity type first region and a second conductivity type second region are selectively formed on a first conductivity type semiconductor substrate, and a second conductivity type is formed on a surface layer of the second region. The third region and the fourth region and the seventh region of the first conductivity type are respectively separated and selectively formed, and the fifth region of the first conductivity type is formed in the surface layer of the fourth region. A seventh electrode is formed on the region, a tenth electrode is formed on the second region sandwiched between the seventh region and the fourth region via an insulating film, and a tenth electrode is formed on the first region and the third region. A first insulated gate bipolar transistor in which a first electrode and a third electrode are respectively formed, and an eighth electrode is formed in a fifth region, and a second conductivity type thirty-first region and a first conductivity type thirty-first region in a surface layer of the second region. The 41st and 71st regions of the conductivity type are separated and selectively formed, and the first conductive layer is formed on the surface layer of the 41st region. In contact with the first 51 region of the form, the 61 region of the second conductivity type is formed, the first 71 electrode is formed 71 on the region, the second sandwiched between the first 71 region and 41 region
The 101st electrode is formed on the region through an insulating film,
The 31st electrode is formed on the 1st region, and the 51st region and the 61st electrode are formed.
An 81st electrode common to the region is formed, and a second insulated gate bipolar transistor in which the 101st electrode and the 71st electrode are connected is connected in parallel (the 7th electrode and the 71st electrode,
(The state where the 8th electrode and the 81st electrode are respectively connected)
A semiconductor device characterized by the following.