JP3439042B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit incorporating an output transistor for driving a load that generates a back electromotive force such as a coil load, and relates to prevention of a parasitic effect due to the back electromotive force.

[0002]

2. Description of the Related Art In an IC for a motor driver, an NPN transistor having a collector as an output terminal is used as one of the output transistors, and a transistor complementary to the NPN transistor is used as the other of the output transistors and is driven by a push-pull circuit. Is being done. A PNP transistor has been used as the transistor forming the complementary pair.
Type integrated circuits and P-channel MOSFETs have been used as the transistors forming the complementary pair.

Such a circuit is shown in FIG. In the figure,
1 is an NPN type output transistor, 2 is a P channel type MOS transistor, 3 is a coil load connected to the output terminal 4, 5 is an inverter circuit connected to the gate of the P channel type MOS transistor 2, 6 is an NPN transistor 1 is a drive circuit. The collector of the NPN transistor 1 is connected to the output terminal 4, the emitter is connected to the ground potential GND, and the source of the P-channel type MOS 2 is the power supply potential V.
The drain is connected to CC and the output terminal 4. A control signal of opposite phase is applied to the P-channel MOS 2 and the NPN transistor 1 by the inverter circuit 5 and the like, whereby one of the P-channel transistor 2 and the NPN transistor is turned on and the other is turned off, so that the coil load 3 is positively fed. Or apply a current in the opposite direction to drive the motor forward / backward.
It rotates in the opposite direction.

The structure of the two output transistors is shown in FIG. 11 is a P-type semiconductor substrate, 12 is an N-type epitaxial layer, 13 is an N + buried layer, 14 is a P + isolation region,
Reference numeral 15 is an epitaxial layer 12 partitioned by the isolation region 14.
Is an island region, 16 is a P-type base region, and 17 is N +
An emitter region, 18 is an N + collector lead-out region, 19 is a gate electrode, 20 is a source region, and 21 is a drain region. NPN transistor 1 collector lead-out region 18 and P
The drain region 21 of the channel MOS2 and the output terminal 4
To drive the coil load 3.

[0005]

However, in a coil load such as a motor, a reverse electromotive force is generated as the motor rotates / stops, and the potential of the output terminal 4 becomes higher than the VCC potential or lower than the GND potential. It is known. Therefore, when the output terminal 4 becomes higher than the VCC potential, the parasitic PNP transistor 23 having the drain region 21 as an emitter, the island region 15 of the P-channel MOS 2 as a base, and the substrate 11 as a collector, and the output terminal 4 having a GN
When the potential becomes lower than the D potential, the parasitic NPN transistor 22 having the island region 15 of the NPN transistor 1 as an emitter, the substrate 11 (isolation region 14) as a base, and the island region 15 of the P-channel MOS 2 as a collector operates to operate inside the IC. There were drawbacks such as malfunctions in and triggers of parasitic thyristors.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and surrounds the back gate portion of a P-channel MOS with a buried layer of one conductivity type and a diffusion region, and further around it. Is surrounded by a buried layer of a reverse conductivity type and a diffusion region, the reverse β of the parasitic transistor
To reduce the occurrence of parasitic effects.

Further, the problem of the parasitic effect is solved by establishing a potential connection for generating a parasitic transistor so that a leakage current does not occur in the substrate.

[0008]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view for explaining the first embodiment of the present invention. In the figure, 31 is P
Type silicon semiconductor substrate, 32 is an N type epitaxial layer formed on the substrate 31 by a vapor phase epitaxy method, 33 is an N + type buried layer formed by being buried in the surface of the substrate 31,
34 is a P + type isolation region that reaches the substrate 31 from the surface of the epitaxial layer 32 and separates the epitaxial layer 32 into a plurality of island regions 35; 36 is a P type base region of the NPN transistor 1 formed on the surface of the island region 35; 37 denotes an N + type emitter region formed on the surface of the base region 36, 3
8 is N reaching the N + buried layer 33 from the surface of the island region 35
+ Type collector lead-out region, 39 is a P + type buried layer formed so as to overlap the N + buried layer, 40 is a P + type lead region reaching the P + buried layer 39 from the surface of the island region 35,
41 is an N + lead-out region reaching the N + buried layer 33 from the surface of the island region 35, 42 is a gate electrode of the P-channel MOS 2, 43 is a back gate formed of an N-type layer surrounded by the P + buried layer 39 and the P + lead-out region 41, 44 is a P-type source region diffused and formed beside the gate electrode 42, 45 is a P-type drain region similarly diffused and formed beside the gate electrode 42, and 46 is an N + contact region for the back gate. The P + lead-out region 40 completely surrounds the P-channel MOS 2, and the back gate 4 together with the P + buried layer.
Electrically isolate 3. An N + derivation region 41 surrounds the P + derivation region 40 further outside.

According to the circuit diagram of FIG. 1 , the emitter region 3 of the NPN transistor 1 is connected by aluminum electrode wiring on the IC.
7 is applied to the ground potential GND, and the power supply potential VCC is applied to the back gate contact region 46 and the source region 44 of the P-channel MOS 2. The collector lead-out region 38 of the NPN transistor 1 is connected to the output terminal 4 (bonding pad) on the IC, and the drain region 45, the P + lead-out region 40, and the N + lead-out region 41 of the P-channel MOS 2 are connected.
Are connected to the output terminal 4. The output terminal 4 is connected to the connection lead outside the package, and is connected to the coil load 3 on the set side. The ground potential GND is applied to the substrate 31 and the isolation region 34.

Since the parasitic transistor 22 described in FIG. 5 uses the isolation region 14 as a base and the back gate 15 as a collector, the P + lead-out region 40 and the N + lead-out region 41 are located between the collector and the base in this structure. It will be. Since the P + lead-out region 40 and the N + lead-out region 41 are connected to the output terminal 4 and have the same potential as the collector lead-out region 35, the parasitic transistor 22 can be prevented from being generated.

[0011] The parasitic transistor 23 described in FIG. 5
Since the back gate 43 serves as the base and the substrate 31 serves as the collector, the P + buried layer 39 and the N + buried layer 33 (P + lead-out region 40 and N + lead-out region 41 in the lateral direction) are provided between the base and the collector in this structure. ) And will be located. Similarly, since the P + buried layer 39 and the N + buried layer 33 are connected to the output terminal 4 and have the same potential as the drain region 45, the parasitic transistor 22 can be prevented from being generated.

In addition, the PN junction between the back gate 43 and the P + lead-out region 40 / P + buried layer 39 is connected as the protection diode 46 between the VCC potential and the output terminal 4. Since the PN junction of the protection diode 46 can be a PN junction having a small forward-direction rising voltage Vf due to the high-concentration anode region, it is possible to provide the IC with built-in characteristics as much as possible, instead of the protection diode which is conventionally attached externally.

FIG. 2 is a sectional view for explaining the second embodiment of the present invention. The same parts as those in the previous embodiment are denoted by the same reference numerals and the description thereof will be omitted. Whereas the first mode is the potential connection that does not generate the parasitic transistor, the second mode allows the parasitic transistor not involving the substrate 31 to cancel the energy of the backward electromotive force. .

Specifically, the ground potential (GND) is supplied to the P + derivation region 40, and the power supply potential (VCC) is supplied to the N + derivation region 41.
Was applied. In such a configuration, first, when the output terminal 4 is pulled to a potential lower than the ground potential (GND), the island region 35 of the NPN transistor 1 serves as an emitter, the isolation region 34 serves as a base, and the island region 35 in which the P-channel MOS 2 is formed is formed. A parasitic transistor serving as a collector is generated, and a current flows from the N + lead-out region 41 to the N + collector lead-out region 38 by a path indicated by an arrow 50. This parasitic current absorbs the energy of the reverse electromotive force of the inductive load L. Conversely, when the output terminal 4 is pulled to a potential higher than the power supply potential VCC, P +
A parasitic transistor having the lead-out region as the collector, the back gate 43 as the base, and the drain region 45 as the emitter is generated, and the parasitic current flows through the path indicated by the arrow 51. This parasitic current absorbs the energy of the reverse electromotive force of the inductive load L. Inside the integrated circuit, the PNP or NPN transistor has a faster switching speed than the PN junction diode.

Therefore, compared with the first embodiment, the second embodiment restores the inductive load L to a stable state by the current of the parasitic transistor, which has the merit that the switching speed of the inductive load can be made higher. At this time, since a parasitic current is positively flown from the P-channel MOS 2 to the NPN transistor 1, the block of the P-channel MOS 2 is interposed between the block of the small signal circuit and the block of the small signal circuit as shown in FIG.
A design method such as arranging a block of the NPN transistor 1 next to it may be adopted.

[0016]

As described above, according to the present invention, the P + lead-out region 40 and the N + lead-out region 41, the P + buried layer 39 and the N + buried layer 33 are formed between the back gate 46 and the substrate 31. Is connected to the output terminal 4, there is an advantage that parasitic transistors 22 and 23 can be prevented from being generated with respect to the reverse electromotive force of the coil load 4.

In addition, since an unavoidable PN junction can be built in as the protection diode 46, there is an advantage that the number of external parts can be reduced. Further, according to the second embodiment, since the inductive load is returned to the stable state by the operating current of the parasitic transistor, there is an advantage that higher speed switching is possible.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the present invention.

FIG. 4 is a circuit diagram for explaining a conventional example.

FIG. 5 is a cross-sectional view for explaining a conventional example.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8234-21/8238 H01L 27/06-27/092

Claims (7)

(57) [Claims] 1. A semiconductor substrate of one conductivity type, a reverse conductivity type epitaxial layer formed on the substrate, and a separation region of one conductivity type that separates the epitaxial layer to form a plurality of island regions. A reverse-conductivity-type buried layer that is buried and formed on the surface of the substrate in the island region; a single-conductivity-type buried layer that is buried and formed so as to overlap the buried layer; Reaching a region of one conductivity type, and a source / drain region of one conductivity type and a gate electrode formed on the surface of the region of the opposite conductivity type surrounded by the region of one conductivity type and the buried layer of the one conductivity type. And a means for connecting a drain region of the output transistor to an output terminal . 2. The drain region is connected to the one conductivity type region, and the drain region is connected to the island region between the one conductivity type region and the isolation region. Item 2. The semiconductor integrated circuit according to item 1. The 3. A minimum potential in the region of the one conductivity type, the island region between the one conductivity type region and the isolation region top
The semiconductor integrated circuit according to claim 1, wherein a high potential is applied to each. 4. A semiconductor substrate of one conductivity type, a reverse conductivity type epitaxial layer formed on the substrate, and a separation region of one conductivity type that separates the epitaxial layer to form a plurality of island regions. A first output transistor having one island region as a collector, a base region of one conductivity type formed on the surface of the island region as a base, and an emitter region of the opposite conductivity type formed on the surface of the base region as an emitter; A buried layer of opposite conductivity type buried in the surface of the substrate in another island region, a buried layer of one conductivity type buried in the buried layer, and a conductive layer from the surface of the other island region. -Conductivity type source / drain formed on the surface of the one-conductivity-type region reaching the buried-type layer and the opposite-conductivity-type region surrounded by the one-conductivity-type region and the one-conductivity-type buried layer. A second output transistor comprising a region and a gate electrode, means for connecting the collector of the first output transistor to the output terminal, and means for connecting the drain region of the second output transistor to the output terminal. A semiconductor integrated circuit, comprising: 5. The drain region is connected to the one conductivity type region, and the drain region is connected to the other island region between the one conductivity type region and the isolation region. The semiconductor integrated circuit according to claim 4 . 6. The method of claim 4, wherein the minimum potential to the one conductivity type region, and each application of maximum potential on the other island region between the one conductivity type region and the isolation region The semiconductor integrated circuit described. 7. The semiconductor integrated circuit according to claim 1, wherein the output terminal is connected to an inductive load.