JPS60223322A - Cmos semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To attain high speed, low power consumption and high circuit integration by applying an input signal to a gate of the 2nd conduction type MOSFET, applying its input signal to the 1st conduction type well layer with a prescribed time of delay so as to activate a parasitic bipolar transistor existing in the 2nd conductor type MOSFET as an active element. CONSTITUTION:When an input signal Vin changes from a low level to a high level, a voltage at an output terminal (b) of a CMOS inverter IV1 changes from a high level to a low level, and a voltage at a terminal (d) via a delay circuit 8 comprising inverters IV2, IV3 changes from a high level to a low level. When the input signal Vin changes from the high level to the low level, the voltage at the output terminal (b) of the CMOS inverter IV1 changes from the low level to the high level. Thus, a voltage is impressed between a gate and a base of an N- channel MOSFETN1, which is turned on and a floating capacitance CL is charged. The N-channel MOSFET is driven in high speed with higher current drive capability than a P-channel MOSFET.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a technology that is particularly effective when applied to an 0MO8 (complementary insulated gate field effect transistor) semiconductor integrated circuit device, such as an output buffer in a CMO8 semiconductor integrated circuit device. It relates to techniques that are effective for use in circuits.

[Background technology]

Digital circuits using MOSFETs (insulated gate field effect transistors) have the drawback of low current drive capability due to current saturation due to pinch-off voltage.To compensate for this drawback, MOSFETs and bipolar transistors are formed on the same substrate together. It is possible to do so. However, when formed in this way, either the manufacturing process becomes extremely complicated or the characteristics of the device must be sacrificed. For example, 0MO8 using a P-type well layer
There is a known technology for forming an NPN transistor based on the P-type well layer using the process described above (
(Refer to Japanese Patent Application Laid-Open No. 57-130461). In this case, C
, P-type sea urchin A'N is 2 to 4 μmK due to MOS performance.
be done. Along with this, the base width of the NPN pibo-2 transistor also becomes 2 to 4 μm, resulting in poor transistor characteristics such as hFE and fT. Furthermore, the area of the bipolar transistor becomes large due to limitations such as photomask alignment margins.

[Purpose of the invention]

The purpose of the present invention is to provide a CMO8 with high speed and low power consumption, high current drive capability, and high integration.
The present invention provides a semiconductor integrated circuit cover.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows.

That is, in a CMO8 circuit having a P-type well layer on an N-type semiconductor substrate, an input signal is supplied to the gate of an N-channel MO8FET, and the input signal is delayed for a certain period of time to be applied to the parasitic bipolar transistor of the N-channel MO8FET. This parasitic bipolar transistor operates as an active element and has high current drive capability, achieving high speed and low power consumption.
8 semiconductor integrated circuit device.

Example 1] Figure 1 shows an N-type well layer formed on an N-type substrate.
FIG. 3 is a cross-sectional view of a channel MO8FET.

In the figure, Ml is an N-channel MO8FET. 1 is an N-type substrate, 2 is a field oxide film, and 3 is a P
1-04 is an N1 type semiconductor layer which is mounted on the source/drain of MO8FETM, and 5 is a P''' type semiconductor layer. 6 is a polysilicon layer forming a gate electrode, and 7 is a gate insulating film.

In this state, as shown in the figure, the parasitic bipolar transistor Q1. Q2 exists. Generally, this parasitic NPN bipolar transistor did not operate because the P-type well layer power supply terminal B was fixed at a low potential (ground power supply zero volts). In this embodiment, a signal having the same polarity as the signal supplied to the gate of the N-channel MO8FETM is delayed by a delay circuit 8 and is supplied to the terminal B as shown in FIG. In this case, the collector terminal C is
Connect to high potential vDD (5 volts) at CMOS level.

[Embodiment 2] FIG. 3 shows a circuit diagram in which the composite element of the N-channel MO8FET and NPN bipolar transistor is applied to an output buffer circuit in a CMO8 semiconductor integrated circuit.

As shown in FIGS. 1 and 2, the terminal C in FIGS. 1 and 2 is connected to the power supply voltage VDD, the I terminal E is connected to the output terminal e, and the gate terminal G is connected to the terminal bKi. This terminal is for CMO
It is coupled to the input terminal a via one stage of the S inverter (V). In addition, this terminal is coupled to a terminal C via a CMOS inverter
It is coupled to terminal d via inverter IV3. The CMOS inverter Iv2 and the inverter V3 constitute the delay circuit 8 described in FIG. 2 above. Furthermore, in the same figure, M2 is an N-channel type MO8FET, whose source is at the ground potential point of the circuit, and whose gate is
The terminal C has its drain coupled to the output terminal e. Although not particularly limited, CMOS inverter IV and CMOS inverter IV2 . IV is approximately 1/2 of the power supply voltage VDD
It is made to have a threshold voltage of .

Input terminal a is connected to signal wiring inside the semiconductor integrated circuit, and output terminal e is connected to a bonding pad, wire, LSI
Connected to signal wiring on an external circuit mounting board via the package. The capacitance CL indicates the capacitance it floating in those signal wirings. This capacitor CL is charged and discharged when the voltage at the output terminal e changes from a low level to a high level, or from a high level to a low level. In order to perform this operation at high speed, the element that drives the output terminal e needs to have the ability to drive a large current.

FIG. 4 is an operational waveform diagram for explaining the operation of the output buffer circuit shown in FIG. 3.

Next, the operation will be explained using this waveform diagram.

When the input signal Vin changes from low level to high level, the voltage at the output terminal d of the CMOS inverter IV changes from high level to low level. The voltage changes from high level to low level. As a result, the transistor Q1*Q21MOSFETR44 is turned off. At this time, N-channel MO8FETM! A high-level potential is supplied to the gate of □, which turns it on. Therefore, the charge in the floating capacitance CL is discharged through the N-channel MOsFETM, and the output signal V. u
l changes from high level to low level. Conversely, when the input signal Vin changes from high level to low level, C
The voltage at the output terminal of MOS inverter IV changes from low level to high level. At this time, the voltage at the terminal d via the delay circuit 8 formed by the CMOS inverters IV, , IV is still at a low level. Therefore, a voltage is applied between the gate of the N-channel MO8FETM and the substrate, and the N-channel MO8FETM+ is turned on and the stray capacitance CL begins to be charged. N channel MO8
The FET has a higher current drive capability than the P-channel MO8FE'r, so it operates at high speed. As the voltage at the output terminal e increases, the N-channel MO8FETM,
The equivalent resistance of increases and the voltage does not rise above a certain level.

However, the CMOS inverter IV forming the delay circuit 8.

When the terminal d changes from the low level to the /% high level via IV, the NPN transistor Q+ -Q2 turns on, and the voltage at the output terminal e becomes a voltage one step lower than the power supply voltage VDD by the transistor level shift amount ■□ It can be strongly pulled up to. ' Also, TT which becomes a load on the output terminal e
Even if the input terminals such as L are connected and the load current is applied to the input terminal, NP
N) The voltage at the output terminal e is maintained at a high voltage due to the high current drive capability of the transistor.

〔effect〕

(1)0 with a P-type well layer on an N-type semiconductor substrate
In the M03 circuit, an input signal is supplied to the gate of the N-channel type MO8FET, and the input signal is further supplied to the gate of the N-channel type MO8FET.
O8FET parasitic (by supplying the above input signal to the Ibora transistor with a certain time delay and operating this parasitic bipolar transistor as an active element,
Since the N-channel type MO8FET does not operate at high speed and the parasitic (Ibora) transistor performs high current drive, it is possible to form an output buffer circuit with high speed and low power consumption.

(2) By forming an N-channel MO8FET and an NPN bipolar transistor in the same area in the 0M08 circuit described above, it is possible to form an output buffer circuit with high current drive capability and high integration for the same reason as above. This effect can be obtained.

Although the invention made by the present inventor has been specifically explained above based on examples, it is to be understood that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. Not even. For example, similar effects can be obtained by using the composite element of the present invention in a circuit for driving long wiring inside an LSI.

Field of Application] According to the present invention, it can be widely applied to an output cover sofa circuit in a semiconductor integrated circuit device configured with complementary MO8FETs.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor integrated circuit device to which the present invention is applied. FIG. 2 is an equivalent circuit diagram of FIG. 1. FIG. 3 is a circuit diagram of an output buffer circuit using the composite element of the present invention. FIG. 4 is an operation waveform diagram for explaining the operation of FIG. 3. 1... N-type substrate, 2... Field oxide film, 3...
・P-type well region, 4...N? layer Tsukuda area, 5...P'
"Layer region, 6... Gate electrode, 7... Gate oxide film, 8... Delay circuit, B... Base, E... Emitter, C... Collector, G... Gate input , Ml, M
t...N channel type MO8FET, Ql-Qh...
・NPN bipolar transistor, IV, ~IV,
・CMOS inverter, agent accountant Takahashi
Meiji University Figure 1 Figure 2 Figure 4 eLt

Claims (1)

[Claims] 1. In a complementary insulated gate field effect transistor having a well layer of a second conductivity type on a semiconductor substrate of a second conductivity type, an input signal is supplied to a gate electrode of a second conductivity type MO8FET, and the input signal is By supplying M to the well layer of the first conductivity type with a certain time delay, the second conductivity type M
A CMO8 semiconductor integrated circuit device characterized in that a parasitic bipolar transistor existing in an O8FET operates as an active element.