JPS61244121A - Output circuit - Google Patents

Abstract

PURPOSE:To invert the voltage at an output terminal securely within a permissible transient period by making the large-small relation among channel conductance values of field effect transistor (FET) coincident with the large-small relation among time constants. CONSTITUTION:Inverters 13 and 14 perform inverting operation when the output signal SIN of a logical circuit 11 is inverted from a high level to a low level (time t1), and the output terminal voltages S'IN of the inverter 13 rises relatively steeply to turn on an N-MOS 15 immediately. The channel conductance of the N-MOS 15 is relatively small, so the voltage SOUT at an output terminal falls slowly. When the gate voltages S''IN of an N-MOS 16 exceeds its threshold value at time t2, the N-MOS 16 turns on and a current from a power source Vdd and a charge from the equivalent capacitance EC of a load circuit 23 are grounded through the source-drain current path of an Nth-MOS 16. The channel conductance of the N-MOS 16 is larger than that of the N-MOS 15, so the equivalent conductance between an output terminal 17 and an earth terminal Vss increases greatly through the inversion of the N-MOS 16 and the voltage SOUT at an output terminal 17 falls abruptly.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an output circuit, in particular, to an output circuit for an output signal representing a binary signal, and the present invention relates to an output circuit for outputting an output signal representing a binary signal, and the present invention relates to an output circuit for outputting an output signal representing a binary signal. The present invention relates to an improvement in an output circuit that prevents the occurrence of shoots or overshoots and also keeps the fall time or rise time of an output signal within a permissible range.

Conventional technology Figure w42 is a circuit diagram showing the configuration of a conventional output circuit.

In the figure, 1 is a logic circuit, for example, an adder circuit composed of a HAND circuit, etc., and the output terminal of the logic circuit 1 is connected to two complementary field effect transistors (hereinafter referred to as C-MOS).
) is connected to the input terminal of an inverter 2 consisting of a The output terminal of this inverter 2 is an N-type field effect transistor (
Below, it is connected to the gate of N-MOS')3,
Its source is connected to the ground terminal Vss, and its drain is connected to the output terminal 4 via the electrode Para 1, respectively.The output terminal 4 is connected to the input terminal of the load circuit 5, and the load circuit 5 There is a pull-up resistor 6 on the input terminal of
A power supply voltage Vdd is applied via.

Next, let EC be the equivalent capacitance of the load circuit 5, let ER be the power supply Vdd that stores the on-resistance of the N-MOS 3, and the equivalent resistance from the load circuit 5 to the ground terminal Vss, and let ER be the equivalent capacitance EC. The influence of the time constant TC determined by the resistance ER on the output signal 5OOT applied to the input terminal of the load circuit 5 is explained in the third section.
The explanation will be as follows with reference to the timing chart shown in the figure.

First, at time tl, the output signal SlN of the logic circuit 1
When flips from a high level to a low level, correspondingly,
Inverter 2 is inverted and its output signal S' 2N goes from low level to high level. Then, N-MOS
3 is turned on, and a radio wave path is formed from the power supply Vdd and the input terminal of the load circuit 5 to the ground terminal Vss.

Here, regarding the channel conductance of N-MOS 3, even if the equivalent capacitance EC is relatively large, not only the current supplied from the power supply Vdd but also the current from the stray capacitance accumulated in the load circuit 5 If this is chosen to be large enough to drain the charge, the output signal 5OUT will fall within the allowed fall time, as shown in FIG. However, even though the equivalent capacitance EC of the load circuit 5 is extremely small, N-
If the channel conductance of MOS 3 is selected to be a relatively large value as described above, the time constant TC becomes a significantly small value, and the current supplied from t [Vdd and the charge from the stray capacitance of the load circuit 5 suddenly increase. As a result, the output signal S'0tlT applied from the output terminal 4 to the input terminal of the load circuit 5 exceeds the ground voltage Vss and rapidly drops to a negative potential, causing an undershoot in the output signal S'OUT. do.

On the other hand, if a load circuit 5 with an extremely large equivalent capacitance EC is connected to the output terminal 4, the N-N053 cannot quickly discharge the charge from the stray capacitance of the load circuit 5, so the output signal S''OUT is changed at time t3. At this point, the voltage finally drops to approximately the ground voltage Vss.

<Problems with the prior art> In the conventional output circuit described above, the output signal S from the logic circuit 1
Since the firefly N-MOS 3 was opened and closed in response to lN and the voltages of the output signals SOU↑, S'OUT, and S''00 were controlled, the specifications of N-MOS 3 were not changed. The range of connectable load circuits 5 is extremely narrow, and in order to obtain an output signal 5OOT with good transient characteristics, the channel conductance of the N-MOS 3 must be redesigned to match the load circuit 5. there were.

Means for Solving the Problems〉 The major invention is the complexity of design changes in the above-mentioned prior art. ! In view of the point ll1I, a plurality of field effect transistors whose gates are commonly connected to the output signal generation circuit and whose source-drain current paths having different channel conductances can be formed in parallel between the ground terminal and the output terminal. , an output circuit is configured with a plurality of capacitors that are connected in parallel between each gate of the plurality of field effect transistors and a ground terminal, and have different time constants between the output signal generation circuit and each of the gates. The gist of the present invention is to match the magnitude relationship of the channel conductance of the field effect transistor to the magnitude relationship of the time constant.

When the output signal representing binary information is inverted, each of the plurality of field effect transistors responds by inverting the output signal with a small time constant between the output signal generation circuit and the gate of each of those transistors. The isometric conductance between the output terminal and the ground terminal, which is inverted sequentially, is initially a small value, but the channel conductance of each field-effect transistor is inverted sequentially. is larger than that of the field-effect transistor that was previously inverted, so the equivalent conductance increases step by step with the passage of time. As a result, when the capacitance added to the output terminal is small, the initial equivalent conductance is kept at a small value, suppressing sudden changes in the output terminal voltage and preventing undershoot, etc. When the capacitance added to is large, the equivalent conductance increases jumpily over time, suppressing the increase in the transient time, and enabling the output terminal voltage to be reversed within the allowable transient time. It is something.

Figure 1 shows the great invention -t! It is an electric circuit diagram showing an example,
In this embodiment, the output circuit according to the long-awaited invention is a logic circuit i! 8
11, etc., are integrated on a single semiconductor substrate 12. The output terminal of the logic circuit 11 is connected in parallel to the input terminal of an inverter 13.14 configured with C-MOS, and the output terminal of each inverter 13.14 is N-M.
Each is connected to the gate of OS 15.16,
The drains of the N-MOS 15, 16 are connected in parallel to the output terminal 17 via electrode bats, while the sources of each are connected to the ground terminal Vss. Here, N-M
The relationship between channel dimensions and conductance in the strongly inverted state of OS 15 and 16 will be explained in δ.

In general, the channel conductance g is calculated by dividing the channel width by W, the channel length by dividing the channel conductivity by 6(x
), and if the depth at which the channel disappears is xi, then it is expressed as follows. Although the channel conductivity 6(x) is proportional to the product of the channel carrier concentration and its mobility, in integrated circuits, since field effect transistors are simultaneously formed on the semiconductor substrate, the channel conductivity 6(x)
(x), the channel length is set to a fixed value, and the channel conductance of each field effect transistor is often changed by selecting the channel width W.
Therefore, in this embodiment integrated on the semiconductor substrate 12, the channel conductance of the N-MOS 15 and 16 is controlled by the channel width W, and the channel conductance of the N-MOS 113 is controlled by the channel width W.
- To select larger than that of MOS 15, N
-The full width of MOS 11+ is formed larger than that of N-MOS 15.

One 1R pole of the MOS capacitor 16 is connected between the inverter 14 and the gate of the N-MOS 16, and the other electrode of the capacitor 18 is connected fa#lA to the ground terminal Vss. On the other hand, inverter 13
No MOS capacitor is connected between the inverter 13 and the gate of the N-MOS 15.
There is only stray capacitance IPC due to the wiring between the gate of S15 and the gate of S15. Therefore, the capacitance connected to the gate of N-MOS 16 is larger than the capacitance connected to the gate of N-MOS 15, and the resistance values of wiring etc. are approximately equal L INN +7) 't', 'r'. /<-'7
14, the time setting MTC1 between N-MOS 18 is inverter 13. It becomes larger than the time constant TC2 between N-MOS 15. The output terminal 17 has an N-MOS for rapid discharge.
19(7) Drain also connected ratio, N-1110
The source of 919 is connected to the ground terminal Vss, and the gate is connected to the output terminal 17 via a Tll channel between the source and drain of N-1110820 for transfer gate.

The gate of the N-MOS 20 is connected to the output terminal of the inverter 13.
M09 *+ is also connected to one electrode of the MOS capacitor 21, and roughly the other electrode of the MOS capacitor 21 is connected to the ground terminal Vss. This MOS capacitor 21
Between the capacitor 281 and N
-1'lOS Time constant T determined from on-resistance of 20, etc.
The capacitance value is determined so that C3 is larger than the above-mentioned time constant TCI. Also, the channel width of N-MGS 19 is significantly larger than that of N-NOS 16, and time constant TC3 is chosen close to the maximum allowable fall time range.

A pull-up resistor 22 and a load circuit 23 are connected to the output terminal 17.
These are the same as the pull-up resistor 6 and load circuit 5 of the conventional example, so their explanation will be omitted.

Next, the operation of the embodiment according to the above configuration will be described below with reference to the timing chart of FIG. 4.

First, when the output signal SlN of the logic circuit 11 is inverted from high level to low level (time t1), each inverter 13.
14 is also inverted and the output terminal of inverter 13.14 goes from low level to high level, where the output terminal voltage S' IN of inverter 13 is equal to
Since there is no stray PCL in the wiring between 15 and 15, the voltage is turned off relatively quickly and the N-MOS 15 is immediately turned on. Thus, the equivalent capacitance EC of the power supply and load circuit 23 supplied from the power supply Vdd
The charge from N-MOS 10315 is immediately grounded through the source-drain current path of N-MOS 1
Since the channel conductance of the output terminal 5 is relatively small, the voltage 5OOT at the output terminal 17 drops slowly.

During this time, N-MGS 20 and N-MOS 15
However, because the time constant aTe3 is large, NJO919 remains in the off state.

Next, at time t2, when the gate voltage S''IN of the N-MGS 16 exceeds its threshold value, it also turns on, and the current from the power supply Vdd and the charge from the equivalent capacitance EC of the load circuit 23 are N-MGS 16 source
It is also grounded through the drain-to-drain 'Wt flow path. N-
The channel conductance of MOS16 is N-MGS
15, the equivalent conductance between the output terminal 17 and the ground terminal Vgs is N-MOS 16.
increases in a jumping manner due to the reversal of
OT drops rapidly. As a result, the voltage SOu↑ at the output terminal 17 becomes approximately the ground potential at time t3, and the inversion of the output signal 5OOT is completed within the allowable fall time.

Next, the operation when the equivalent capacitance EC of the load circuit 23 is extremely small will be described.

Even in this case, N-MOS 15.16 reversal time t2)
Regarding t3, there is no change, first of all, N-MOS 15
transitions to the on state. However, since the channel conductance of N-MOS 15 is small, the output signal S'
Although the voltage drop at OUT is a little faster than the output signal 5OOT mentioned above, it does not drop suddenly.
Since the voltage of the output signal S'0tjT has dropped to some extent after the N-MGS lft transitions to the on state and before the equivalent channel conductance increases dramatically, the output signal S' Even if the voltage at OUT suddenly drops, the drop will be small and no undershoot will occur.Additionally, in the above two operation examples (SOOT,
S'0UT), the inversion of the output signals 5OUT and S'OUT is completed before the N-MOS 19 turns on.

Next, we will explain the operation when the equivalent capacitance EC of the load circuit 23 is extremely large. In this case, even after the N-N0S 16 turns on and the equivalent conductance increases dramatically, Since EC cannot be fully discharged, the output signal S
”OUT remains at a high level. However, M
The charging of the OS capacitor 21 is completed, and as a result, N-
When MQS [ transitions to the on state, the equivalent conductance between the output terminal 17 and the ground terminal Vss increases exponentially, and the output signal S'' increases within the allowable range of the fall time.
The inversion of OUT ends (time t4).

Output signal SOO? The operation at the time of OUT is the same as that at the time of falling, so the explanation thereof will be omitted.

In addition, in the embodiment, the output circuit is formed by two sets of inverters and N-MOSs in parallel with each other, and therefore three or more sets of such inverters and N-MOSs are used. It may be provided.

Effect> As explained hereafter, according to the claimed invention, the gates are commonly connected to the output signal generation circuit, and the source-V-rain current circuits having different channel conductances are connected to the ground terminal and the output terminal. a plurality of field effect transistors formed in parallel between the plurality of field effect transistors, and a plurality of field effect transistors connected in parallel between each gate of the plurality of field effect transistors and a ground terminal, the time constants between the output signal generation circuit and each gate being different from each other; By configuring the output circuit with multiple capacitors,
Since the magnitude relationship of the channel conductance of the field effect transistor can be made to match the magnitude relationship of the 94P constant, when inverting the output signal, the initial speed of one inversion can be kept small, while the bonding speed of inversion can be increased. Therefore, even if the equivalent capacitance of the load circuit varies widely, this can be handled without changing the design of the one-field effect transistor. That is, the voltages at the output terminals of various load circuits can be reliably reversed within the allowable transient period, and the excellent effect of not causing undershoot or the like in the output signal waveform can be obtained.

Furthermore, in one embodiment of the present application, an inversion time control circuit is further provided, so even when a load circuit with an extremely large equivalent capacitance is connected to the output terminal, the voltage at the output terminal can be completely controlled within the allowable transient period. It has the advantage that it can be reversed.

[Brief explanation of drawings]

Fig. 1 is an electric circuit diagram showing an embodiment of the great invention, Fig. 2 is an electric circuit diagram showing a conventional output circuit, Fig. 3 is a timing chart of the output circuit shown in Fig. 2, and Fig. 4 is an electric circuit diagram showing an embodiment of the great invention. The figure is a timing chart diagram of one embodiment. 11... Output signal generation circuit (logic circuit) 15, 18... Multiple field effect transistors (N-MOS) 17...・・・・・・・・・・・・Output terminal 18, P
C......Multiple capacitors (MOS capacitor, stray capacitance 1Ik) 19......Field-effect transistor for rapid discharge (N-MOS') 20・・・・・・・・・・・・・・・Field effect transistor for transfer gate (N-MOS) 21・・・・・・・・・・・・・・・Capacitor (MO
S capacitor) 1. T2) T3... Time constant Vss... Ground terminal SlN...
・・・・・・・・・Output signal patent applicant: Japan Texas Instruments Co., Ltd. Figure 1

Claims (2)

[Claims] (1) In the output circuit interposed between the output signal generation circuit 11 that outputs the output signal SlN representing binary information and the output terminal 17, the gates thereof are commonly connected to the output signal generation circuit 11, and the channels are mutually connected. A plurality of field effect transistors 15 and 16 forming source-drain current paths with different conductances in parallel between the ground terminal Vss and the output terminal 17, and respective gates of the plurality of field effect transistors 15 and 16 and grounding. The channel conductance of the field effect transistor includes a plurality of capacitors 18 and PC connected in parallel between the terminal Vss and having different time constants TC1 and TC2 between the output signal generation circuit 11 and each gate. An output circuit characterized in that the magnitude relationship of is made to match the magnitude relationship of the time constant. (2) In the output circuit according to claim 1,
A field effect transistor 19 for rapid discharge forming a current path between its source and drain between the ground terminal Vss and the output terminal 17, and a field effect transistor whose gate is inverted first among the plurality of field effect transistors. A transfer gate field effect transistor 20 is connected to the gate of the rapid discharge field effect transistor 15 and forms a source-drain current path between the output terminal 17 and the gate of the rapid discharge field effect transistor 19; The output terminal 17 and the rapid discharge field effect transistor 1 are arranged between the gate of the type transistor 19 and the ground terminal Vss.
The time constant TC3 between the output signal generating circuit 11 and the gate of the field effect transistor 16 to be inverted last among the plurality of field effect transistors
The output circuit further comprises an inversion time limiting circuit having a capacitor 21 greater than 1.