JPS6290021A - Schmitt trigger circuit - Google Patents

Abstract

PURPOSE:To realize a desired threshold voltage and to facilitate the increase in the hysteresis width by providing a means setting the upper limit and lower limit threshold voltages of a Schmitt trigger circuit of an integrated circuit having a CMOS structure depending on different conditions. CONSTITUTION:PMOS 3 and NMOS 4 have an upper limit threshold value V<+>T and PMOS 5 and NMOS 6 have a lower limit threshold value V<->T. When the input voltage VIN is 0 volt, the PMOS 3, 5 are turned on, the NMOS 4, 6 are turned off, the PMOS 7 is turned off and the NMOS 8 is turned on and a low level voltage is outputted to an output terminal 2. When the input voltage VIN rises up to V<->T, the NMOS 8 is turned off. In this case, a point D1 is at a high level and the high level is kept until the input voltage reaches V<+>T. Thus, when the input voltage is higher than the V<->T and lower than the V<+>T, the output voltage keeps a low level without charging an electric charge to a parasitic cpacitance of transistors. When the input voltage reaches the V<+>T, the level of the output terminal 2 is inverted. Then the VT<+>T depends on the W/L ratio of the PMOS 3 and NMOS 4 and the V<->T depends on the W/L of the PMOS 5 and NMOS 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a Schmitt trigger circuit having a complementary MO8 transistor (hereinafter referred to as CMO8) structure.

[Conventional technology]

Generally, a Schmitt trigger circuit composed of CMO8 is
As shown in Figure 3, P-channel type MOS transistor (hereinafter referred to as PMO8) 3 and N-channel type MO8)
transistor (hereinafter referred to as NMO8), 4 series circuit and P
The series circuits of MO8.5 and NMO8.6 are arranged in parallel,
The respective drain terminals Di and D2 are connected, and the output terminal 2 is connected to the drain terminal D2 via an inverter 11 for signal inversion to be read. The output of the inverter 11 is connected to the gates of PMO8, 5 and NMO8, 6.
・Each gate of 4 is connected to input terminal ・1.

[Problem that the invention seeks to solve]

In the Schmitt trigger circuit described above, when a low level (0 volt) input voltage is input to input terminal 1, PMO 8.
3 turns on and NMO8-4 turns off, so the connection point DI
, D2 become high level. This high level voltage is
It is inverted by inverter 11 and a low level output voltage is output from output terminal 2, and PMO8.5 and N
Applied to the gates of MO8 and MO6. This allows PMO
8 and 5 are turned on, and NMOs 8 and 6 are turned off to stabilize the low level output voltage. Then, when the input voltage is gradually increased from O volts, Dl.

The potential at point D2 begins to decrease. When the input voltage further increases and the potential at points DI and D2 falls below the threshold voltage of the inverter 11, the output voltage is inverted to a high level. Since this high level voltage is applied to the gates of PMO8.5 and NMO8.6, PMO8.5 is turned off and NMO8.6 is turned on, causing DI.

The potential at point D2 drops rapidly to stabilize the high level output voltage. The input voltage at this time is the upper threshold voltage
It becomes VT+.

Next, when the input voltage is decreased from this state, DI,
The potential at point D2 begins to rise. When the input voltage further decreases and the potential at points Di and D2 rises above the threshold voltage of the inverter 11, the output voltage is inverted to a low level. Since this low level voltage is applied to the gates of PMO8.5 and NMO8.6, PMO8,s is turned on, NMO8.6 is turned off, and the potential at points DI and D2 rises rapidly, causing the low level output voltage to rise. Stabilize. The input voltage at this time becomes the lower limit threshold voltage vT''.

Here, VT″″ is W/L of PMO8・1, PMO8・
It is determined by the W/L of 3 and the W/L of NMO8.2. On the other hand, W/L of VT″″&tPMO8,1, NMO8゜2
It is determined by the W/L of NMO8.4 and the W/L of NMO8.4. W is the channel width and L is the channel length.

In a Schmitt trigger circuit as shown in FIG. 3, for example, the hysteresis width ΔVT (:VT - VT)
When you want to increase the noise margin by making the VT
+t
408-3's W/L is dog-gagged, NMO8-2's W/L
'fr: If you want to lower Vy-, reduce the W/L of PMO8.1 and NMO8.2.
And the W/L of NMO8.4 will be increased.

In other words, PMO8.1 and NMO8.2 are VT
It has been extremely difficult to achieve a desired threshold voltage within a certain transistor size because three contradictory conditions are required in relation to both VT- and VT-.

[Means for solving problems]

An object of the present invention is to provide means for setting the upper limit threshold voltage VT+ and the lower limit threshold voltage VT"" of a Schmitt trigger circuit of an integrated circuit having a CMO8 structure, respectively, according to different conditions.

According to the present invention, a Schmitt trigger circuit includes a first input circuit having an upper threshold voltage and a second input circuit having a lower threshold voltage and receiving a common input with the first input circuit. and has a source, a drain, and a gate.
a first conductive EIL type @IMO8) transistor whose source is connected to a first power source and whose gate is connected to an output terminal of the first input circuit;
by a 42M0S transistor formed in a second conductor opposite to the first conductor, which is connected to a power supply, has a gate connected to the output terminal of the second input circuit, and has a drain commonly connected to the drain of the first MOS transistor. Accordingly, it is possible to obtain a Schmitt trigger circuit which obtains an output signal from the drains of the commonly connected second MOS transistors.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a Schmitt trigger circuit of an integrated circuit having a CMO8 structure showing one embodiment of the present invention.

Upper threshold voltage at 8 for Schmitt trigger circuit, VT
A series circuit of PMO8.3 and NMO8.4 with a lower limit threshold voltage vT-.
and NMO8. are arranged in parallel, and each gate is connected to input terminal 1. The gate of PMOS.7 is connected to the drain holder Dl of the series circuit of PMO8.3 and NMOS.4, and the source is connected to the power supply terminal 9.

The gate of NMO8.8 is P M 08.5 and NMO8.
It is connected to the drain terminal D2 of the series circuit of 6, the source is connected to the ground terminal 10, and the drain is connected to the PMO8 7
It is connected in common with the drains of , and further connected to output terminal 2.

Next, the operation of this embodiment will be explained.

In Figure 1, when a low level (0 volt) input voltage is input to input terminal 1 at 8, PMO 8 and 3 and PMOS
-5 is turned on and %NMO8.4 and NMO8.6 are turned off, so the potentials at the connection points DI and D2 both become high level. This high level voltage is applied to the gates of PMO8/7 and NMO8/8, so PMO8/7 is turned off and NMO8/8 is turned off.
8.8 is on 1. A low level voltage is output to the output terminal 2.

From this state, the input voltage is gradually increased from O volts, and when the input voltage rises to Vr-, PMO8
・5 turns off and N+'A OS・6 turns on, so
4th place with 2 D points is at a low level. This low level pressure is applied to the gate of NMO8.8.

NMO8.8 is turned off. At this time, the potential at point A1 is at a high level, and the high level voltage is maintained until the input voltage reaches vT. Therefore, the input voltage is higher than Vt-, and VT
When the voltage is lower, both PMO8 and 7°NMO8 and 8 are in an off state, and the parasitic capacitance of the transistor is not charged, and the output voltage is maintained at a low level. Then, when the input voltage reaches VT''K, PMO8-3ybx turns off and NMOF3.4 turns on, so the potential at point Dl becomes low level. This low level voltage is applied to the gates of PMO8.7, and PMO8. 7 is turned on, the output voltage is inverted from low level to high level.

Next, when the input voltage is decreased from this state to VT+, PMO8.3 is turned off and NMOS.4 is turned on, so that the Dl point "4" becomes a high level. This high level 'tlE is applied to the gates of PMO8 and 7,
PMO8 and PMO7 are turned off.

The potential at these 402 points is low level, and the input voltage is V'r-
The low level voltage is held until the voltage drops to . Therefore, the input colored soil is lower than VT+ and higher than VT″″, PM
Both O8・7 and NMOS・8 are in the off state at h9, and the charge is not discharged from the parasitic capacitance of the transistor.
The output voltage remains at a high level. Input voltage is VT'''
When the voltage drops to this level, PMOS'.5 is turned on and NMO8.6 is turned off, so that the first A2 point becomes a high level. This high level voltage is applied to the gate of NMO8・8+7)nl,
Since NMO8.8 is turned on, the output voltage is inverted from high level to low level.

Here, VT is PMO8・3(7)W/L and NMO8
・Determined by the W/L ratio of 4. On the other hand, VT- has PMO8.5
It is determined by the ratio of W/L of NMO8.6 to W/L of NMO8.6.

〔Effect of the invention〕

As explained above, the present invention can improve the upper limit threshold voltage and lower threshold voltage of a Schmitt trigger circuit. Since each threshold voltage is determined by different conditions, a desired threshold voltage can be easily set, and the hysteresis width can also be easily widened to increase the noise margin.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an embodiment of the Shemitt trigger circuit of the present invention, Fig. 2 is a diagram showing the hysteresis characteristics of the Schmitt trigger circuit of Fig. 1, and Fig. 3 is a diagram showing a conventional Shemitt trigger circuit. It is. 1...Input terminal, 2...--Output terminal, 3
, 5, 7...P channel gMO8) transistor, 4,6゜8...N channel type MO8) transistor, 9...power terminal, 10...・
Ground terminal, 11...Inverter for signal inversion. Agent Patent Attorney Uchihara 2 'Machi Kaya IUIJ $2 Figure Kaya 3 Figure

Claims (1)

[Claims] a first input circuit having a first threshold voltage; a second input circuit having a second threshold voltage and to which an input common to the input signal of the first input circuit is applied; and a source and a drain. a first MOS transistor of a first conductivity type, having a gate, the source being connected to a first power supply, and the gate being connected to an output terminal of the first input circuit;
A source is connected to a second power supply, a gate is connected to an output terminal of the second input circuit, and a drain is connected to the first MO input circuit.
A Schmitt device comprising a second MOS transistor of a second conductivity type opposite to the first conductivity type commonly connected to the drains of the S transistors, and an output signal is obtained from the drains of the commonly connected second MOS transistors. trigger circuit.