JP2541289B2 - Output circuit - Google Patents

Description

The present invention relates to an output circuit connected to an output terminal of a semiconductor integrated circuit device.

[Conventional technology]

Conventionally, this type of output circuit has been used in which two stages of inverter circuits as shown in FIG. 3 are connected. That is, in each inverter circuit, the P-channel MOS transistor 6 and the N-channel MOS transistor 7 are connected in cascade between the power supplies, the gates are commonly connected for input, and the drains are commonly connected for output. Connect the common gate of the front-stage inverter circuit to the input terminal 1 (connection point to other circuits in the IC), connect the common drain of the front-stage inverter circuit to the common gate of the rear-stage inverter circuit via the resistor 10, and then connect the rear-stage inverter circuit. The output terminal 8 was connected to the common drain of the circuit.

[Problems to be Solved by the Invention]

The above-mentioned conventional output circuit has a drawback that the peak value of the charging / discharging current of the output additional capacitance is large, and therefore the potential of the power supply ground fluctuates due to the power supply and the ground impedance.

Therefore, as shown in FIG. 3, a circuit in which a resistor 10 is added to the input of the inverter circuit is often used. However, this causes a new drawback that the input voltage change (rise time, hall time) of the inverter circuit becomes large and a through current flows in the inverter circuit from the power supply to the ground.

[Means for solving the problem]

The output circuit of the present invention is an output circuit in which a first-conductivity-type first MOS transistor and a second-conductivity-type second MOS transistor are connected in series between power supplies, and an output is taken out from the series connection point. And a third MOS transistor of one conductivity type is connected between the gate of the first MOS transistor and
A reverse conductivity type fourth MOS transistor is connected between the other of the power source and the gate of the second MOS transistor so that a signal from an input terminal is commonly applied to the gate of the third MOS transistor and the gate of the fourth MOS transistor. A fifth MOS transistor having a fifth MOS transistor connected to a common line and a fifth MOS transistor whose one end is connected to the gate of the first MOS transistor and a sixth MOS transistor whose one end is connected to the gate of the second MOS transistor are connected in common. And the other end of the sixth MOS transistor is connected to the input terminal via an inverter, and the fifth MOS transistor and the fifth MOS transistor are connected.
A common gate connection point with the 6MOS transistor is connected to the input terminal or the output terminal of the inverter.

The output circuit of the present invention has an effect that the fluctuation of the power supply and the ground potential at the time of charging / discharging the output load is small and the through current of the output circuit itself is small.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. In the figure, 2, 5, and 7 are N-channel MOS transistors, and 3, 4, and 6 are P-channel MO transistors.
S transistor, 9 is an inverter. Considering immediately after the potential of the input terminal changes from low level to high level (0V to VDD potential), the P-channel MOS transistor 3
Changes from ON to OFF, and the N-channel MOS transistor 5
It changes from OFF to ON. After that, the output resistance of the inverter 9 and N
The on-resistance of the channel MOS transistor 2 slowly lowers the gate voltage of the P-channel MOS transistor 6. Therefore, the N-channel transistor 7 is turned off first and then the P-channel transistor 6 is slowly turned on. Therefore, the two P-channel and N-channel transistors 6 and 7 are not turned on at the same time, and a through current does not flow from the power supply to the ground. Further, since the gate voltage of the P-channel transistor 6 drops slowly, the potential of the output terminal 8 also moves slowly. Therefore, the fluctuation of the power ground potential due to the power ground impedance is small. When the voltage of the input terminal changes from the high level to the low level (from VDD potential to 0V), the P-channel and N-channel transistors 6 and 7 are the MOS transistors 4 and the P-channel transistor 3 is the N-channel transistor in the above description. 5, the P-channel transistor 6 is replaced with the N-channel transistor 7 for operation.

FIG. 2 shows an output circuit of the second embodiment of the present invention. In contrast to the first embodiment, the MOS transistor 2'is a P channel M
This is realized by an OS transistor, and the MOS transistor 4'is implemented by an N channel. The circuit operation is the same as in the first embodiment.

〔The invention's effect〕

As described above, the present invention has the advantages that the fluctuation of the power supply ground potential at the time of charging / discharging the output load is small and the through current from the power supply of the output circuit itself to the ground is small. There is an effect that the power consumption is low without paying much attention to the layout.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional example. 1 ... Input terminal, 2,4,2 ', 4' ... MOS transistor,
3,6 P-channel MOS transistor, 5,7 N-channel MOS transistor, 8 output terminal, 9 inverter, 10 resistance.

Claims (1)

(57) [Claims] 1. An output circuit in which a first-conductivity-type first MOS transistor and a second-conductivity-type second MOS transistor are connected in series between power supplies and an output is taken out from the series connection point, and one of the power supplies is A third MOS transistor of one conductivity type is connected between the gates of the first MOS transistor, and a fourth conductivity type M of the opposite conductivity type is connected between the other of the power source and the gate of the second MOS transistor.
An OS transistor is connected, a wiring is connected to the gate of the third MOS transistor and the gate of the fourth MOS transistor so that a signal from an input terminal is commonly applied, and one end is connected to the gate of the first MOS transistor. 5th MOS
A transistor and a gate of a sixth MOS transistor whose one end is connected to the gate of the second MOS transistor are commonly connected, and the other end of the fifth MOS transistor and the sixth MOS transistor are connected.
An output characterized in that the other end of the transistor is connected to the input terminal via an inverter, and a common gate connection point of the fifth MOS transistor and the sixth MOS transistor is connected to the input terminal or the output end of the inverter. circuit.