JP2934265B2 - Complementary MOS output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding a complementary MOS output circuit that outputs signals that change simultaneously from a plurality of output terminals, glitches due to inflow of a transient current into a low-potential-side power supply are prevented, and a malfunction may occur. An output-stage P-channel MOS transistor connected between a high-potential-side first power supply and an output terminal; and a low-potential-side second power supply. A complementary MOS output circuit that outputs a signal from the output terminal by turning on one of an output stage N-channel MOS transistor connected between the output terminal and the first output terminal. A plurality of MOS transistors including a constant-current P-channel MOS transistor that is connected and driven based on an on-drive instruction of the output-stage N-channel MOS transistor; A constant current load circuit for flowing a constant current for turning on the output stage N-channel MOS transistor from the drain of the MOS transistor; a constant current load circuit connected between the output terminal and the output terminal of the constant current load circuit; And a MOS capacitor that is discharged by a constant current output from the constant current load circuit.

[Industrial applications]

The present invention relates to a complementary MOS output circuit, and more particularly to a complementary MOS output circuit that outputs a signal that changes simultaneously from a plurality of output terminals.

An integrated circuit having a complementary MOS (CMOS) configuration has a large number of output terminals, and simultaneously changes and outputs signals of a plurality of bits such as data and addresses.

It is desired that the power supply voltage of the integrated circuit does not change even when a plurality of signals change simultaneously.

[Conventional technology]

FIG. 5 is a circuit diagram showing an example of an output circuit of a conventional CMOS output circuit.

In the figure, a terminal 10 receives a control signal CTL for high impedance control, and a terminal 11 receives data DATA.
It is supplied to drive circuits 12 and 13. Drive circuit 12 is inverter 1
2a, 12b, is constructed from 12c and the NAND circuit 12d and the P-channel MOS transistor P _0, signal CTL is data in the L level H
N-channel MOS transistor N1 of the output stage at a level to generate a signal for driving the P-channel MOS transistor P ₁ of the output stage when off. Drive circuit 13 is more configuration and inverter 13b, signal CTL is data in the L level to generate a signal MOS transistors P ₁ at the H level to drive the MOS transistors N ₁ and N-channel output stage when off.

The output terminal 14 is connected to a commonly connected drain of the MOS transistors P ₁ and N ₁ .

[Problems to be solved by the invention]

MOS transistor P ₁ is turned on when the load of a large capacity to the output terminal in the conventional circuit is connected, MOS transistor
N ₁ is the MOS transistor P ₁ from H-level data output off off, the MOS transistor N ₁ is turned on, a transient current flows through the MOS transistor N ₁ from the load to the power supply, that the ground of the low potential side, MOS transistors P ₁ , the current driving capability N ₁ flows to ground If it is larger becomes larger.
When the output terminal 14 outputs an address or data, for example, when the address of 32 bits changes to the H level or the L level of all bits, an overcurrent flows into the ground from the 32 output circuits, and a glitch occurs in which the ground potential rises, As a result, an L-level output signal of another output terminal is erroneously set to an H-level in a subsequent circuit, which may cause a malfunction.

The present invention has been made in view of the above points, and has as its object to provide a complementary MOS integrated circuit that prevents glitches due to a transient current flowing into a power supply on the low potential side and eliminates the possibility of malfunction. I do.

[Means for solving the problem]

A complementary MOS output circuit according to the present invention comprises: an output-stage P-channel MOS transistor connected between a high-potential-side first power supply and an output terminal; A complementary MOS output circuit that outputs a signal from an output terminal by turning on one of the output stage N-channel MOS transistors connected to the output stage, the source of which is directly connected to the first power supply, and the output stage N-channel MOS transistor A plurality of MOS transistors including a constant current P-channel MOS transistor driven based on a transistor ON drive instruction;
OS transistor drain to output stage N-channel MOS
A constant current load circuit that supplies a constant current for driving the transistor ON, is connected between the output terminal and the output side terminal of the constant current load circuit, and is discharged by the constant current output from the constant current load circuit.
MOS capacity.

[Action]

In the present invention, a constant current for ON drive of the output stage N-channel MOS transistor is passed by a constant current load circuit,
And MO between the output terminal and the output side terminal of the constant current load circuit.
Since the S capacitance is provided, the output stage N-channel MOS transistor is gradually turned on, so that the discharge current of the load of the output terminal is prevented from flowing abruptly, the occurrence of glitches is suppressed, and the possibility of malfunction is eliminated.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the circuit of the present invention. 4, the same parts as those in FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 1, data DATA from terminal 11 is a constant current load circuit.
It is supplied to the gate 20 and N-channel MOS transistor N _2. Constant current load circuit 20 is connected between the power supply Vcc and the MOS transistors N ₁ of the high side gate, the source of the MOS transistor N ₂ is grounded.

Control signal CTL from the terminal 10 is supplied to the gate of N-channel MOS transistor N _3, MOS transistor N ₃ is grounded source, and is a drain connected to the gate of the MOS transistor N _1.

The output of the inverter 12b is an N-channel MOS transistor
Is supplied to the gate of N _4, MOS transistor N ₄ is grounded source, and is a drain connected to the gate of the MOS transistor N _1. Also between the drain of the output-side terminal i.e. MOS transistor N ₂ output terminals 14 and the constant current load circuit 20 MOS capacitor 21 is inserted and connected.

MOS transistor N ₂ above is a transistor for turning off the MOS transistors N ₁ of the output stage when H-level data DATA. MOS transistor N ₃ is turned on off, high impedance mode output operation mode. MOS transistor N ₄ is a transistor for turning off the MOS transistors N ₁ when the on-MOS transistor P ₁ of the output stage.

As shown in FIG. 2, the constant current load circuit 20 includes P-channel MOS transistors P ₂ and P ₃ having a current mirror configuration, a resistor R _{1 made of} polysilicon or diffusion, an N-channel MOS transistor N ₅ for switching, and a terminal. inverting the data dATA coming from the 22 are more configuration and supplies an inverter 23 to the gate of the MOS transistor N _5, the data dATA is rendered conductive MOS transistor N ₅ at the L level M constant current
To the gate of the OS transistor P ₃ of the drain of FIG. 1 via a terminal 24 MOS transistors N ₁ supplying a constant current.

Here, when the control signal CTL is at the L level and the MOS transistor
In the output operation mode in which P ₀ and N ₃ are off, when the data DATA is at the H level and the MOS transistor P ₁ is on, the MOS transistor
N ₁ is the data DATA from the H-level data output OFF L
When the level becomes the level, the MOS transistors P ₁ , N ₂ , and N ₄ are turned off, and the constant current load circuit 20 starts flowing a constant current. However, increase in the gate potential of the MOS transistor N ₁ by the discharge of the MOS capacitor 21 which is charged in the H level data output state is suppressed, MOS transistors N ₁ gradually increases as the discharge of the MOS capacitor 21 begins to turn on. This gives M
MOS transistors N ₁ discharge OS capacitor 12 is accelerated to an output terminal 14 in the ON state becomes the data output state of an L level.

In this way, the MOS transistor 21
Suppressing the rise of the gate potential of N ₁ is performed, the increase in the gate potential of the MOS transistor N ₁ charge of the MOS capacitor 21 is to be driven by the constant current driving circuit 20 is stable, the load on the output terminal 14 Since the discharge current does not flow rapidly, the generation of glitch is suppressed.

FIG. 3 shows a circuit diagram of a modification of the circuit of the present invention. In the figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

It is provided buffer stage 25 between the gate of the constant current load circuit 20 and the MOS transistor N ₁ in Figure 3. Buffer stage 25 and the N-channel MOS transistor N ₁₀ as a buffer connected to the gate to the constant current load circuit 20 and the MOS capacitor, the MOS transistor N ₂ and the gate of the output stage to the H level when the commonly connected with and data DATA the MOS transistors N ₁ and N-channel MOS transistor N ₁₁ which is turned off,
MOS transistor N ₄ and MOS transistor N ₁₀ when the ON MOS transistors P ₁ of the output stage gate are commonly connected
And N-channel MOS transistor N ₁₂ for turning off the, MOS
Transistor N ₃ and a gate commonly connected to and output operation mode off, turned on in a high-impedance mode N
Is more configuration as channel MOS transistor N _13.

In the configuration of Figure 1 requires a constant current load circuit 20 and the MOS transistor N ₂ and the like is large driving capability to some extent for driving the MOS transistors N ₁ of the output stage supplying a large current, large capacity Therefore MOS capacitor 21 to some extent Is required. This third driving ability, such as the constant current load circuit 20 and the MOS transistor N ₂ because it provided a buffer stage 25 in the configuration in FIG. For be small, and therefore the MOS capacitor 21 can be a small capacity .

In the constant current load circuit 20 shown in FIG. 2, the electron mobility increases at low temperatures, and the transient current in the output stage also increases. In order to solve this, the circuit of the constant current load may be configured as shown in FIGS. 4 (A) and 4 (B).

P-channel MOS transistor Pa~Pn is inserted and connected in series connected n-stage in common connecting the gate and source between the fourth view (A) in the drain of the MOS transistor P ₂ and the resistor R _1. The N-channel MOS transistor connected in series in Figure 4 (B) in the same MOS transistor n stages and a gate and a drain commonly connected to the back gate voltage ground level between the drain of P ₂ and the resistance R ₁ Na
To Nn are inserted and connected.

FIG. 4 (A), even if increasing the electron mobility at low temperatures in the configuration of (B), both ends of the resistor R ₁ by MOS transistors Pa～Pn (or Na～Nn) each threshold value is increased at a low temperature The voltage decreases, the load current decreases, and the transient current of the output stage can be kept constant. Further, in the configuration of FIG.
Even when Vcc rises, the back gate bias of the MOS transistors Na to Nn increases, so that the threshold values of the MOS transistors Na to Nn increase and the transient current of the output stage can be kept constant.

〔The invention's effect〕

As described above, according to the complementary MOS output circuit of the present invention,
This prevents glitches due to the flow of transient current into the low-potential-side power supply and eliminates the risk of malfunction, which is extremely useful in practice.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the circuit of the present invention, FIG. 2 is a circuit diagram of an embodiment of a constant current load circuit, FIG. 3 is a circuit diagram of a modification of the circuit of the present invention, and FIG. FIG. 5 is a circuit diagram of an example of a conventional circuit of a current load circuit. In the figure, 14 is an output terminal, 20 is a constant current load circuit, 21 is a MOS capacitor, P ₁ is an output-stage P-channel MOS transistor, N ₁ is an output-stage N-channel MOS transistor, and N _{2 to} N ₁₃ are N-channel MOS transistors. , P ₂ and P ₃ indicate P-channel MOS transistors.

Claims (1)

(57) [Claims] An output stage P-channel MOS transistor (P ₁ ) connected between a first power supply on a high potential side and an output terminal (14); a second power supply on a low potential side; In the complementary MOS output circuit for outputting a signal from the output terminal (14) by turning on _{one of} the output stage N-channel MOS transistors (N ₁ ) connected to the output terminal (14), the source is A constant current P-channel MOS transistor (P) that is directly connected to the first power supply and driven based on an ON drive instruction for the output stage N-channel MOS transistor (N ₁ ).
₃ ) including a plurality of MOS transistors including the constant current P
A constant current load circuit (20) for flowing a constant current from the drain of the channel MOS transistor (P ₃ ) to turn on the output stage N-channel MOS transistor (N ₁ ); the output terminal (14) and the constant current A MOS capacitor (21) connected between an output terminal of the load circuit (20) and discharged by a constant current output from the constant current load circuit (20). .