JPS63258115A - Ttl compatible sell for cmos integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to TTI and compatible cells included as signal input circuits in electronic integrated circuits in CMO5 technology, and provides compatibility with TTL logic in CMOS chips. It is something that gives it sex. More particularly, the present invention relates to a TTL compatible cell that consumes zero power during power down of the integrated circuit.

[Prior art] As is known, VLSI (Very Large 5ca
The Integra-L 1on) is often built in CMO8 technology to reduce power consumption. In order to further reduce the average consumption of power, the above (:M
It is also known to provide an OS chip with a deactivation bin or a power down bin, which can be used in a known manner to power down the chip when either chip is powered but not in use. This makes it possible to forcibly reduce the consumption of the circuit (actually, to the lowest value).

However, many input bins of CMOS chips have TT
Compatibility with L logic signals is required. This means that the input circuit that the bin reaches will accept all voltages below 0.8v as logic 0.
2. This means that all voltages above OV (sometimes 2.4V) must be recognized as logic I. For this purpose, an input circuit known as a TTL convertible cell is used, which circuit must supply the appropriate CMOS levels of logic 0 and logic 1 at the output, respectively.

Prior art TTL compatible cells essentially consist of two cascaded inverters, the first of which
A suitable tripping threshold (
For example, 1.4V).

In the power-down state, a conductive path exists in the cell's input inverter between the power supply and ground, as will be explained in detail below, and therefore there is a significant Because there are intermediate levels of TTL input signals (not under the control of the CMOS chip) where power is consumed, the consumption of these cells may remain relatively high.

[Problem II to be Solved by the Invention] As will be explained in more detail below, in known TTL compatible cells, this problem is solved by providing the cell with a MOS transistor controlled by an inverter,
The solution is to force the voltage of the TTL logic external to the chip to change to an extreme value that will cause the inverter to be non-depletable.

However, this solution has the disadvantage of changing the state of the external TTL logic, which may not be used in some cases, for example if this TTL logic drives further circuits; It has no effect if it is a voltage generator.

That is, the object of the present invention is to (:) without affecting the state of the TTL circuit included in the MOS chip and outside the chip.
The present invention provides a TTL compatible cell with substantially zero consumption during power down of a CMO8 integrated circuit.

[! ! SUMMARY OF THE INVENTION The above objects of the present invention as well as other objects and advantages which will become apparent hereinafter, include two CMOS inverters connected in cascade and interlocked with input pins of an integrated circuit to receive signals of TTL logic. In TTL compatible cells for CMOS integrated circuits with a 1M circuit or a power-down pin,
The above input pins of the CMO5 integrated circuit are connected in parallel to P-channel and N-channel first and second MOs, respectively.
The first of the above two inverters through the S transistor
The first transistor is controlled by the power-down pin, and the second transistor is controlled by the inverter driven by the power-down pin and turns off when the power-down signal is logic 1. When the signal is logic 0, the other MOS transistor is connected between the input of the first inverter and ground, and when the power-down signal is logic 1, the other MOS transistor is activated. This is achieved by a TTL compatible cell characterized in that the gates of the other MOS transistors are controlled such that they are active and turn off when the even signal is logic 0.

[Example] The present invention will now be described in detail with reference to the accompanying drawings relating to embodiments.

In FIG. 1 related to the conventional technology, the input bin 10 of the ClO2IC (not shown in FIG. The above transistors are connected in series between the power supply voltage Van (typically 5V) and the earth GND.

m (note) 16 between transistors 12 and 14 is 2
The input of a second inverter formed by two MOS transistors 12.20 is connected in a similar manner to the first inverter. The output 22 of the second inverter 18.20 constitutes the output of the TTL compatible cell.

In the table of FIG. 2 showing the output voltage V o u L of the first inverter as a function of the input voltage V in , pin 12
For all voltages from +Ov to 0.8V applied to , m16 is between VDD and vx≧vDn-vTP, where vTP is the P-channel dark value voltage of inverter 18.20, and 2. For all input voltages from Ov to VDD, 1i16 is between oV(GND) and vy≦vT□, where vTH is the N-channel dark value voltage of inverter 18.20.

That is, in the first case the inverter 18.20 has a logic l at its input and a logic zero in the second case.

As is known to experts in this field, the input voltage and GND (
If the difference from N channel off) or Voo (p channel off) is less than a threshold voltage, the CMOS inverter does not dissipate power, ie there is no continuity between the power supply and ground in such a case.

Conversely, the input at the first inverter 12.14!
If the voltage is included between VTN and vlI=vD0-vip, both N and P channels will be conductive and the output will be set to the value read from the table in Figure 2.6 For example, if the input is 2V, then The output is vy. In these cases, for a given value of the voltage applied to the bin, the first inverter of the TTI, compatible cell forming part of the CMOS chip draws a significant current compared to the low values of other currents in the circuit. consume.

In order to reduce or eliminate power dissipation in the TTL compatible cells forming part of the CMOS chip, the cell of FIG. There is. MO between the 1st inverter 12.14 and the 2nd inverter 18.20
An S transistor 24 is inserted so that the S, , TC line is at the supply voltage VDD and the source is connected to the second inverter 18.
．． Connected to 20 inputs. The source of transistor 24 is further connected via a limiting resistor 26 to bin lO. In this way, even if the voltage at pin lO takes a value such that the TTL compatible cell consumes power (for example, 2.OV), the voltage at node 16 will be V, and therefore transistor 24 will be driven by a high gate-source voltage. be done. Therefore, the current flows through the limiting resistor 26 towards pin 10,
It then flows to the outer 5TTL circuit and the output voltage of this circuit is forced to vbo, as is obvious to those skilled in the art.

Obviously, as mentioned at the beginning, this solution changes the conditions of the external circuitry leading to the chip, so it cannot be used if this external circuitry drives another chip. It has no effect if it is controlled by a voltage generator instead.

According to the present invention, the TTL compatible cell in FIG.
Cascaded 12.14 and 18.20 respectively
Fig. 1 and Fig. 3 I2 composed of! has first and second inverters similar to. However, bin 10
are not directly connected to the input of the first inverter, but are connected in parallel via two P-channel and N-channel MOS transistors 28 and 30, respectively. The gate of transistor 28.30 is the power down bin 3 of I,C.
1 directly and via input 32, respectively. The power down signal is further connected to the inputs of the first inverters 12, 14 and to ground (
GND) controls the gate of an N-channel transistor 34 connected between the two terminals.

It will be seen that under normal operating conditions, i.e. when the power down signal is a logic zero, the two transistors 28.30 in parallel are both conducting while transistor 34 is off, so that elements 28.30 ,32.3
The cell operates exactly like the 11 cell, as if 4 were not present.

When the power-down signal becomes active, ie, logic 1, transistors 28, 30 turn off while transistor 34 conducts. The pins are therefore isolated from the chip while the inputs of the inverters 12, 15 are grounded so that there is no conductive path between Vl)6 and the ground of the inverters 12, 14 of the T-compatible cells.

The additional circuitry including elements 28, 30, 32, and 34 thus constitutes a circuit that separates the internal circuitry leading to the CMOS chip and the external circuitry driving the pins.

Figure MS5 is a second diagram of a TTL compatible cell according to the present invention.
This embodiment is similar to the first embodiment and also includes a cascaded first inverter 1
2.14 and a second inverter 18.20 and two transistors 30.28 connected in parallel, which are controlled directly by the power down bin and through the inverter 32.

It will be easily understood that unlike the first embodiment, the transistor 34 is of a P-channel type and its gate is controlled by the output of the inverter 32 rather than the power down bin 31, and the zero operation is equivalent.

Although particularly preferred embodiments of the invention have been described, it will be understood that modifications may be readily made by those skilled in the art without departing from the spirit of the invention.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first type of prior art TTL compatible cell. FIG. 2 is a table of the output voltage of the cell of FIG. 1 as a function of the input voltage. FIG. 3 is a circuit diagram of a second type of TTL compatible cell according to the prior art. FIG. 4 shows a T according to a particularly preferred first embodiment of the invention.
FIG. 2 is a circuit diagram of a TL compatible cell. The tPIS diagram is a circuit diagram of a TTL compatible cell according to another particularly preferred embodiment of the present invention. 10-...Input bin 12.14...Inverter 28-P channel MOS transistor 30--N channel MOS transistor 31-...Power down pin 32...Inverter 34...MOS transistor

Claims (1)

[Claims] 1. A CM that includes two cascade-connected CMOS inverters and is interlocked with an input pin of an integrated circuit so as to receive a TTL logic signal, and the integrated circuit further has a power-down pin.
CM in TTL compatible cells for OS integrated circuits
The input pin (10) of the OS integrated circuit is connected to the first of the two inverters (12, 14) through the first and second P-channel and N-channel MOS transistors (28, 30) connected in parallel, respectively. The first transistor is controlled by the power down pin (31) and the second transistor is controlled by the inverter (32) driven by the power down pin so that the power down signal is logic. It turns off when the signal is 1 and becomes active when the signal is logic 0, and another MOS transistor (34) is connected between the input of the first inverter and ground, so that the power down signal becomes logic 1. Other MOSs mentioned above when
A TTL compatible cell characterized in that the gate of the other MOS transistor is controlled so that the transistor is activated and turned off when the signal is logic 0. 2. The TTL compatible cell according to claim 1, wherein said other MOS transistor is of N-channel type and its gate is connected to a power down pin. 3. Claim 1, wherein the other MOS transistor is of a P-channel type and its gate is connected to the output of an inverter driven by a power down pin.
TTL compatible cell described in.