JP2765330B2 - Output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit constituting an output stage of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a conventional output circuit. This output circuit includes an inverter 1 for inverting an input signal, a P-channel transistor 20 and an N-channel transistor 21 connected in series between a high-potential-side power supply and ground.
It consists of. The output of the inverter 1 is provided to the gates of the transistors 20 and 21. The interconnection point between the drains of the transistors 20 and 21 is connected to the output terminal 10.

Next, the operation of the conventional output circuit configured as described above will be described.

The inverter 1 outputs a low-level (hereinafter, L-level) signal when a high-level (hereinafter, H-level) signal is applied to its input terminal. The charge stored in the gate input capacitors of the transistors 20 and 21 is discharged by the L-level signal output from the inverter 1, and the gate potentials of the transistors 20 and 21 become substantially the ground potential.

Thus, the P-channel transistor 20
Is turned on because the gate potential is sufficiently lower than the source potential (that is, the power supply potential). The N-channel transistor 21 is turned off because the source potential (that is, the ground potential) and the gate potential are the same. Therefore, when the input signal applied to inverter 1 is at H level, the potential of output terminal 10 is also at H level. Assuming that the output load is a capacitive load, electric charges are accumulated in the output load, and the output terminal 10 becomes the power supply potential.

On the other hand, when the input signal goes low, the output of inverter 1 goes high, P-channel transistor 20 is turned off, and N-channel transistor 21 is turned on. Therefore, the electric charge accumulated in the capacitive output load is discharged, and the output terminal 10 becomes the ground potential (that is, L level).

[0007]

However, in the above-described conventional output circuit, the potential of the output terminal 10 changes from the power supply potential to the ground potential in accordance with the level change of the input signal. There is a problem that it takes time to change the level of the output signal. In general, a capacitive output load has relatively large stored energy, and therefore has a large charge / discharge current value accompanying a change in the level of the output terminal 10. The charge / discharge current of this capacitive output load is determined by the P-channel transistor 20 or the N-channel transistor 21.
To the power supply or the ground, the power supply potential or the ground potential fluctuates depending on the impedance of the power supply or the ground. Therefore, the conventional output circuit has a problem that a power supply potential or a ground potential fluctuates with a change in the level of an input signal, which causes a malfunction and a reduction in operation speed of the semiconductor integrated circuit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a short transition time of an output level, a small charge / discharge current value of a capacitive output load, and a malfunction and operating speed of a semiconductor integrated circuit. It is an object of the present invention to provide an output circuit capable of avoiding a decrease in the output.

[0009]

According to the present invention, there is provided an output circuit comprising: an inverter for inverting an input signal; first and second transfer gates each having an input terminal to which the output of the inverter is provided; An output of the first transfer gate is applied, an N-channel transistor whose drain is supplied with a high-potential-side power supply voltage and whose source is connected to the output terminal, and whose gate is supplied with the output of the second transfer gate. A drain provided with a low-potential-side power supply voltage and having a source connected to the output terminal; a first transfer gate formed of an N-channel transistor; and a second transfer gate formed of a P-channel transistor. It is characterized by being constituted by a channel transistor.

[0010]

According to the present invention, first and second transfer gates are interposed between the inverter and the respective gates of the N-channel and P-channel transistors whose sources are connected to the output terminals. The first and second transfer gates are constituted by an N-channel transistor and a P-channel transistor, respectively. Therefore, when the first and second transfer gates are both in the ON state, a potential difference is generated between the input terminal and the output terminal. In other words, the potential applied to the gate of the N-channel transistor via the first transfer gate when the output of the inverter is at the H level is lower than the output potential of the inverter. When the output of the inverter is at L level, the second
The potential applied to the gate of the P-channel transistor via the transfer gate is higher than the output potential of the inverter. Accordingly, the potential of the output terminal transitions between a potential lower than the high-potential-side power supply voltage and a potential higher than the low-potential-side power supply voltage with a change in the level of the input signal. As a result, the transition time of the output level is shortened, and the charge / discharge current value of the capacitive output load is reduced, so that malfunction of the semiconductor device and reduction in operation speed can be avoided.

[0011]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an output circuit according to a first embodiment of the present invention.

The N-channel transistors 2, 3, and 4 are connected in series and form a first transfer gate. A power supply potential is applied to the gates of these transistors 2, 3, and 4. Further, P-channel transistors 6, 7, and 8 are also connected in series, forming a second transfer gate. The gates of these transistors 6, 7, 8 are supplied with a ground potential.

The output of the inverter 1 is provided to each input terminal of the first and second transfer gates. Also, the first
Each output terminal of the second transfer gate is connected to each gate of the N-channel transistor 5 and the P-channel transistor 9, respectively. The transistor 5 has a drain connected to the power supply and a source connected to the output terminal 10. The transistor 9 has a drain connected to the ground and a source connected to the output terminal 10.

FIG. 2 is a waveform chart showing the operation of the circuit of this embodiment. Note that a is an input signal to the inverter 1, b is an output signal of the inverter 1, c is a signal applied to the gate of the transistor 5, d is a signal applied to the gate of the transistor 9, and e is output from the output terminal 10. Signal.

Assuming that input signal a to inverter 1 is at L level, output signal b of inverter 1 is at power supply voltage V
_DD (that is, H level). The first transfer gate constituted by N-channel transistors 2, 3, and 4 transmits this H-level signal to the gate of N-channel transistor 5, but at this time, transistors 2, 3,
4 has a potential difference between its drain and source, the signal c applied to the gate of the N-channel transistor 5 is a signal having a potential lower than the power supply voltage V _DD .
Since the N-channel transistor 5 has the drain potential fixed to the power supply potential and operates as a source follower, the signal e output from the output terminal 10 is at the H level, but drops significantly from the power supply voltage V _DD . Potential.

At this time, since the potential of signal d applied to the gate of the P-channel transistor via the second transfer gate constituted by P-channel transistors 6, 7, 8 is power supply voltage V _DD , The channel transistor 9 is off.

Next, when the input signal a goes high, the output signal b of the inverter 1 goes low. As a result, signal c applied to the gate of N-channel transistor 5 via the first transfer gate formed of N-channel transistors 2, 3, and 4 is at the ground level.
Therefore, N-channel transistor 5 is turned off.

On the other hand, the signal d applied to the gate of the P-channel transistor 9 has a potential difference between the source and the drain of the P-channel transistors 6, 7, and 8 constituting the second transfer gate. Also has a high potential. For this reason, the signal e output from the output terminal 10 is at the L level, but has a potential that greatly increases from the ground potential.

In this embodiment, as described above, since the change in the potential of the output terminal 10 is small, the time required for the transition of the output level is short. Further, the charge / discharge current value of the capacitive output load becomes smaller than before, and the fluctuation of the power supply voltage and the potential of the ground can be suppressed, which causes inconveniences such as malfunction of the semiconductor integrated circuit and reduction in operation speed. Can be avoided.

FIG. 3 is a circuit diagram showing an output circuit according to a second embodiment of the present invention.

This embodiment is different from the first embodiment in that three transfer gates are connected in parallel between the inverter 1 and the transistors 5 and 9, respectively. Since the third embodiment is the same as the first embodiment, the same reference numerals in FIG. 3 denote the same parts as in FIG. 1, and a detailed description thereof will be omitted.

In this embodiment, a transfer gate constituted by N-channel transistors 2, 3 and 4 and a transfer gate constituted by N-channel transistors 12 and 13 are provided between the inverter 1 and the gate of the N-channel transistor 5. The gate and a transfer gate constituted by the N-channel transistor 11 are connected in parallel.

A P-channel transistor 6 is connected between the inverter 1 and the gate of the P-channel transistor 9.
A transfer gate formed by P, 7 and 8, a transfer gate formed by P-channel transistors 14 and 15, and a transfer gate formed by P-channel transistor 16 are connected in parallel.

Then, a signal obtained by inverting the drive signal of the transfer gate constituted by the transistors 2, 3, 4 by the inverter 17 is supplied to the transfer gate constituted by the transistors 6, 7, 8 as the drive signal. The two transfer gates operate as a pair. In addition, transistors 12, 1
3 is obtained by inverting the driving signal of the transfer gate formed by the inverter 3 by the inverter 18.
5 is provided as a driving signal to the transfer gate constituted by the transfer gates 5. The two transfer gates operate as a pair. Further, a signal obtained by inverting the driving signal of the transfer gate constituted by the transistor 11 by the inverter 19 is the transistor 16.
Are provided as driving signals for the transfer gates constituted by the two transfer gates, and these two transfer gates operate as a pair.

In this embodiment, three pairs of transfer gates having different numbers of stages (number of transistors) are provided. By controlling each pair of transfer gates, the potential of the output terminal 10 at the H level and the L level is controlled. Can be changed. Therefore, in the present embodiment, in addition to obtaining the same effects as those of the first embodiment, in addition to the case of the H level and the L level depending on the output load and the input threshold value of the receiving device, etc. Can be set to an optimum value.

[0027]

As described above, according to the present invention, the first transfer gate and the P transfer transistor each constituted by an N-channel transistor are provided between the inverter and the N-channel transistor and the P-channel transistor connected to the output terminal. Since the second transfer gate constituted by the channel transistor is interposed, the transition width of the output signal is small, the level transition time is shortened as compared with the related art, and the charge and discharge current of the capacitive load causes In this case, the fluctuation of the power supply voltage and the ground voltage can be avoided, and the malfunction and the decrease in the operation speed of the semiconductor device can be avoided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an output circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing the same operation.

FIG. 3 is a circuit diagram showing an output circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional output circuit.

[Explanation of symbols]

 1, 17 to 19; inverters 2 to 5, 11 to 13, 21; N-channel transistors 6 to 9, 14 to 16, 20; P-channel transistors 10; output terminals

Claims (1)

(57) [Claims] 1. An inverter for inverting an input signal, first and second transfer gates each having an input terminal to which the output of the inverter is provided, and a drain to which the output of the first transfer gate is provided. An N-channel transistor whose source is connected to the output terminal, and the gate of which is connected to the second terminal.
And a P-channel transistor having a drain supplied with a low-potential-side power supply voltage and a source connected to the output terminal, and the first transfer gate is constituted by an N-channel transistor. An output circuit, wherein the second transfer gate comprises a P-channel transistor.