JP3055165B2 - Output buffer circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an output buffer circuit, and more particularly to a CMOS output buffer.

[Conventional technology]

A conventional output buffer will be described with reference to FIGS. 7 and 8 (a) and (b). FIG. 7 is a circuit diagram showing a conventional output buffer CMOS circuit of an inverter. In Figure 7, the P-channel transistor 21, and the capacitive load C _L with the N-channel transistor 22 output buffer. The transistors 21 and 22 form an inverter circuit, and generally have a large driving capability and large transistors.

The operation of FIG. 7 will be described with reference to FIGS. 8 (a) and 8 (b). In FIG. 8 (a), first, when the output load _CL is small, the input IN is at a low level (hereinafter referred to as “L”) →
When the level becomes high (hereinafter referred to as “H”), the output O is output through an inverter circuit composed of transistors 21 and 22.
UT changes from H to L. That is, the input IN changes from H to L, and the output OUT changes from L to H. In both cases, the output waveform OUT has steep falling and rising waveforms because the output load _CL is small. As shown in FIG. 8 (b), when the output load _CL is large, the output waveform OUT has a gentle falling and rising waveform.

[Problems to be solved by the invention]

In such a conventional circuit, when the load is large (FIG. 8B), the output waveform becomes dull and the speed becomes slow.

In order to increase the speed, transistors 21 and 22
If you make the size larger, the speed will be faster,
There is a problem that a through current from the power supply to the ground increases, switching noise increases, and power consumption also increases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an output buffer circuit which solves the above-mentioned problems and requires a small through current and a small switching noise.

[Means for solving the problem]

The configuration of the present invention includes an input terminal to which a signal is input, an output terminal to which a signal is output, a first inverter having an input terminal connected to the input terminal and an output terminal connected to the output terminal, A second inverter having a threshold value of 1 and an input terminal connected to the output terminal; a second inverter having a threshold value higher than the first threshold value;
And a third inverter having an input terminal connected to the output terminal and a source / drain path connected in series between a high potential power supply and the output terminal, and one gate connected to the input terminal. P-channel first and second field-effect transistors having the other gate connected to the output terminal of the second inverter, and a source-drain path between the low-potential power supply and the output terminal. N-channel third and fourth field-effect transistors connected in series, one gate being connected to the input terminal, and the other gate being connected to the output terminal of the third inverter. I do.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an output buffer circuit according to a reference example of the present invention.

Referring to FIG. 1, the present embodiment includes a first inverter circuit of a conventional output buffer including only a P-channel transistor 6 and an N-channel transistor 7.
P-channel transistor 1, second P-channel transistor 2, and second N-channel transistor 3
And a second OCMS inverter circuit including a first N-channel transistor 4 and an inverter 5. The same signal as the input signal IN is applied to the gates of the transistors 1 and 4 and the transistor 2
A signal obtained by inverting the output OUT signal of the first inverter circuit by the inverter 5 is input to the gate of the transistor 3 and the gate of the transistor 3.

The operation of FIG. 1 will be described with reference to the waveforms of FIGS. 2 (a) and 2 (b).

In FIG. 2A, when the input signal IN changes from L to H, the transistor 6 is turned off and the transistor 7 is turned on.
The output signal OUT changes from H to L, and the transistor 1 is also turned off.
The transistor 4 is also turned on. At the node a, the signal of the output OUT passes through the inverter 5 and changes from L to H. Therefore, the transistor 2 is turned off and the transistor 3 is turned on. At this time, there is a time difference between the timing when the transistor 1 and the transistor 2 are turned off and the timing when the transistor 3 and the transistor 4 are turned on, so that the gate potentials of the transistors 1 to 4 do not become the same intermediate potential. Input signal IN
However, when H → L, the transistor 6 is turned on, the transistor 7 is turned off, and the output OUT changes from L → H. The transistor 1 is turned on, and the transistor 4 is turned off. Node a is H → L
Becomes Therefore, the transistor 2 is turned on and the transistor 3 is turned off. Thus, the discharge of the load C _L, will serve to accelerate the speed of charging. When the load _CL is small (FIG. 2A), the falling and rising waveforms of the output waveform OUT are steep, but when the load _CL is large (FIG. 2B), the logical threshold of the inverter 5 is increased. until it exceeds the voltage falling of the output OUT, while the rise of the waveform W _1, W ₃ is gradual, beyond which, the transistor 3 is turned on, accelerate the discharge of the load C _L, or transistor 2 is turned on And accelerates charging, resulting in steep falling and rising waveforms W ₂ , W
_{And 4} . Therefore, the speed also increases.

3 and 4 are a circuit diagram and a timing diagram showing an output buffer circuit according to an embodiment of the present invention. In FIG.
This embodiment is different from the reference example in that the inverters 5 for driving the transistors 2 and 3 in FIG. In that the inverter 9 is replaced. When the load _CL is small (Fig. 4 (a))
Although it is almost the same as the reference example, when the load _CL is large (FIG. 4B), for example, when the output OUT waveform falls, the inverter 9 has a high logic threshold voltage.
As soon as the potential of the output OUT starts to decrease, it is inverted, the node b becomes H, and the transistor 3 is turned on. Also, OUT
When the waveform rises, since the logic threshold voltage of the inverter 8 is low, the inverter 8 is inverted as soon as the potential of the output OUT starts to rise, the node a becomes L, and the transistor 2 is turned on. Therefore, the discharge of the load C _L, so that the more accelerated than in Reference Example charging. That is, at the time of inversion, the gentle waveforms W ₁ and W
₃ , steep waveforms W ₂ and W ₄ are obtained.

FIG. 5 shows the first P-channel transistor 1 and the second P-channel transistor 2 described above,
FIG. 10 is a circuit diagram of another reference example in which the N-channel transistor 4 and the second N-channel transistor 3 are replaced.

FIG. 6 shows another embodiment in which the only inverter 5 of the circuit of FIG. 5 is divided into a first inverter 8 and a second inverter 9, which are used as gate inputs of the transistors 2 and 3, respectively. It is a circuit diagram.

The same effects as in FIGS. 1 and 3 can be obtained in the other reference examples and other embodiments of FIGS. 5 and 6, respectively.

〔The invention's effect〕

As described above, the present invention adds a CMOS inverter composed of two P-channel transistors and the same two N-channel transistors, so that even if the output load is large, the CMOS inverter can pass through. Since no current flows, there is an effect that the switching speed of the through current is not increased, the power consumption due to the through current is not increased, and the speed is increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an output buffer circuit according to a reference example of the present invention. FIGS. 2 (a) and 2 (b) are waveform diagrams showing operation waveforms of the reference example of FIG. 4 is a circuit diagram showing an embodiment of the present invention, FIGS. 4 (a) and 4 (b) are waveform diagrams showing the operation waveforms of FIG. 3, and FIG. 5 is another reference example of the present invention. FIG. 6 is a circuit diagram showing another embodiment of the present invention, FIG. 7 is a circuit diagram showing a conventional output buffer circuit, and FIGS. 8 (a) and 8 (b) 8 is a waveform chart showing the operation waveforms of FIG. 1,2,6,21 …… P-channel transistor, 3,4,7,22 ……
N-channel transistor, 5,8,9 …… Inverter, W ₁ ,
W ₂ , W ₃ , W ₄ ... waveform.

Claims (1)

(57) [Claims] An input terminal for receiving a signal, an output terminal for outputting a signal, a first inverter having an input terminal connected to the input terminal and an output terminal connected to the output terminal;
A second inverter having a first threshold and an input connected to the output terminal, and a third inverter having a second threshold higher than the first threshold and having an input connected to the output terminal. An inverter, a source-drain path connected in series between the high-potential power supply and the output terminal, one gate connected to the input terminal, and the other gate connected to the output terminal of the second inverter. P-channel type first and second
A source-drain path is connected in series between the low-potential power supply and the output terminal, one gate is connected to the input terminal, and the other gate is connected to the output terminal of the third inverter. An output buffer circuit comprising N-channel third and fourth field-effect transistors connected to each other.