JPH0332113A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To evade a through-current at the final stage output and to reduce generation of noise by separating an input signal to a final output stage circuit and varying the leading and trailing speed of a signal respectively. CONSTITUTION:When an input signal A changes from L to H, an N-channel transistor(TR) 5 is turned on, the discharge time is controlled by a capacitor 7 and a signal B is gradually discharged. Moreover, when the input signal A changes from H to L, a P-channel TR 4 is turned on, the the signal B is quickly charged. Thus, the charging time of the output signal B of a pre-stage circuit I is quickened and the discharge time slows down, and the charging time of an output signal C in a pre-stage circuit II shows down and the discharge time is quickened by utilizing the similar effect. Since the N-channel TR 3 is turned on by the signal C after the P-channel TR 2 is turned off by the signal B, the through-current at the final output stage circuit is suppressed to reduce generation of noise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an output circuit of a semiconductor integrated circuit formed on a semiconductor substrate using a CMO transistor.

[Conventional technology]

FIG. 3 is a circuit diagram showing the output circuit of a conventional semiconductor integrated circuit, in which a P-channel transistor (2) and an N-channel transistor (3) are simply connected in series, this connection is set as output terminal 0, and the input ( ), inverter 0 is connected to P-channel transistor (2) and N-channel transistor (2), respectively.
The threshold values of the P-channel transistor (2) and N-channel transistor (3) connected to the gate of 3) are V+hp = -0.7V, respectively.

If V+hs = 0.7 V, when 5V is applied to the power supply.

The P-channel transistor (2) turns on when the input voltage is 4.3V or less, and the N-channel transistor (3) turns on when the input voltage is 4.3V or less.
) becomes ON when the input voltage is 0.7V or higher.

Therefore, when the input voltage is between 0.7 V and 4.3 V, both the P-channel transistor (2) and the N-channel transistor (3) are in the ON state, so a through current flows.

[Problem that the invention attempts to solve]

As shown in Figure 4, conventional semiconductor integrated circuit devices are configured as described above, and since the inputs are in the same phase, there are parts where through-current flows, which causes noise and other problems. there were.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit device having an output circuit that suppresses through-current and generates less noise.

[Means to solve the problem]

The semiconductor integrated circuit device according to the present invention has a first P-channel transistor and a first N-channel transistor connected in series. In an output circuit having a continuous final output stage, the gate of the first P-channel transistor has @3 N-channel transistors connected in series between the drain of the second P-channel transistor and the drain of the second N-channel transistor. The drain and source are connected respectively, the gate of the added third N-channel transistor is connected to the power supply, a capacitance is added to the source connected to the drain of the second N-channel transistor, and the second P The drain of the channel transistor is connected as an output to the gate of the first P-channel transistor, and the source of the fourth P-channel transistor is connected in series between the drain of the third P-channel transistor and the drain of the fourth N-channel transistor. and the drain are connected respectively, and the added fourth
The gate of the P-channel transistor is grounded and fpI3
A capacitor is added to the source connected to the drain of the P-channel transistor, and the drain of the fourth N-channel transistor is connected as an output to the gate of the first N-channel transistor. a channel transistor and a second . The respective gates of the fourth N-channel transistors are connected to each other to serve as an input terminal.

[Effect]

The output circuit of the present invention reduces the through current in the final output stage by separating the input signals to the P-channel transistor and N-channel transistor of the final output stage and making them out of phase.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First, the input signal generation circuit for the final output stage will be described. In FIG. 1, the input signal A goes from 5L' to
When reversed, the P-channel transistor (4) is OFF.
Since the gate of the N-channel transistor (6) is connected to the power supply, the N-channel transistor (6) is always in the ON state. Therefore, both N-channel transistors (5) and (6) are in the ON state, and the charge stored in the capacitor (7) is discharged, so that the signal B becomes an L umbrella.

At this time, the discharge time is controlled by the capacitor (7) connected between the N-channel transistors (5) and (6), and the signal B gradually discharges to tL as shown in FIG.

Next, when the input signal A changes from 1H' to 1L', the N-channel transistor (5) becomes OFF. However, since the P-channel transistor (4) is turned on, the signal B is charged and becomes H'. At this time, if there is no N-channel transistor (6), the charging time will be gradually charged due to the influence of the capacitor (7), but with the addition of the N-channel transistor (6), the capacitor (7) will be charged gradually. ), it is gradually charged, but signal B can be charged quickly. Therefore, by adding an N-channel transistor (6) as shown in the figure, the charging time of the output signal B of this front stage circuit I can be made faster.
The discharge time can be slowed down. Also, by utilizing the same phenomenon, the charging time of the output signal C is slowed down in the front-stage circuit L.
Discharging time can be made faster. When the above-mentioned pre-stage circuit signal is input to the final output stage circuit, the input signal becomes
When changing from # to tL#, signal B rises quickly, so P
Channel transistor (2) turns OFF quickly, but signal C rises gradually, so N-channel transistor (3)
turns on with a delay. Therefore, after the P-channel transistor (2) is turned off by the signal B, the N-channel transistor (3) is turned on by the signal C, so that there is no through current in the final output stage circuit.

Even when the signal A changes from $L# to H4, the N-channel transistor (3) is turned OFF by the signal C.

After that, the P-channel transistor (2) is turned on by the signal B, so that the through current disappears.

〔Effect of the invention〕

As described above, according to the present invention, by separating the input signals to the final output stage circuit and changing the rising and falling speeds of each signal, it is possible to eliminate the through current in the final output stage, which generates noise. This has the effect of providing a semiconductor integrated circuit device with less noise.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an output circuit of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a timing waveform diagram of each signal in FIG. 1, and FIG. 3 is a circuit diagram showing an output circuit of a conventional semiconductor integrated circuit. The circuit diagram shown in FIG. 4 is an explanatory diagram showing input/output characteristics in the final output stage circuit. In the figure, (1) is the power supply, (2), (4),
(8), αq is a P-channel transistor, (3), (
5), (6), and (9) are N-channel transistors, and (7) and (b) are capacitances. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In an output circuit of a semiconductor integrated circuit having a final output stage in which a first P-channel transistor and a first N-channel transistor are connected in series, a second P-channel transistor is connected to the gate of the first P-channel transistor. The drain and source of a third N-channel transistor are connected in series between the drain and the drain of the second N-channel transistor, the gate of the added third N-channel transistor is connected to a power supply, and the drain of the second N-channel transistor is A capacitor is added to the source connected to the drain of the channel transistor, and the drain of the second P-channel transistor is connected as an output to the gate of the first P-channel transistor, and further connected to the drain of the third P-channel transistor. The source and drain of a fourth P-channel transistor are connected in series between the drains of the fourth N-channel transistors, the gate of the added fourth P-channel transistor is grounded, and the drain of the third P-channel transistor is connected to the drain of the third P-channel transistor. A capacitor is added to the source connected to the fourth N-channel transistor, the drain of the fourth N-channel transistor is connected as an output to the gate of the first N-channel transistor, and the drain of the fourth N-channel transistor is connected to the gate of the first N-channel transistor. 4 N
A semiconductor integrated circuit device characterized in that each gate of a channel transistor is connected to serve as an input terminal.