JPS61248614A - Pulse delay circuit - Google Patents

Abstract

PURPOSE:To attain a pulse delay time control by a single control voltage by using a MOS transistor (TR) so as to change an output line resistance value on output lines of a half of even number of lines when a pulse edge of an input pulse is transmitted on the lines. CONSTITUTION:MOS TRs 21 and 22, 31 and 32, and 41 and 42 form respectively the inverter of complementary MOS. Since the quantity of the conductive resistance value of a conductor path is controlled by a voltage 6 fed to gate terminals of N-MOS TRs 22, 23, the output line resistance is made variable when the N-MOS TR 22 or 32 is turned on with an inverter 2 or 3 at low level output state. Since the conductive resistance is lowered more as an applied voltage 6 to the gate of the N-MOS TRs 23, 33 gets higher, the variable control of the delay time decreasing/increasing t1, t2 is attained by increasing or decreasing the applied voltage so as to make the gradient of the discharging curve steep or gentle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pulse delay circuit used in digital circuit devices and the like, and particularly to a pulse delay circuit suitable for varying delay time.

[Background of the invention]

As a conventional example of a pulse delay circuit, Japanese Patent Application Laid-Open No. 59-506
There is one described in Publication No. 10. In this example, the delay time is variable using one control voltage, and the output pulse duty (the ratio of the high-level output period or low-level output period to the repetition period) is detected and feedback is applied, so the delay time remains constant. This is effective when delaying an input pulse with a repetition cycle while strictly maintaining its duty, or when shaping the waveform to obtain a desired duty.

However, a voltage comparator is required as a circuit component;
The circuit scale becomes larger. Furthermore, it is difficult to use it to delay pulses whose repetition period is not constant.

[Purpose of the invention]

An object of the present invention is to eliminate the drawbacks of the prior art described above and use a simple circuit configuration to make the delay time of a pulse variable with one control voltage. It is an object of the present invention to provide a pulse delay circuit which can be used for delaying a pulse while maintaining its pulse width (high level output time or low level output period) with high precision.

[Summary of the invention]

In order to achieve this object, the present invention connects a plurality of logic gates in series, and controls the pulse delay time by varying the line resistance of the pulse transmission line from one logic gate to the input of the next logic gate. In the delay circuit, by using only either a P-channel MOS transistor or an N-channel MOS transistor as a variable element for line resistance, it is possible to vary the delay time with a single control voltage, and the delay time can be varied with a single control voltage. Variable resistance is applied to an even number of pulse transmission lines, and on half of these lines, the delay time of the rising phase of the input pulse is controlled, and on the other half of the lines, the delay time of the falling phase of the input pulse is controlled. The feature is that by configuring this, it is possible to preserve the pulse width of the input and output of the delay circuit.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a pulse delay circuit according to the present invention, in which 1 is an input pulse, 2.3 is an output resistance variable inverter, 4 is an inverter used as a waveform shaping gate, and 5 is a delayed pulse delay circuit. 6 is the delay time amount control voltage, 21°31.41 is a P-channel MOS transistor (hereinafter P-H) which is a component element of the inverter.
05T), 22, 32.42 are N-channel MOS transistors (hereinafter abbreviated as N-HO5T) which are also component elements of the inverter, and 23.33 is a variable output resistance value of the inverters 2 and 3, respectively. N-H05T, 7.8 is a capacitor placed at the input section of the inverters 3 and 40.

In the same figure, HO5T 21 and 22.31 and 32,
41 and 42 are respectively complementary Mos (c −xos
) form an inverter. N-MO5T 22
, 23 can control the magnitude of the conduction resistance value of the conductive path by the voltage value of the voltage 6 applied to the gate terminal, so when the inverter 2 or 3 outputs a low level, that is, N −
The output line resistance value when HO5T 22 or 32 is ON (low resistance state; at this time, P-MO5T 21 and 32 are OFF, that is, high resistance state) is varied. Note that as the capacitor 7.8, it is also possible to use a stray capacitance parasitic to the inverter input section, and in this case, there is no need to add a capacitor.
゛The voltage waveforms at each point in Figure 1 are shown in Figure 2. In Fig. 2, when input pulse 1 is at logic level “0”, F
-HO5T 21 is ON, N -HO5T 22
is turned OFF, and the input terminal of the inverter 3 is connected to the power supply line 10 having a voltage value of the logical "1" level, so the input pulse 9 of the inverter 3 becomes the 11" level.

At this time, P -MO5T 31 is OFF L, N -M
Since O5T32 is turned on, the input terminal of inverter 4 is N.
- It is connected to the "0" level power supply line (ground in FIG. 1) via the -HO5T 33, and the input pulse 11 of the inverter 4 becomes the "0" level after the level fluctuation transient time described later. Furthermore, at this time, P-MO5T al is ON
, N-HO5T 42 is turned off, and the output pulse 5 becomes "1# level."

Next, when the input coupler level changes to +1, P-HO5T 21 turns OFF, N
-MO5T22 is ONL, the pulse 9 draws a discharge curve determined by the capacitor 7 and the conduction resistance of the N-MO5T 25, and descends from the "1" level to the +0" level. The level force of the pulse 9, the threshold of the inverter 3 At the point when the P-HO
5T31 is turned ON, N-MO5T'52 is turned OFF, and the pulse 11 becomes 11 levels.

The simultaneous double pulse 5 becomes the "0" level. Through the above operations, a pulse 5 is obtained in which the rising edge of the pulse 1 (level change part from "0 level color" to "1" level) is delayed by the time t.

After the above, when pulse 1 changes from @1 level to 1IOl level, P-HO5T 21 is ON, N-MO5
T22 is OFF L-pulse 9 immediately changes from "0" level to "1" level. At this time, P-HO5T31
is OFF, N-HO5T 32 is turned ON, and pulse 11 draws a discharge curve determined by the capacitor 8 and the conduction resistance of N-MO5T 33, and changes from "1" level to 0.
Level [Fll].When pulse 110 passes the threshold level of level inverter 4, pulse 5 becomes "0".
Changes from level to "1" level.

As a result of this operation, the falling edge of pulse 1 (the level change part from +1 level to 10'' level) is output as pulse 5 with a delay of time t.N-MO5T 23 , 3
3 has a characteristic that the higher the voltage 6 applied to the gate terminal, the lower the conduction resistance becomes. Therefore, by increasing the applied voltage and making the slope of the discharge curve steeper, tl + tt
Variable control of the delay time is possible by increasing t and +it by decreasing the value of t, +it or by lowering the applied voltage to make the slope of the discharge curve gentler.

Here, if MOS transistors manufactured using a semiconductor manufacturing mask pattern having the same geometrical shape are used for the N-HO5T 23 and 33, when the same control voltage 6 is applied, the The conduction resistance values are almost the same. Therefore, by appropriately setting capacitors 7 and 8 using external capacitors, etc., the configuration shown in FIG. 1 can be used to maintain t and t2 the same using a single control voltage 6. You can control the amount of time.

In addition, in Fig. 1, a configuration is shown in which a polarity-inverted pulse of the input pulse is obtained as an output pulse 5 obtained by delaying input pulse 1, but an inverter similar to 4 (however, capacitor 8 is not required) is installed after inverter 4. It is also easy to obtain delayed output pulses having the same polarity as the input pulses by adding a 2-channel inverter 4 or using a known non-inverting logic gate in place of the inverter 4.

FIG. 3 shows a configuration example of an output line resistance variable logic gate circuit that can be used in place of inverters 2 and 3 in FIG. 1.

Figure 3(a) shows P-MO5T 121 , N-MO
An inverter composed of 5T 122, p-MO5
T 121 oN (At this time, N-HO5T 122 is O
The output line resistance of FF) is made variable by P-MO3T 123. Connect the pulse input terminal to 13.
Setting the output terminal as 14, using two circuits with the configuration shown in FIG. 3 (α) instead of 2 and 3 in FIG. 1, and applying a common applied voltage 6 to the two configurations, the same pulse delay as in FIG. Time can be controlled. Hiko, in this case, instead of the discharge curve of pulses 9 and 11 in Figure 2, change the charging curve (transient waveform characteristics of the part where pulses 9 and 11 change from "0" level to 1 degree level). The delay time is controlled by the P-HO5T 123. Since the P-HO5T 123 has a characteristic that its conduction resistance value decreases as the voltage applied to the gate terminal decreases, the delay time is set such that the lower the applied voltage 6, the smaller the delay time. Becomes control.

FIG. 3(A) shows P-MO5T 151 , N −
After the output end of a normal inverter consisting of MO5T 152, P-MO5T 153 and N-MO5T 15
4 is inserted, and P-MO5T 151
When N-MO5T152 is ON (at this time, N-MO5T152 is opp), the output line resistance is approximately equal to the conduction resistance of P-MO5T15'5, and when N-HO5T152 is ON (at this time, P-
The output line resistance of MO5T 151 (opp) is approximately N
- It becomes the conduction resistance of MO5T 154.

Therefore, the gate terminal 16 of F-HO5T 153
is connected to the ``0'' level power supply line (ground in Figure 6) to keep the transistor always on, and N - HO8
The control voltage 6 is applied to the gate terminal 17 of T 154, and the input terminal 15. If the output terminal is 14, it becomes the same functional block as 2 or 3 in FIG. In addition, the gate terminal 17 of the #-MO5T 154 is connected to the power supply line 10 at the ``V level, so that the transistor is always turned on.
Assuming N state? If the configuration is such that the control voltage 6 is applied to the gate terminal 16 of the -H05T 153, as shown in FIG.
This is the same functional block as the configuration example α).

Therefore, for example, maple in both 2 and 3 of Figure 1 (Fig.
It is also possible to use two circuits having the configuration h), or it is also possible to use only one of the circuits 2 and 3 in FIG. 1 with the circuit having the configuration shown in FIG. 3(A). Also, Figure 3 (a
) and (h) are also possible.

As explained above, P-MOS transistor or N
- By using only one of the MOS transistors as a line resistance control element, it becomes possible to control the delay time with one control voltage. However, in this case, 1
In controlling the line resistance of the output line at the two points, only one pulse edge of the input pulse can be effectively delayed, and the other pulse edge cannot be delayed. The control is configured so that the rising edge of the input pulse is delayed by variable line resistance on one side, and the falling edge is controlled by variable line resistance on the other side, so that it is possible to delay the input pulse while preserving the pulse width of the input pulse. I have to.

FIG. 4 is a circuit diagram showing another embodiment of the pulse delay circuit according to the present invention, in which 18 and 19 are logic gates with variable output line resistance; Third
FIG. 2 is a circuit block diagram as shown in FIG.

The difference between this embodiment and the embodiment shown in FIG. 1 is that a non-inverting gate 20 is inserted between output line resistance variable logic gates 18 and 19. FIG. 5 shows operating waveforms when logic game (18.19) uses 2 and 3 of FIG. 1.

By inserting the non-inverting gate 20, a pulse 9', which is a waveform-shaped version of the pulse 9, is input to the second stage output line resistance variable logic gate 19, but other operations are as shown in FIG. is similar to, and the rising edge of input pulse 1 at the output line resistance variable logic gate 18 is
At step 19, the delay time of each falling edge is controlled.

The configuration shown in FIG. 4 is particularly suitable when the circuit of the present invention is integrated into an LSI having a C-MO5 structure. The reason for this will be explained below.

A circuit diagram of the non-inverting gate 20 of FIG. 4 is shown in FIG. 201 and 203 are P-HO3T.

202 and 204 are N-HO3T, which are constructed by connecting inverters in series.

Here, the input part of the non-inverting gate, that is, P-MO8T 201, N-MO5T 202
If an inverter section configured with the same geometric shape as the inverter shown in FIG. 1 or 4 is used, the input stray capacitance of the non-inverting gate 20 shown in FIG. Since the stray capacitance and the external stray capacitance can be made to have almost the same capacitance value, there is no need to connect a capacitor outside the LSI and adjust its capacitance value.
It is possible to realize a pulse delay that maintains the pulse width of the input pulse with high accuracy.

FIG. 7 is a circuit diagram showing still another embodiment of the pulse delay circuit of the present invention, in which 71 and 72 are voltage comparison amplifiers;
3.74 is the reference voltage, 75.76 is P-HO5T, 77
, 78 are diodes.

In FIG. 7, the voltage comparison amplifiers 71 and 72 may use commercially available bipolar transistors. As is well known, the voltage comparison amplifiers 71 and 72 are
Connect the reference voltage 75.74 to the negative input terminal,
If an input pulse is applied to the positive input terminal, it operates as a non-inverting gate. Voltage comparison amplifier 71.
P-MO5T75 and diode 77 are used as the first stage variable line resistance logic gate where the line resistance at 1" level output is variable.

Voltage comparison amplifier 72. The P-MO5T76 and the diode 7B constitute a second stage variable line resistance logic gate whose line resistance is variable when outputting a 1" level.

FIG. 8 shows operational waveforms of each part of the embodiment shown in FIG. 7.

The voltage comparator amplifier outputs a pulse with the same polarity as input pulse 1, but since the conduction resistance of P-MO8T 75 is inserted into the output line only when the "1" level is output, this resistance and the floating input of the inverter 4' Due to the integral characteristic with the capacitance, the input end pulse 79 of the inverter 4' has a waveform with a rounded rising portion as shown in FIG. 8 79. When this waveform is shaped by an inverter 4', an output pulse 80 is obtained, and the delay (time t+) of the rising edge of the input pulse 1 is realized.

Similarly, the input pulse 81 of the inverter 4 has a waveform that is the rising edge of the input pulse 8o of the voltage comparator amplifier 72, so if this waveform is shaped by the inverter 4, the falling edge of the input pulse 1 can be smoothed. delay (time t2)
is realized, and the output pulse 5 has the waveform shown in FIG. 8.

Also in the configuration example shown in FIG. 7, since only P-HO5T can be used to vary the line resistance, delay control is possible with a single control voltage 6.

Gao, P-MO5T75,7 as a line resistance variable element
6, use #-HO5T, diode 77.7
8 in the opposite direction as shown in Figure 7, or insert it in the direction shown in Figure 3 (
It is also possible to use a parallel connection of N-MO5T and P-MO5T shown in h).

The embodiments shown in FIGS. 1, 4, and 7 described above are all examples in which two output line resistance variable logic gates are used, but an even number of output line resistance variable logic gates of two or more are used. If half of them are configured to delay the rising edge of the input pulse and the other half are configured to delay control the falling edge of the input pulse, P-HO5 can be used as a variable line resistance element.
Using either T or N-HO5T, that is, a single delay time control voltage, enables pulse delay control that preserves pulses.

〔Effect of the invention〕

As explained above, according to the present invention, the output line resistance at the time of pulse essino transmission of one of the input pulses on half of the output lines of the even number of output lines in which the MOS transistors are inserted is The value is changed by changing the output line resistance value during transmission of the other pulse edge of the input pulse on the remaining half of the output lines.
Since the pulse can be delayed while maintaining the pulse width of the input pulse with high precision, it is possible to control the pulse delay time using a single control voltage, and a simple circuit can be used without requiring a voltage comparator as an essential component. Furthermore, it is possible to realize the entire circuit using a C-MOS process, which is particularly advantageous for integration into an LSI with a c-uoS structure, and is superior to the above-mentioned disadvantages of the conventional technology. A functional pulse delay circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a pulse delay circuit according to the present invention, FIG. 2 is a waveform diagram of each part of FIG. 1, and FIG. 3 is an implementation of an output line resistance variable logic gate different from FIG. An example circuit diagram, FIG. 4 is a block diagram of another embodiment of the pulse delay circuit according to the present invention, FIG. 5 is an operation waveform diagram of each part of FIG. 4,
6 is a circuit diagram of the non-inverting gate shown in FIG. 4, FIG. 7 is a block diagram of still another embodiment of the pulse delay circuit according to the present invention, and FIG. 8 is a diagram of operation waveforms of each part of FIG. 7. . 1・・・・・・・・・・・・・・・・・・・・・・・・
...Input pulse 2.3.18.19...
・Output line resistance variable logic gate 4.4'...
・・・・・・・・・・・・・・・Inverter 5・・・・・・
・・・・・・・・・・・・・・・・・・・・・Output pulse 21.31.41・・・・・・・・・P channel MOS transistor 22, 32.42・・・・・・
...N-channel MOS transistor

Claims (1)

[Claims] In a pulse delay circuit in which a plurality of logic gates are connected in series and an input pulse is applied to the first stage logic gate, and a delayed output pulse is applied to the final stage logic gate output, the input pulse is applied from a different even number of logic gates to the next stage logic gate. A conductive path of a MOS transistor is inserted in series in an output line leading to an input end of a logic gate, and the gate terminals of the MOS transistors are connected in common to serve as a voltage application terminal for controlling the groove path resistance value of the MOS transistor; The output line resistance value at the time of transmission of one pulse edge of the input pulse is determined by half of the output lines of the even number of output lines in which the MOS transistors are inserted, and the output line resistance value at the time of transmission of one pulse edge of the input pulse is determined by the output line resistance value of the other half of the output lines by the other half of the output lines. 1. A pulse delay circuit characterized in that the output line resistance value is changed during pulse edge transmission.