JPS63185054A - Voltage step-up circuit - Google Patents

Abstract

PURPOSE:To enhance the reliability of operation than in a conventional circuit and to enhance voltage step-up efficiency, by constituting a plurality of transistors from the input side in an enhancement type, and constituting transistors in the rear stage in an intrinsic type or a depression type. CONSTITUTION:The constitution of a voltage step-up circuit is approximately the same as a conventional circuit. A front part 1 of the circuit is constituted by N-channel MOS transistors T1-TL of an enhancement type 2. An intermediate part 3 is constituted by N-channel MOS transistors TL+1-Tm of an intrinsic type 4. A rear part 5 is constituted by N.channel MOS transistors Tm+1-Tn of a depression type 6. These transistors T1-Tn are connected in a diode mode, i.e., the drains and the gates are mutually connected. An input voltage Vi is supplied to the drain and the gate of the first transistor T1. An output voltage Vo is taken out of the source of the transistor Tn.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention, for example, boosts a power supply potential supplied from an external system into an integrated circuit, and applies this boosted power supply potential to an internal circuit. The present invention relates to a booster circuit used for supplying electricity, etc.

(Prior Art) An example of a conventional booster circuit is shown in FIG. This booster circuit includes a plurality of enhancement type N-channel MOS transistors Ql-Qn whose drain-source current paths are connected in series.

Each of these transistors Q1-Qn is diode-connected, that is, its drain and gate are interconnected. Even-numbered transistors Q2 and Q4 when viewed from the input side
, ・=, At the gate of Qn-1, a capacitor C2,
A clock signal φ is supplied through C4, . . . , Cn-1, and odd-numbered transistors Q3, Q5, . . . , Qn are supplied with an inverted clock signal φ via capacitors C3, C5, . . . , Cn, respectively.

In other words, in this booster circuit, the input terminal v1 is supplied to the drain and gate of the first transistor Q.
1, a clock signal φ and an inverted clock signal φ
The configuration is such that a plurality of transistor sets TSI to TSN each consisting of two transistors whose conduction is controlled by a plurality of stages are connected in cascade.

Next, the operation of such a booster circuit will be explained with reference to the timing chart of FIG.

Let vth be the threshold voltage of each transistor Ql-Qn when the substrate bias voltage vB is 0 [v], and let Δv be the change in threshold voltage due to this substrate bias voltage vB.
B, the actual threshold voltage of each transistor Q1 to Qn is vth+ΔVa.

Therefore, if the amplitude of the clock signal φ is Vφ, the potential Va at the connection point a between transistors Q1 and Q2 when the clock signal φ−0 [v] is Vi − (Vth + AVi) due to the cutoff condition of the transistor Q1. It becomes (-vaO). At this time, the potential vb of the connection point between transistors Q2 and Q3 becomes Vφ (-V bO) as the inverted clock signal φ rises. Also, at this time, the potential VC of the connection point C between transistors Q3 and Q4
is Vφ− due to the cutoff condition of transistor Q3.
(V th+ΔVφ) (-V co).

Next, when the clock signal φ rises, the potential Va at the connection point a at this time becomes Vi − (Vth + ΔV1) + Vφ because the transistor Q1 is cut off (
-Val). At the connection point, the inverted clock signal φ-0[
v], so the potential vb at this time is the transistor Q
According to the cutoff condition of 2, Vat −(Vth+AV
al) and naru (-Vbl).

Further, the potential Ve at the connection point C at this time is vco+Vφ (-V cl).

When the clock signal φ falls again, the potential Va at the connection point a returns to VaO, but the potential vb at the connection point A at this time is vb1.
+Vφ (-Vb2), and the potential Vc at the connection point c is Vb
2- (Vth+ΔV b2) (-V c2)
.

Then, when the clock signal φ rises next, the potential Va at the connection point a becomes Vat, and the potential vb at the connection point S becomes Vbl.
Returning to , the potential VC at the connection point C at this time becomes VC2+vφ (-Vc3).

In this way, the clock signal φ and the inverted clock signal T
Due to the clock operation by the connection point a.

b, c (D potentials va, vb, Vc are clock signals φ-
When the voltage is 0 [V], V aO, V b2. Vc2
Therefore, when the clock signal φ-Vφ [V], Val
.

Vbl, Vc2+Vφ. Therefore, the first stage transistor set TS obtained by clock operation
The output potential of I, that is, the potential Vc at the connection point C becomes Vc2 when the clock signal φ-0 [v], that is, Vc2-VaO+2Vφ-2Vth-(ΔVat+ΔV b2).

Here, we newly added 'W41st stage transistor set TSI.
The human power potential at the time of φ-0 [V] is vl (-Van), the output potential is V2 (-Vc2), the change in threshold voltage due to the substrate bias effect ΔVal + ΔVb2 is ΔVBt, and the subsequent transistor set TS2 Assuming that the input potential is v2 and the output potential is v3, the N-th transistor set TS, (7) output potential V Ni1 is VN+1-VN +2Vφ-2Vth-AVB N-V
l+2N-Vφ ■...Equation (1) is obtained. Since this voltage VN+1 becomes the output voltage Vo of the booster circuit, it can be seen from this equation (1) that the input voltage Vt is boosted and output.

However, in a booster circuit with such a configuration,
As shown in the third term of equation (1) above, the decrease in boosted voltage due to the threshold voltage of the transistor (-(2N+1)
・V th).

Furthermore, as shown in the fourth term of equation (1), there is a decrease in the boosted voltage (-ΣΔ■BK) due to the substrate bias effect. The influence of this substrate bias effect path 1 is greatest in the latter stages of the transistor sets TSI to TSN, so that the reduction in boosting efficiency in the latter stages becomes significant.

Decrease in boost voltage due to transistor threshold voltage (-
(2N+1) · To solve the problem of V thl, there is a method of making all the transistors Ql-Qn intrinsic type transistors. In this way, the threshold voltage of the transistor becomes Vth - 0 [V], which makes it possible to increase the boost efficiency. However, if the threshold voltage of the transistor near the first stage becomes vth<o due to manufacturing variations, Otherwise, the booster circuit will not operate properly. Another method is to boost the voltage of the clock signal φ to compensate for the drop in boost efficiency, but in this case, a new circuit is required to boost the clock signal φ, which increases the circuit area. .

[Objective of the invention] (Problems to be solved by the invention) This invention was made in view of the above-mentioned points. Conventional booster circuits have low boosting efficiency, so it takes a lot of energy to obtain a predetermined output voltage. We have improved the reliability of the operation by configuring the booster circuit with intrinsic transistors to increase the boost efficiency. The purpose is to provide circuits.

(Means and effects for solving the problem) The booster circuit according to the present invention includes a plurality of series-connected transistors, each of which is diode-connected, and is connected to an even-numbered port when viewed from the input side. A clock signal is supplied to the gate of each transistor through a capacitor.
] In a booster circuit in which an inverted clock signal is supplied to the gate of each transistor via a capacitor,
A plurality of transistors from the input side are configured as enhancement type transistors, and transistors in subsequent stages are configured as intrinsic type transistors or depletion type transistors.

In a booster circuit with the above configuration, the transistor on the output side, which is significantly affected by the body bias effect, is of the intrinsic type or depletion type. It becomes possible to relax the situation. Furthermore, since the plurality of transistors from the input side are of the enhancement type, the booster circuit can operate normally even if the threshold voltage varies due to manufacturing variations.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure shows a booster circuit according to an embodiment of the present invention.
The circuit configuration of this booster circuit is almost the same as the conventional circuit shown in Figure 4, but in this booster circuit, the front stage of the transistor array is an enhancement type transistor, and the middle stage is an intrinsic type transistor. , the latter part is composed of depletion type transistors.

In other words, the front stage of this circuit is an enhancement type N
Channel MOS transistors T'l to TL, the middle stage is composed of intrinsic type N-channel MOS transistors T L''l -T l s, and the rear stage is composed of depletion type N-channel MOS transistors Tll1il-Tn. Transistor T1~
Each Tn is diode-connected, that is, its drain and gate are interconnected.

Even-numbered transistors T2°T4. as viewed from the input end.・
..., the gate of Tn-1 has a capacitor C2゜C4,
..., Cn-1, and the odd-numbered transistors T3 . T5. , Tn are supplied with an inverted clock signal 7 via capacitors C3, C5, . . . , Cn, respectively.

The input voltage v1 is supplied to the drain and gate of the first transistor T1, and the output voltage Vo is taken out from the source of the transistor Tn.

FIG. 2 shows enhancement type N-channel MOS transistors T1 to T with respect to increase in substrate bias voltage VB.
It shows the state of change in each threshold voltage of the L, intrinsic type N-channel MO3) transistor TL+l-Tm, and the depletion type N-channel MOS transistor Tm+1-Tn. Enhancement type & channel MO3) If the threshold voltage of transistors T1 to TL is vth, and the change in threshold voltage due to the substrate bias effect is Δvth, the actual threshold voltage is vt.
h+Δvth. Here, Δvth is Δvth-
There is a relationship γ (W), where γ is a constant and vB is the substrate bias voltage.

The solid line in the figure shows the change in threshold voltage when an enhancement type transistor is used in the front stage, an intrinsic type transistor is used in the middle stage, and a depletion type transistor is used in the rear stage as shown in FIG. In this way, if an enhancement type transistor is used in the first stage, an intrinsic type transistor is used in the middle stage, and a depletion type transistor is used in the second stage, the increase in threshold voltage is alleviated compared to the conventional case where only the enhancement type is used. It is possible to reduce the drop in boosted voltage as described above due to the threshold voltage.

FIG. 3 shows the relationship between the number of stages N of the transistor set TS and the output voltage Vo. In the case of a booster circuit in which a transistor array is configured only with an enhancement type, when it is assumed that there is no substrate bias effect, the output voltage vO is Vo −Vi +2N (vφ−V th
), so the output voltage ■0 and the transistor set TS
The relationship with the number of stages N is a straight line with a slope of 1/2 (Vφ-V th) as shown as Ll.

However, in reality, the threshold voltage of the transistor changes due to the substrate bias effect, so the relationship between the output voltage VO and the number of stages N of the transistor set TS becomes a curve like L2. Therefore, many transistor sets are required to obtain the desired output voltage VO.

As in this embodiment, when a booster circuit is configured using an enhancement type transistor in the front stage, an intrinsic type transistor in the middle stage, and a depletion type transistor in the rear stage, the relationship between the output voltage VO and the number of stages N of the transistor set TS is L3.
A curve like this is obtained, the boosting efficiency is improved, and it becomes possible to obtain a desired output voltage value with a small number of stages N.

In addition, instead of dividing the transistor strings that make up the booster circuit into three groups as in this embodiment, the booster circuit is divided into two groups, one on the input side and one on the output side, and the transistors on the input side are of the enhancement type, and the transistors on the output side are of the enhancement type. It is also possible to configure the transistor as an intrinsic type. In this case,
The relationship between the output voltage vO and the number of stages N of the transistor set TS is as shown by a curve L4. Although the boosting efficiency of the booster circuit having such a configuration is slightly lower than that of the embodiment described above, it is possible to obtain a boosting efficiency higher than that of the conventional circuit shown by curve L2, and furthermore, the manufacturing process is similar to that of the embodiment described above. It will be easier than the example. It is also possible to configure the input side transistor to be an enhancement type and the output side transistor to be a depletion type.

Although this embodiment has been described only when an N-channel MOS transistor is used, the same effect can be obtained by using a P-channel MOS transistor instead of an N-channel MOS transistor. However, in this case, the circuit becomes a booster circuit that boosts the input voltage v1 in the negative direction.

Further, in this embodiment, the transistor array is divided into three groups in units of transistor sets, but it is not necessary to do this, and the transistor array may be divided at any connection point of the transistors connected in series. Furthermore, boosting efficiency can be further improved by setting the threshold voltage of each transistor in each set of enhancement-type transistors, intrinsic-type transistors, and depletion-type transistors to a value that takes into account the substrate bias effect. It becomes possible.

[Effects of the Invention] As described above, according to the present invention, a booster circuit with high boosting efficiency can be obtained, and the number of transistors required to obtain a predetermined output voltage value can be reduced.

Wear. Therefore, the booster circuit can be formed with a small chip area, making it suitable for formation inside an LSI circuit. Further, by using an enhancement type transistor on the input side of the booster circuit, malfunctions due to manufacturing variations are not caused.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram illustrating a booster circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing how the threshold voltage of a transistor provided in the booster circuit changes with respect to an increase in substrate bias voltage. FIG. 3 is a diagram for explaining the boosting efficiency of the booster circuit, FIG. 4 is a circuit diagram for explaining the conventional booster circuit, and FIG. 5 is a timing chart for explaining the operation of the conventional booster circuit. . T1~TL...Enhancement type N-channel MO
S transistor, T L"l -T ta...intrinsic type N-channel MOS) transistor, Tm+
1~Tn...depression type N channel MO3)
transistor, 02 to Cn... capacitor, φ... clock signal, φ... inverted clock signal.

Claims (3)

[Claims] (1) A plurality of transistors are connected in series, each of which is diode-connected, and a clock signal is supplied via a capacitor to the gate of each even-numbered transistor connected from the input side. In a booster circuit, an inverted clock signal is supplied via a capacitor to the gates of odd-numbered transistors other than the first transistor when viewed from the input side. A booster circuit characterized in that the transistors in the subsequent stage are either intrinsic type transistors or depletion type transistors. (2) A plurality of transistors are connected in series, each of which is diode-connected, and a clock signal is supplied via a capacitor to the gate of each even-numbered transistor connected from the input side. In a booster circuit in which an inverted clock signal is supplied via a capacitor to the gates of odd-numbered transistors other than the first transistor when viewed from above, the transistors in the stage subsequent to the enhancement-type transistor are a plurality of intrinsic-type transistors. ,
2. The booster circuit according to claim 1, comprising a depletion type transistor at a subsequent stage. (3) The booster circuit according to claim 1, wherein all transistors subsequent to the enhancement type transistor are intrinsic type transistors.