JPS63136713A - Delay circuit - Google Patents

Abstract

PURPOSE:To set optionally a delay time by constituting each logic element by a logic element whose leading and trailing characteristics differ and having plural input terminals, supplying an input signal or an output signal from a logic element of the pre-stage to one of input terminals of each logic element and connecting the other input terminals to a variable voltage supply source. CONSTITUTION:Plural two-input logic elements 1-n (n is an integral number) are connected in series by the n-stage and consist each of field effect TRs (120-129) and junction diodes (151-154). In inputting an input signal 200 to an input terminal 101, an output changing its waveform in a way of prolonging its leading time and shortening its trailing time is generated from the output of the two-input logic element 1 of a 1st stage. This is because the delay time is varied in the increasing direction by a time 221 corresponding to the threshold voltage difference by using a variable power supply to change the threshold voltage 280 at the trailing of the output signal 202. Thus, in setting the trailing time shorter and the leading time longer, the delay time is varied continuously by varying the threshold voltage.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a delay circuit, and particularly to a delay circuit that can generate variable delay time under ultra-high-speed operation in communication equipment, electronic computers, measuring instruments, etc. It is.

<Prior Art> Conventionally, this type of delay circuit has a configuration in which a plurality of multiple input logic elements 501 to 505 are connected in series, as shown in the circuit diagram of FIG. It is composed of transistors 520-535 and junction diodes 551-558.

The operation of the delay circuit shown in FIG. 5 is shown in the timing chart of FIG. 6. When an input signal 601 is supplied to the input terminal 501, the input signal 601 is inverted by the first stage multiple input logic element 502, and the input signal 601 is inverted by the first stage multiple input logic element 502.
The delay time 620 due to 2 is the difference between the input signal 601 and the output 602 of the first stage multiple input logic element. Therefore, this delay circuit consists of circuits 503 to 505 similar to the first stage logic element 502.
Since the configuration has a total of 4 stages connected in series, the output terminal 51
The output signal 610 from 0 was delayed from the input signal 601 by a time equal to approximately 4 times the propagation delay time 620 of the multi-input logic element 502, 621.

<Problems to be solved by the invention> Since the conventional delay circuit described above generates delay time by connecting n (n is an integer) stages of multi-input logic elements in series, the delay time is determined by the hardware. The delay time cannot be changed externally after the delay circuit is completed, and the delay time generated by the delay circuit is only an integer multiple of the transmission delay time of the multiple input logic element was there.

Generally, when designing digital integrated circuits, the relative speed of signals is an issue, and if a reference clock is not used, it is necessary to provide a delay circuit on one of the signal lines to send the signal.

At this time, it is necessary to set the delay time by taking into consideration not only the element delay time of each of the multiple input logic elements mentioned above, but also the delay time due to wiring, stray capacitance, etc., but as the operating frequency of the digital integrated circuit becomes higher, , the allowable error range for setting the delay time becomes narrower, making it extremely difficult to set the delay time using the conventional delay circuit described above, and in some cases, the relative speed relationship may be reversed due to manufacturing errors, etc. There were times when I ended up

Therefore, in view of the problems of the prior art described above, it is an object of the present invention to provide a delay circuit in which the delay time can be arbitrarily set.

<Means for Solving the Problems> The present invention provides a delay circuit having a plurality of logic elements connected in series, in which each of the logic elements is configured with a logic element having a plurality of input terminals with different rising and falling characteristics. However, one of the input terminals of each logic element is supplied with an input signal or an output signal from a previous logic element, and the other input terminals are connected to a variable voltage supply source.

Functions and Effects> When the delay circuit according to the above configuration changes the voltage supplied from the variable voltage supply source, the rise characteristics and fall characteristics of each logic element shift, respectively. However, since the rise and fall characteristics of each logic element are different from each other, a difference occurs in the respective shift amounts, and the delay time can be continuously changed based on this difference. Therefore, in the present invention, the delay time can be adjusted even after the delay circuit is completed, and the delay time can be changed continuously.

As a result, even when the delay circuit according to the present invention is used at high frequencies, inconveniences such as reversal of relative speed can be avoided, and the range of application can be expanded.

<Example> Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is an electrical circuit diagram showing the principle of an embodiment of the present invention. This circuit diagram shows a plurality of two-manpower logic elements 1 to n
(n is an integer) stages are connected in series, and are composed of junction field effect transistors 120 to 129 and junction diodes 151 to 154. To explain the internal structure of the two-person logic element 1 using the first-stage two-person logic element 1 as an example, this two-person logic element 1 has a front-stage section 3 (junction type field effect) that inverts the signal and changes the threshold voltage of the logic element. (composed of transistors 120, 121, 122) and a rear stage section 4 (junction field effect transistors 123, 124 and junction diode 151) that adjusts the input level to the next stage logic element.
, 152). In configuring the front stage section 3, the ratio of the transfer conductance parameters β of the junction field effect transistor 120 and the junction field effect transistors 121 and 122 is set so that the rise time of the output signal is shorter than its fall time.

Next, the gate input of the junction field effect transistor 122, which is one input of the two-way logic element 1, is connected to the power supply 191 for changing the threshold voltage. This variable power supply 19 for changing the threshold voltage
By making the voltage of 1 higher than the low level of the input signal, the threshold voltage of the two-manual logic element can be lowered.

The operation of this circuit will be explained using the timing chart shown in FIG. When an input signal 200 is input to the input terminal 101, the output of the first-stage second-stage logic element 1 generates an output whose waveform changes so that the fall time is longer and the rise time is shorter, as shown in the timing chart. . This occurs when the output signal 202 falls and the threshold voltage of the next stage is the reference threshold voltage 270 (shown as a broken line in FIG. 2).
Therefore, by changing the threshold voltage 280 by the variable power supply (indicated by the solid line in FIG. 2), the delay time is increased by the time 221 corresponding to the threshold voltage difference. However, the rise time works to reduce the delay time by the time 222 due to the difference in threshold voltage. Therefore, if the rise time and fall time are made the same, even if the threshold voltage is changed as described above, the delay time will be the same for each even number of stages, but as in this embodiment, the fall time is short and the rise time is If it is set long, the delay time can be changed continuously by changing the threshold voltage. The output signal 210 appearing at the output terminal 110 is an output signal when n stages are an odd number of stages.

Variable delay time 23 of output signal 210 by variable power supply
1,232 is generated based on the fall time 221 of each stage 1 to n due to the difference in threshold voltage and the rise time 222 of each stage 1 to n due to the difference in threshold voltage, and is variable delay time 231, The difference in 232 is input terminal 1.
This is due to the difference in threshold voltage of the input signal 200 supplied to the input signal 200.

Next, FIG. 3 shows a detailed electrical circuit diagram of one embodiment of the present invention. This circuit diagram is a circuit when the circuit diagram of FIG.
and junction diodes 351 to 358. FIG. 4 shows a timing chart of the circuit diagram of FIG. 3. In this timing chart, the signal when the reference threshold voltage is 470 is represented by a broken line, and the signal when the threshold voltage is 480, which is changed by the variable power supply, is represented by a solid line. The variable delay time 430 can be increased in accordance with the number of stages. Further, the delay circuit in the conventional example has the advantage of being able to gain delay time by incorporating multiple stages of logic elements, but in this embodiment as well, the pulse width is almost the same as that of the input signal 400 at the input terminal 301 for each even-numbered stage. No reduction in pulse width or attenuation of amplitude is observed due to the multistage incorporation of two human-powered logic elements.

As explained above, one embodiment of the present invention is constructed of a junction field effect transistor and a junction diode that have a fast response speed in an ultra-high frequency band, and utilizes the transmission delay time of a logic element.

By applying a variable voltage to the input terminal of the logic element to change the threshold voltage of the logic element, there is an advantage that the delay time can be changed linearly.

Furthermore, by incorporating this delay circuit into the system and changing the delay time from the outside, it is possible to easily match the timing between signals, and furthermore, the operating margin with respect to frequency is increased.

[Brief explanation of the drawing]

Fig. 1 is an electric circuit diagram showing the principle of an embodiment of the present invention, Fig. 2 is a timing chart diagram of the delay circuit shown in Fig. 1, and Fig. 3 is a detailed circuit diagram of an embodiment of the invention. Electrical circuit diagram, Fig. 4 is a timing chart diagram of the delay circuit shown in Fig. 3, Fig. 5 is an electrical circuit diagram of a conventional delay circuit, and Fig. 6 is a timing chart diagram of the delay circuit shown in Fig. 5. . 1-n...2 human logic element, 101.501
...Input terminal, 110.510...Output terminal, 120-129, 320-339...Junction type field effect transistor, 151-154.351-358...Junction type diode, 191.391...・Variable power supply for changing threshold voltage, 192-194, 392-394, 592-594...
...Power supply connection terminal, 200...Input signal of input terminal 101, 202.402...Output of 1st stage 2 human logic element, 403...2 Output of the second stage human-powered logic element, 210...Output signal of the output terminal 110, 270.470...Reference threshold voltage, 280.480...Threshold voltage changed by variable power supply, 400. ...Input signal of input terminal 301, 404...Output of third stage second human logic element, 410...Output signal of output terminal 310, 221... ...Fall time due to difference in threshold voltage, 222...Rise time due to difference in threshold voltage, 231.232.430...Variable surface power delay time due to variable power supply.

Claims (2)

[Claims] (1) In a delay circuit having a plurality of logic elements connected in series, each of the logic elements is configured with a logic element having a plurality of input terminals with different rising and falling characteristics,
1. A delay circuit characterized in that one input terminal of each logic element is supplied with an input signal or an output signal from a preceding logic element, and the other input terminals are connected to a variable voltage supply source. (2) The delay circuit according to claim 1, wherein each of the logic elements includes a junction field effect transistor and a junction diode.