JPH0332137A - Signal transmitter - Google Patents

Abstract

PURPOSE:To avoid a change in the duty ratio and the effect of a load connecting to the post-stage of the circuit without increase in power consumption and the necessity of a high speed device by transmitting signal corresponding to the duty ratio of the transmission signal in the level edge of the output of a flip-flop circuit. CONSTITUTION:A digital circuit 1 generates signals Q1, and Q1 in response to the level edge of an input signal and they are sent to a reception side via a signal transmission circuit 3, a flip-flop circuit 2 is set by the signal Q1 and reset by signal Q1 and a signal Q2 is outputted. In this case, the signal Q2 rises in coincident with the rising timing of the signal Q1 and falls in coincidence with the rising timing of the signal Q1. Thus, the transmission of the signal Q2 having the same duty rate as that of the input signal being the transmission signal is attained. Thus, the increase in the circuit power consumption and the high speed device are not required and the effect of the load connecting to the post-stage of the circuit is not given on the duty ratio in the digital signal transmission.

Description

[Detailed Description of the Invention] [Summary] Regarding a signal transmission device in a digital circuit, it is possible to receive and receive signals between digital circuits to a subsequent stage without increasing circuit power consumption or requiring high-speed devices. The purpose of the present invention is to provide a digital signal transmission device in which the duty ratio does not change due to the influence of the load connected to the transmitter. Transmission signal generation means generates inverted and non-inverted signals whose levels change in response to level edges of the signal, and the output of the transmission signal generation means is transmitted to a receiving circuit via a signal transmission path, and a flimp-flop circuit provided at the input stage and set by one of the inverted and non-inverted signals and reset by the other, the level edge of the output of the flimp-flop circuit being made to correspond to the duty of the transmitted signal. Configure to transmit signals.

[Industrial application field]

The present invention relates to a signal transmission device, and more particularly, to a signal transmission device in a digital circuit intended to stabilize the duty ratio.

In digital circuits, various calculations are performed using binary logic signals, so the duty of the pulse is extremely important, and timing is often taken in synchronization with the pulse edge or by the duty time.

As digital circuits have become faster in recent years, the pulse width of digital signals has become narrower and narrower.

Therefore, a circuit is required in which the duty of each signal does not shift so that the shift of the duty of each signal does not interfere with the stable operation of the circuit. In response to the demand for higher speeds, the speed is usually increased by using faster devices or increasing the power consumption of the circuit.

[Conventional technology]

Conventionally, in order to receive and pass signals to the subsequent stage between two digital circuits, a buffer circuit or the like is used to control the rise and fall times of the signal depending on the amount of load connected to the subsequent stage of the circuit. This maintains the duty of the transmission signal.

[Problem to be solved by the invention]

However, in such conventional signal transmission devices, when receiving and passing signals such as clock signals and PWM signals that are affected by changes in the signal duty ratio, it is difficult to receive and pass signals such as clock signals and PWM signals, which are affected by the load connected to the subsequent stage of the circuit. This configuration requires a special buffer circuit with equal rise and fall times so that the duty ratio does not change, but since it is usually difficult to implement such a circuit, A method generally used is to reduce the time difference by reducing both the fall time and the duty so short that they do not affect the duty. However, this method has problems such as increased power consumption and the need for expensive high-speed devices to increase the speed of the circuit.

Therefore, the present invention provides a method for receiving and passing signals between digital circuits to the subsequent stage, without increasing circuit power consumption or requiring high-speed devices, and changing the duty ratio due to the influence of the load connected to the subsequent stage of the circuit. The purpose of the present invention is to provide a digital signal transmission device that will never cause problems.

[Means to solve the problem]

In order to achieve the above object, a signal transmission device according to the present invention is provided at the output stage of a transmission side circuit that generates a transmission signal having a constant duty, and has an inverting and a non-inverting signal whose level changes in response to the level edge of the transmission signal. A transmission signal generation means for generating a signal, and an output of the transmission signal generation means is transmitted to a receiving side circuit via a signal transmission path, and is provided at an input stage of the receiving side circuit to generate one of the inverted and non-inverted signals. The signal is transmitted by making the level edge of the output of the Frisopfloop circuit correspond to the duty of the transmission signal.

[Effect]

In the present invention, the transmission signal generating means generates inverted and non-inverted signals in response to the level edge of the transmitted signal having a constant duty, and these are transmitted to the receiving side circuit via the signal transmission path, and the Fritsop-flop circuit It is set by one of the inverted and non-inverted signals and reset by the other, so that the level edge of its output corresponds to the duty of the transmitted signal.

Therefore, even if the duty ratio of the inverted and non-inverted signals changes due to the difference in the rise and fall delay times of the transmission signal generating means, it will be restored to its original state by the Friso Bufronob circuit.
It is possible to transmit a signal having the same duty as the transmission signal.

[Explanation of principle]

FIG. 1 is a circuit diagram for explaining the present invention in detail.

In the figure, l is the inverted and non-inverted output Ql.

A digital circuit with Q (corresponding to transmission signal generation means)
A signal Q4. is arranged at the output stage of a transmitting circuit that generates an input signal (transmission signal) having a constant duty, and whose level changes in response to the level edge of the input signal.
2 is a flip-flop circuit that is placed in the human power stage of the receiving side circuit, has a cent input and a reset power, and outputs an output Q2, and the flip-flop circuit 2
is sent by the signal Qt transmitted through the signal transmission circuit 3 and reset by the signal Ql to generate the output Q2.

As shown in the timing chart in Fig. 2, when an input signal with a constant duty is input to the digital circuit 1, the signals Q, , Q
, is generated and transmitted to the receiving side via the signal transmission circuit 3, and the flip-flop circuit 2 is sent by the signal Ql, reset by the signal Ql, and outputs the signal Q2.

In this case, the signal Q2 rises in coincidence with the rising timing of the signal Ql, and falls in coincidence with the rising timing of the signal Ql. Therefore, if the signal Q and
Even if the duty ratio of ,Q, changes, in the flip-flop circuit 2, the duty is determined only at the rising timing of each signal, so it will eventually return to the original state.
It becomes possible to transmit the signal Q2 having the same duty as the input signal which is the transmission signal. As a result, in contrast to passing signals to subsequent stages in digital logic circuits, it is possible to change the duty ratio due to the influence of the load connected to the subsequent stage of the circuit, without increasing circuit power consumption or requiring high-speed devices. It is possible to perform digital signal transmission without any interference.

〔Example〕

A first embodiment of the present invention based on the above principle will be described below. FIG. 3 is a block diagram of the first embodiment. In this figure, 11 is a transmitting side circuit, 12 is a receiving side circuit, and 13 is a signal transmission path. The transmitting side circuit 11 performs various logical operations (the portions shown in the diagram) to generate a transmitting signal having a certain duty (for example, generates a predetermined clock signal), and has a digital circuit 1 and an output circuit at its output stage. It has a cover sofa 14.15 and transmits the signal to the digital circuit diagram l.
The receiver is input as an input signal to generate non-inverted and inverted signals, and these are sent to the signal X via the signal transmission path 13, respectively.
, , Y, to the receiving circuit 12. The digital circuit 1 and the output sofa 14,15 constitute a transmission signal generating means 16. Note that the output buffer 14.
15 have the same characteristics, for example, as shown in FIG.
A sota follower circuit is used.

The signal transmission line 13 is constituted by a bare line, and the influence of the load on the output buffers 14 and 15 is made to be as much as possible on the inverting and non-inverting sides. Furthermore, each line of the signal transmission path 13 has stray capacitances C,,C,. On the other hand, the receiving side circuit 12 receives signals X, , Y generated based on a transmission signal having a constant duty.

The transmission signal receiving means 17 has at its input stage a transmission signal receiving means 17 which generates a signal Q of a constant duty again in response to the flip-flop circuit 2 and the input sofa 1
8.19. The input buffers 18 and 19 have predetermined threshold levels, invert the levels of the signals X+ and '/+, and output them to the flip-flop circuit 2.
The function of the flip-flop circuit 2 is similar to that described in FIG. 1, but its output is Q. Receiving side circuit 12
performs various logical operations based on the output Q having a constant duty.

In the above configuration, as shown in timing diagram 4 in FIG. 5, when an input signal with a constant duty is input to the digital circuit circuit l, non-inverted and inverted signals are generated in response to the level output. are generated and sent to the receiving side circuit 12 via the signal transmission path 13 as signals X, , Y, respectively via output buffers 14 and 15. In this case, a grounded emitter circuit is used for the output buffers 14 and 15, but this circuit usually has a characteristic of fast rising response but slow falling response. This is shown as delay times A and B (especially rise time) in the figure. On the other hand, in the receiving side circuit 12, the input cover sofa 18
．． 19 generates inverted signals Xz and Yz for the signals x, Y2, respectively, and inputs them to the Frisopfloop circuit 2. Finally, an output signal Q is generated and sent to the transmitter circuit 11.
The signal is transmitted between the receiving circuit 12 and the receiving circuit 12.

At this time, the rise response characteristics of the output cover sofas 14 and 15 are the same, and the duty of the output signal Q is determined by this rise response.
As in the case of the explanation of the principle of the invention described above, it is possible to transmit the signal Q having the same duty as the input signal. Also,
Even if the temperature or power supply voltage changes, the circuit characteristics of the inverting and non-inverting output buffers 14 and 15 change in the same way, so the duty ratio of the signal Q does not change. the result,
In contrast to passing signals to subsequent stages in digital logic circuits, digital logic circuits do not increase circuit power consumption or require high-speed devices, and the duty ratio does not change due to the influence of loads connected to subsequent stages of the circuit. Signal transmission can be performed.

Next, FIGS. 6 to 8 are diagrams showing a second embodiment of the present invention, and the same components as those in the first embodiment are given the same numbers and redundant explanation will be omitted. In the configuration diagram shown in FIG. 6, the output stage of the transmitting side circuit 21 is provided with an inverter type output buffer 22.23 in addition to the digital circuit diagram l, and the digital circuit diagram l and the output buffer sofa 22.23 are provided. 23 constitutes a transmission signal generating means 24. Output buffer 22.2
Embodiment 3 differs from the first embodiment in that it outputs an inverted signal; for example, as shown in FIG. 7, a common emitter circuit consisting of a transistor Q2 and a resistor R2 is used. The rest is the same as the first embodiment.

Therefore, in this embodiment, as shown in the timing chart of FIG. 8, since the falling times of the signals X, Y, are the same, the duty of the output signal Q of the Frisopflosop circuit 2 is determined by this falling response. Therefore, the same effects as in the first embodiment can be obtained.

In addition, in the above embodiment, an output cover sofa and an input cover sofa circuit were used, but these serve a supplementary role to a digital circuit having inverted and non-inverted outputs and a flip-flop circuit, so they do not need to be used. Often, there may be multiple stages.

Furthermore, the effect is the same whether the inverting or non-inverting output is connected to either the set or reset terminal of the Frisop flop circuit. It is also effective to transmit signals randomly, rather than repeatedly.

Furthermore, the present invention can be widely applied to signal transmission between circuits inside an IC and between devices.

〔Effect of the invention〕

According to the present invention, the reception and reception of signals to subsequent stages in digital circuit time eliminates the influence of loads connected to subsequent stages of the circuit, without increasing circuit power consumption or requiring high-speed devices. It is possible to transmit digital signals with a stable duty ratio.

[Brief explanation of drawings]

Figures 1.2 are diagrams explaining the present invention in detail, Figure 1 is its circuit diagram, Figure 2 is a timing chart explaining its operation, and Figures 3 to 5 are signal transmission devices according to the present invention. FIG. 3 is a configuration diagram thereof, FIG. 4 is a circuit diagram of the output sofa, FIG. 5 is a timing chart explaining its operation, and FIGS. 6 to 8 are diagrams of the present invention. FIG. 6 is a configuration diagram thereof, FIG. 7 is a circuit diagram of the output sofa, and FIG. 8 is a timing chart illustrating its operation. 1...Digital circuit (transmission signal generation means) 2
・・・・・・Flifubufuron 7' times iW, 3.13・
...Signal transmission circuit, 11.21...Sending side circuit, 12...Receiving side circuit, I4.15.22.23...Output cover sofa, 1
6.24... Transmission signal generating means, 17...
... Transmission signal receiving means, 18.19 ... Inner cover sofa. Beni! ? Figure 4 Circuit diagram of the output buffer sofa of the first embodiment Figure 4 Diagram of the output buffer of the second embodiment Output 1 circuit diagram

Claims (1)

[Claims] A transmission signal that is provided at the output stage of a transmission side circuit that generates a transmission signal with a constant duty, and that generates inverted and non-inverted signals whose levels change in response to level edges of the transmission signal. a generating means; an output of the transmission signal generating means is transmitted to a receiving circuit via a signal transmission path, the circuit is provided at an input stage of the receiving circuit, and is set by one of the inverted and non-inverted signals; 1. A signal transmission device comprising: a flip-flop circuit that is reset by the other flip-flop circuit, and transmits a signal by making a level edge of an output of the flip-flop circuit correspond to a duty of the transmission signal.