JP2831788B2 - Flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] With respect to a flip-flop circuit, it is an object of the present invention to provide a flip-flop circuit which can operate in a high frequency range and can improve the degree of integration by preventing an increase in the number of circuit elements. A clock signal is supplied from the outside, a pulse generating circuit that generates a signal with a minimum pulse width that activates the latch circuit, and a signal with a minimum pulse width that is generated by the pulse generating circuit are supplied and synchronized with the signal. A latch circuit for latching an input signal, wherein the pulse generation circuit includes a multiplexer or an exclusive NOR gate, and the multiplexer or the exclusive NOR gate has substantially the same circuit configuration as the latch circuit. And

[Industrial applications]

The present invention relates to a flip-flop circuit.
The present invention relates to a flip-flop circuit which performs high-frequency operation and has a reduced number of circuit elements.

In recent years, with the demand for higher speed and higher frequency of the system and an increase in gate size, a semiconductor circuit that operates at higher speed and at higher frequency with a minimum number of circuits has been required.

In digital systems, AND, OR, NOT, NAND, NOR
In addition to the basic gate IC described above, another important basic circuit is a flip-flop circuit. This is a circuit that alternately switches between two stable states with one pulse, and is often abbreviated as FF or FF in general.

[Conventional technology]

As a conventional flip-flop circuit, for example, there is one as shown in FIG. FIG. 1 shows a master-slave type flip-flop circuit, which includes a master unit 1 and a slave unit 2. The data signals D (D0 to D3...) Shown in FIG. 10 (a) input to the terminal I1 are supplied to the data input terminal D of the master unit 1 and the terminal I2
10 (b) is supplied to the clock input terminal C of the master unit 1 and the clock inversion input terminal of the slave unit 2, respectively. When the clock signal falls to the "L" level, the master unit 1 captures the data signal, and outputs from the terminal Q the data signal as shown in FIG. 10 (c) captured after the time tpd1 from the fall. On the other hand, an inverted signal of the terminal Q is output from the terminal. The time tpd1 is a propagation delay time of the master unit 1. Thereafter, when the clock signal rises to the “H” level, the master unit 1 holds the signal output to the terminal Q, and keeps the signal at the terminal Q while the clock is at the “H” level even if the input signal changes. The level does not change.

On the other hand, when the clock signal rises, the slave unit 2
A signal as shown in FIG. 10 (d), which is obtained by taking in the output signal of the terminal Q and taking it after the propagation delay time tpd2 of the slave unit 2 from the rising of the clock signal, is output from the terminal X. Outputs an inverted signal. Thereafter, when the clock signal falls to the “L” level, the slave unit 2 holds the signal output to the terminal X, and the clock remains at the “L” level even when the input signal Q of the slave unit 2 changes. During this period, the level of the terminal X does not change.

FIG. 11 is a block diagram of the latch circuit 3, and FIG. 14 is a signal time chart when the latch circuit 3 is used as a flip-flop circuit.

The data signal shown in FIG. 14A input to the terminal I3 is supplied to the data input terminal D of the latch circuit 3, and
The clock signal shown in FIG. 14B input to I4 is supplied to the clock input terminal C of the latch circuit 3. When the clock signal rises to the "H" level, the latch circuit 3 captures the data signal and outputs it from the terminal X as shown in FIG. On the other hand, the inverted output of the signal of the terminal X is output from the terminal. The time tpd3 is a propagation delay time of the latch circuit 3. Thereafter, when the clock signal falls to the “L” level, the latch circuit 3 holds the signal output to the terminal X, and even if the input signal changes, while the clock is at the “L” level, the terminal X, Level does not change.

[Problems to be solved by the invention]

However, in such a conventional flip-flop circuit, in the case of the latter latch circuit 3 described above, the circuit configuration is simple, but on the other hand, the following conditions are required. There is a problem that it is difficult to use it as a circuit.

That is, as shown in FIG. 13, when the data signal changes while the clock signal is at the "H" level, the changed data is output after the propagation delay time tpd3 ', and does not operate as a flip-flop circuit. In order to operate as a flip-flop circuit, the data signal is set (switched) as shown in FIG.
There is a big constraint that must be done between levels. At low frequencies, the clock "L" level period is sufficient and data can be set, but at higher frequencies, the clock "L" level period becomes shorter as the frequency increases. , It becomes very difficult to set data. For example, when the clock frequency is 100 MHz, the clock level period is about 5 ns
500ps at 1GHz, 100ps at 5GHz, 5ps at 10GHz
It becomes very short like 0ps. Therefore, it cannot be used as a flip-flop circuit at high frequencies.

On the other hand, in the case of the former technique described above, there is no constraint as described above, but on the other hand, there is another problem that the number of circuit elements increases as described below.

That is, as shown in FIG. 12, the data may be set at the "H" level or at the "L" level of the clock. This is because either the master unit 1 or the slave unit 2 always holds the output data. For this reason,
Data can be set twice as long as the latter,
Time to set data is about 10 at clock frequency 100MHz
ns, 1 ns at 1 GHz, 200 ps at 5 GHz, and 100 ps at 10 GHz. Therefore, although the problem of use in a high frequency range can be solved, two circuits of the master unit 1 and the slave unit 2 are always required in circuit, and the number of circuit elements in a semiconductor device having a large number of flip-flop circuits inside the LSI is increased. And the degree of integration is reduced. For example, as shown in FIG. 15, when a large number of flip-flop circuits operating in synchronization with one clock signal are provided inside the LSI, these flip-flop circuits need master units 1a to 1n and slave units 2a to 2n. Therefore, a large number of elements are required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a flip-flop circuit which can operate in a high frequency range and can improve the degree of integration by preventing an increase in the number of circuit elements.

[Means for solving the problem]

In order to achieve the above object, a flip-flop circuit according to the present invention is provided with a pulse generating circuit for generating a signal having a minimum pulse width to which a clock signal is supplied from outside and operating a latch circuit, and a minimum pulse generated by the pulse generating circuit. A signal having a width is supplied, and a latch circuit that latches an input signal in synchronization with the signal is provided.The pulse generation circuit includes a multiplexer or an exclusive NOR gate, and the multiplexer or the exclusive NOR gate is connected to the latch circuit. It is characterized by having substantially the same circuit configuration.

[Action]

In the present invention, as shown in FIG. 1, an external clock signal is input to the pulse generation circuit 201 from a terminal I6, and when the external clock signal rises from "L" level to "H" level in the pulse generation circuit 201. As shown in FIG. 2, after the propagation delay time tpd4 of the pulse generation circuit 201, the output waveform rises from the “L” level to the “H” level.
After d0, the signal falls from the “H” level to the “L” level, and a clock pulse having a pulse width of tpd0 is output to the latch circuit 200. Here, tpd4 is the time that passes through the pulse generation circuit 201, and tpd0 is the minimum pulse width time during which the latch circuit 200 can operate, that is, the time from when a clock signal is input to the latch circuit 200 until data is output. It is. The clock that has passed through the pulse generation circuit 201 has a pulse waveform as shown in FIG. 2C and is input as a clock of the latch circuit 200. When the pulse waveform as a clock rises, the latch circuit 200 outputs data D (D0 to D4...) From a terminal I5.
..) And outputs data after a time tpd0 when the data passes through the latch circuit 200. This pulse waveform has the time tpd0
After that, the output waveform of the latch circuit 200 is held. Thus, a flip-flop operation is performed.

Therefore, the setting (switching) of the data signal is sufficiently satisfied that the condition that the clock signal must be performed during the "L" level, the latch circuit 200 operates reliably, and the conventional master / slave flip-flop can be used. The operating frequency is increased by the same amount as that of the circuit, and operation in a high frequency range becomes possible. Further, even if the semiconductor device has a large number of flip-flop circuits inside the LSI without requiring two circuits of a master unit and a slave unit in terms of a circuit, the number of circuit elements can be prevented from increasing and the degree of integration can be improved.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. 3 to 8 are diagrams showing one embodiment of the flip-flop circuit according to the present invention. FIG. 3 is a block diagram when a flip-flop circuit is used inside the LSI. In this figure, 11a to 11n are latch circuits, and 12 is a pulse generation circuit. The latch circuits 11a to 11n are the same as those in the related art. Data is input to each data input terminal D, and a clock pulse is supplied from the pulse generation circuit 12 to a clock terminal. The pulse generation circuit 12 is provided with only one pulse signal, processes the external clock signal, generates a signal having a minimum clock pulse width for operating the latch circuits 11a to 11n, and generates the latch circuit 11a.
Output to clock terminals of ~ 11n.

Here, a specific circuit example of the pulse generation circuit 12 is shown in FIG. First, the first pulse generating circuit shown in FIG. 4A is composed of inverters 21 and 22, a buffer gate 23 and a NOR gate 24. An external clock is inputted from a terminal C and a clock pulse is outputted from a terminal X. . FIG. 5 is a timing chart of the pulse generating circuit. As shown in FIG. 5, the external clock input from the terminal C is inverted and output to the node 1 (indicated as N1 in the drawing) after the delay time tpd5 of the inverter 21. NOR gate 24 delay time tp
The output is inverted from the terminal X after d6. When the external clock input from the terminal C rises, the time tpd4 (= tpd5 + tpd
6) The level of the terminal X rises later, and the clock is transmitted to the node 2 (indicated as N2 in the drawing) after the time tpd1 from the node 1 by the time tpd1. A pulse is output. A circuit constant is set so that a delay time difference equal to the time tpd0 is provided between the nodes 1 and 2, and this corresponds to a time when the latch circuits 11a to 11n output data.
That is, the time tpd0 corresponds to the clock pulse having the minimum pulse width at which the latch circuits 11a to 11n operate. FIG. 4 (a)
The circuit equivalent to the above is shown in FIG. 2B, and this pulse generation circuit includes a buffer gate 31 and an AND gate 32 in addition to the inverter 22 and the buffer gate 23.

FIG. 4 (c) shows a second example of the pulse generation circuit, which is composed of an inverter 41, a NAND gate 42 and a NOR gate 43. An external clock is input from a terminal C, and a clock pulse is input from a terminal X. Is output. One input terminal of the NAND gate 42 is fixed at the “H” level, and the signal of the node 1 is input to the other input terminal. The propagation delay time of the NAND gate 42 is set to tpd0. Therefore, a clock pulse having a minimum pulse width for operating the latch circuits 11a to 11n is output in the same manner as in the pulse generation circuit of FIG. 4A. A circuit equivalent to FIG. 4 (c) is shown as in FIG. 4 (d), and this pulse generating circuit includes a buffer gate 51 and an AND gate 52 in addition to the NAND gate 42.

FIG. 4 (e) shows a third example of the pulse generating circuit. This pulse generating circuit comprises an inverter 61, a multiplexer 62 and a NOR gate 63. An external clock is inputted from a terminal C, and a clock pulse is outputted from a terminal X. Is output. The multiplexer 62 has data terminals D1 and D2 and a select terminal S. The data terminal D1 is fixed at "L" level, the data terminal D2 is fixed at "H" level, and the signal of the node 1 is input to the select terminal S. You. When S = “L”, the signal of the data terminal D1 (“L” level) is inverted and output from the terminal, and when S = “H”, the data terminal D2 (“H” level)
Is inverted from the terminal and output. The propagation delay time of the multiplexer 62 is set to tpd0. Therefore, as in the pulse generation circuit of FIG.
A clock pulse having a minimum pulse width for operating 11a to 11n is output. A circuit equivalent to FIG. 4 (e) is shown as in FIG. 4 (f).
In addition, a buffer gate 71 and an AND gate 72 are included.

FIG. 4 (g) shows a fourth example of the pulse generating circuit, which is composed of an inverter 81, an exclusive NOR gate 82 and a NOR gate 83, and a terminal C
Further, an external clock is input and a clock pulse is output from the terminal X. One input terminal of the exclusive NOR gate 82 is fixed at the “L” level, and the signal of the node 1 is input to the other input terminal. The propagation delay time of the exclusive NOR gate 82 is set to tpd0. Therefore, a clock pulse having a minimum pulse width for operating the latch circuits 11a to 11n is output in the same manner as in the pulse generation circuit of FIG. 4A. A circuit equivalent to FIG. 4 (g) is shown as in FIG. 4 (h), and this pulse generating circuit includes a buffer gate 91 and an AND gate 92 in addition to the exclusive NOR gate 82.

In the above circuit example, in particular, the multiplexer 62 and the exclusive NOR gate 82 can be configured by the same circuit configuration as the latch circuits 11a to 11n, and if this is formed by the ECL circuit, the signal propagation delay time becomes the same, so that There is an advantage that a desired delay time tpd0 can be obtained.

Next, the above-described latch circuits 11a to 11n,
An example will be described in which the exclusive NOR gate 62 and the exclusive NOR gate 82 are configured by an ECL circuit.

FIG. 6 shows an example of latch circuits 11a to 11n. The latch circuit includes transistors 101 to 110, a constant current source 111 and a resistor 1
It is composed of 12-117. The emitters of the transistors 103 and 104 are connected in common. The input data and the reference voltage Verf1 are supplied to the respective bases, and the logical outputs are taken out from the respective collectors and supplied to the bases of the emitter follower transistors 109 and 110. Similarly, the emitters of the transistors 105 and 106 are connected in common, and the bases of the transistors 105 and 106 are connected to the transistor 10 of the emitter follower.
9, 110 are connected to the emitter side, from which the output X is taken out. The clock pulse is supplied from the terminal C to the base of the transistor 101, and is received by the emitter follower to determine the base voltage of the transistor 107. At this time, the reference voltage Vref2 is supplied by the other transistor 108, and the base voltage of both transistors is used. When either of them is turned on, the operation of the ECL transistors 103 and 104 or 105 and 106 is controlled. Therefore, when the clock pulse is at “H” level, the transistor 107 is turned on and the ECL transistors 103 and 104 are turned on.
Becomes operable and accepts input data. When the input data is at “L” level, the transistor 108 is turned on and the ECL transistor 10 is turned on.
5, 106 become operable to hold the output data. For example, if the input data D is at “H” level, the transistor 103 is turned on and its collector output becomes “L”, the transistor 104 is turned off and its collector output becomes “H”, and the transistor 110 becomes “H”. To convey
The output terminal X goes to “H” level, and the transistor 109 transmits “L”, so that the output terminal goes to “L” level.
On the other hand, when the input data D is at the "L" level, the transistor 104 is turned on and the collector output thereof is at the "L" level, and the transistor 110 transmits "L".
Level. When the clock pulse is at the “L” level, the transistor 108 is turned on and the ECL transistors 105 and 1 are turned on.
06 becomes operable, and the output data being output to X at that time is held. For example, if the output data X is “H” level and “L” level, the transistor 10
6 turns on and its connector output goes to "L", transistor 105 turns off and its collector output goes to "H", and transistor 110 transmits "H", so the output terminal X remains at "H" level Nevertheless held, transistor 10
9 transmits "L", so that the output terminal is maintained without being kept at "L" level. The same holds when the “L” level is output to the output terminal X and the “H” level is output to the output terminal X.
As a result, the input data is latched and the flip-flop operates.

In this case, since the clock pulse is set to the minimum pulse width at which the latch circuits 11a to 11n operate, the data signal must be set (switched) while the clock signal is at the "L" level. The condition is sufficiently satisfied, the latch circuit operates reliably, and the operating frequency is increased by the same amount as that of the conventional master / slave flip-flop circuit, so that operation in a high frequency range becomes possible. In addition, even if the semiconductor device does not require two circuits, a master unit and a slave unit, and has many flip-flops inside the LSI, the number of circuit elements can be prevented from increasing and the degree of integration can be improved. The effect is obtained.

FIG. 7 shows an example of the multiplexer 62. The multiplexer 62 includes transistors 121 to 130, a constant current source 131, and resistors 132 to 137. Transistors 123, 124
Are connected to the emitter in common, and the signal of data terminal D2 (“H” level fixed) and the reference voltage Verf1
, And a logical output is taken out from each collector side and supplied to the bases of the transistors 129 and 130 of the emitter follower. Similarly, the emitters of the transistors 125 and 126 are also connected in common, and the signal of the data terminal D1 (“L” level fixed) and the reference voltage Vref1 are connected to the respective bases.
Is supplied, and the logical output is taken out from each collector side, and the transistors 129 and 1 of the emitter follower are also output.
Supplied to 30 bases. Then, an output X is taken out from the emitter followers of the transistors 130 and 129. The signal of the select terminal S is supplied to the base of the transistor 121, which is received by the emitter follower to determine the base voltage of the transistor 127. At this time, the reference voltage Vref2 is supplied to the other transistor 128,
Either of them is turned on by the base voltages of both, and the operation of the ECL transistors 123, 124 or 125, 126 is controlled. Therefore, when the select signal S is at "H" level, the transistor 127 is turned on, the ECL transistors 123 and 124 are enabled, and the signal of the data terminal D2 ("H" level) is output from the terminal X. The signal at terminal D2 is inverted and output. On the other hand, when the select signal S is at the "L" level, the transistor 128 is turned on, the ECL transistors 125 and 126 are enabled, and the signal at the data terminal D1 ("L" level) is output from the terminal X. Is inverted and output.

FIG. 8 shows an example of the exclusive NOR gate 82. The exclusive NOR gate 82 can also be used as an exclusive OR gate. Exclusive NOR gate 82 is transistors 141-150, constant current source
151 and resistors 152-157. The emitters of the transistors 143 and 144 are commonly connected, and a fixed signal (“L” level fixed) and a reference voltage Vref1
, And a logical output is taken out from each collector side and supplied to the bases of the transistors 149 and 150 of the emitter follower. Similarly, the emitters of the transistors 146 and 145 are also connected in common, and a fixed signal (“L” level is fixed) and a reference voltage Vref1 are supplied to the respective bases, and a logical output is taken out from each collector side. Of the transistors 150 and 149. However, the supply relationship depends on the transistor 14
The opposite is true for 3,144. Then, the output X from the emitter side of the transistors 149 and 150 of the emitter follower,
Is taken out. The signal B of the node 1 is a transistor 141
The base voltage of the transistor 147 is determined by receiving the base voltage of the transistor 147 at this time, and the reference voltage Vref2 is supplied to the other transistor 148 at this time. ECL
The operation of the transistors 143, 144 or 145, 146 is controlled. Therefore, when the signal B at the node 1 is at the “H” level, the transistor 147 is turned on, the ECL transistors 143 and 144 are enabled, and a signal having a fixed signal (“L” level fixed) level is output from the terminal. You. On the other hand, node 1
When the signal B is at the "L" level, the transistor 148 is turned on, the ECL transistors 145 and 146 are enabled, and the signal having the fixed signal ("L" level fixed) level is inverted and output from the terminal. You.

As described above, these circuits are latch circuits 11a to 11n.
It can be configured with the same circuit configuration as
If it is made of a circuit, the signal propagation delay time becomes the same, and a desired delay time tpd0 can be obtained accurately.

〔The invention's effect〕

According to the present invention, it is possible to reliably operate the latch circuit by sufficiently satisfying the condition that the data signal must be set while the clock signal is at the "L" level. The operating frequency can be increased by the same amount as that of the circuit to enable operation in a high frequency range. Also, the circuit does not require two circuits, a master unit and a slave unit,
Even in a semiconductor device that requires a large number of flip-flop circuits inside, the number of circuit elements can be prevented from increasing and the degree of integration can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining the principle of the present invention, FIG. 2 is a timing chart for explaining the principle of the present invention, and FIGS. 3 to 8 are diagrams showing one embodiment of a flip-flop circuit according to the present invention. FIG. 3 is a block diagram when the flip-flop circuit is used inside the LSI, FIG. 4 is a diagram showing a specific circuit example of the pulse generation circuit, and FIG. 5 is a timing chart of the circuit shown in FIG. Chart, FIG. 6 is a specific circuit diagram of the latch circuit, FIG. 7 is a specific circuit diagram of the multiplexer, FIG. 8 is a specific circuit diagram of the exclusive NOR gate, and FIGS. 9 is a diagram showing a conventional flip-flop circuit, FIG. 9 is a block diagram of the master-slave type, FIG. 10 is a timing chart of the circuit shown in FIG. 9, FIG. 11 is a block diagram of the latch circuit type, FIG. Figure 12 shows the FIG. 13 is a timing chart for explaining the problem of the latch circuit type, FIG. 14 is a timing chart for the circuit shown in FIG. 11, and FIG. 15 is its flip-flop. FIG. 3 is a block diagram in the case where a large number of circuits are inside an LSI. 11a to 11n, 200: latch circuit, 12, 201: pulse generation circuit, 21, 22, 41, 61, 81: inverter, 23, 31, 5
1, 71, 91 ... buffer gate, 24, 43, 63, 83 ... NOR gate, 32, 52, 72, 92 ... AND gate, 42 ... NAND gate, 62 ... multiplexer, 82 ... exclusive NOR gate, 101-110, 121-130, 141-150 ...
Transistors, 111, 131, 151 ... constant current sources, 112 to 11
7, 132-137, 152-157 ... Resistance.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03K 3/037 H03K 3/286

Claims (1)

(57) [Claims] A pulse generating circuit for generating a signal having a minimum pulse width for operating a latch circuit when a clock signal is externally supplied; and supplying a signal having a minimum pulse width generated by the pulse generating circuit. A latch circuit that latches an input signal in synchronization with a signal, wherein the pulse generation circuit includes a multiplexer or an exclusive NOR gate, and the multiplexer or the exclusive NOR gate is configured with substantially the same circuit configuration as the latch circuit. A flip-flop circuit.