JP2010273322A - Flip-flop circuit with majority circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that improvement of immunity to software error and reduction of circuit scale cannot be comatible. <P>SOLUTION: A clock adjusting circuit 7 adjusts a ratio between a high state and a low state of an input clock signal CLK to narrow a data hold time zone of one master latch 1, and outputs the ratio between a high state and a low state of an input clock signal CLK while narrowing the high state (a data hold time of the master latch 1) as far as possible. An inverter 6 performs the reversal of polarity of the output of the clock adjusting circuit 7. A transfer gate 4 of the master latch 1 and transfer gates 5-1 to 5-3 of slave latches 2-1 to 2-3 control passage of data, in accordance with outputs of the clock adjusting circuit 7 and inverter 6. Outputs of the slave latches 2-1 to 2-3 become an output signal Q after a rule by the majority is performed by a three-input majority circuit 3. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a logic circuit that holds and outputs data signals, and in particular, can hold and output correct memory contents even if a soft error occurs due to external factors such as α rays and secondary cosmic ray neutrons. The present invention relates to a flip-flop circuit with a majority circuit.

In order to enhance resistance against a soft error in which the flip-flop data is rewritten to an unintended value due to external factors such as α rays and secondary cosmic ray neutrons, for example, FIG.
As shown in FIG. 3, three flip-flops each consisting of a master latch 1, a slave latch 2 and transfer gates 4 and 5 are arranged and made redundant, and the output data of the three flip-flops is majority decided by a three-input majority circuit 3. There are known ways to avoid the effects of soft errors. However, in this method, since a plurality of flip-flops having the same configuration each having a master latch and a slave latch are provided, the circuit scale increases, and the area occupied by the logic circuit and power consumption also increase.

In order to solve this problem and reduce the circuit scale, two master latches and one slave latch are used instead of the three master latches 1 and slave latches 2 in connection with the flip-flop circuit of FIG. It is public to make a majority decision with latches. But,
In this configuration, if a soft error occurs in the data retention time zone of the slave latch,
The effect cannot be avoided and the correct data cannot be restored.

  In addition, a delay adjustment circuit that adjusts the data capture timing and supplies it to the master latch circuit is provided in the preceding stage of the register composed of the master latch circuit and the slave latch circuit, and technology that can cope with the recent increase in CPU speed is also disclosed. Has been.

WO2004 / 105241 publication JP 2000-315391 A

The problem to be solved is that it is impossible to achieve both improvement in resistance to soft errors and reduction in circuit scale.

The most important aspect of the present invention is that the holding time of the input data signal of the master latch is shortened by adjusting the ratio between the high state and the low state of the clock signal, and the resistance against the soft error during the data holding time of the master latch is increased. Features.

The flip-flop circuit with a majority circuit of the present invention has one master latch, shortens the holding time of the input data signal as much as possible, reduces the number of occurrences of soft errors during the data holding time of the master latch, and It is advantageous to improve the resistance against soft errors while reducing the circuit scale by avoiding the influence of soft errors during the data holding time of the slave latch by majority vote.

It is a circuit diagram which shows Example 1 of this invention. 3 is a detailed diagram of a clock adjustment circuit in Embodiment 1. FIG. It is a waveform diagram of a clock adjustment circuit. 3 is a first timing chart for explaining the operation of the first embodiment. 6 is a second timing chart for explaining the operation of the first embodiment. It is a circuit diagram which shows Example 2 of this invention. 6 is a circuit diagram of a 5-input majority circuit in Embodiment 2. FIG. It is a figure which shows the truth table of 5 input majority circuit. It is a circuit diagram which shows Example 3 of this invention. 10 is a timing chart of Example 3. 6 is a timing chart for explaining problems of the first to third embodiments. It is a circuit diagram which shows Example 4 of this invention. 10 is a timing chart for explaining the operation of the fourth embodiment. It is a circuit diagram which shows the example of the conventional flip-flop circuit with a majority circuit.

The purpose of both improving resistance against soft errors and reducing the circuit scale is realized by reducing the number of master latches and the data holding time zone of the master latches.

  FIG. 1 is a circuit diagram of Embodiment 1 of the circuit of the present invention. Basically, master latch 1 and slave latch 2, and transfer gates 4 and 5 for controlling the input of data signals to each latch are shown. Become. And in order to avoid the influence of a soft error, the slave latch 2 is made into the three slave latches 2-1 to 2-3, and it has the 3-input majority decision circuit 3 which takes the majority decision about the output. Compared with the circuit of FIG. 14, there is a difference in that one master latch is provided and a clock adjusting circuit 7 is further provided. The three slave latches 2-1 to 2-3, the 3-input majority circuit 3 and the inverter 6 are the same as the circuit of FIG.

  The clock adjustment circuit 7 adjusts the ratio of the high state and low state of the input clock signal CLK so as to narrow the data holding time zone of the master latch, and enables the high state of the clock signal CLK (data holding time of the master latch 1). Output as narrowed as possible. The degree is the shortest time during which the master latch 1 holds data and the slave latch 2 can input data. As described above, since there is one master latch, there is no protection by majority vote. However, if the data holding time zone is shortened, the number of soft errors occurring in the master latch 1 is extremely reduced. The inverter 6 inverts the polarity of the output of the clock adjustment circuit 7.

  The output of the clock adjustment circuit 7 is supplied to the negative gate of the transfer gate 4 for the master latch 1 and the positive gate of the transfer gate 5 for the slave latch 2. The output of the inverter 6 is supplied to the positive gate of the transfer gate 4 for the master latch 1 and the negative gate of the transfer gate 5 for the slave latch 2. As a result, in one of the master latch 1 and the slave latch 2, if one is a data holding time zone, the other is a data input time zone, and if one is a data input time zone, the other is a data holding time zone.

The transfer gate 4 closes when the clock signal CLK is high and the data signal DI
N is refused to be input to the master latch 1, and is opened in the low state to allow the data signal DIN to be input to the master latch 1. On the other hand, the transfer gate 5 opens when the clock signal CLK is high and allows the input of the master latch 1 output, and closes when the clock signal CLK is low and rejects the input of the master latch 1 output to the slave latch 2. In this way, the three transfer gates 5-1 to 5-3 and the slave latches 2-1 to 2-3 of the slave side input all operate at the same timing.

  The 3-input majority circuit 3 determines the majority of the outputs of the slave latches 2-1 to 2-3, and corrects the majority even if a soft error occurs in any one of the slave latches 2-1 to 2-3. As a result, a correct value is output as the output signal Q of the flip-flop. The 3-input majority circuit 3 is composed of three 2-input NANDs and one 3-input NAND, and outputs of slave latches 2-1 and 2-2, outputs of slave latches 2-1 and 2-3, and slave latch 2-2. And 2-3 outputs are respectively input to the 2-input NAND, and the negative OR of the three 2-input NAND outputs is taken by the 3-input NAND.

When the low state of the clock signal CLK becomes longer in the clock adjustment circuit 7, the time during which the transfer gate 4 is open becomes longer. However, during that time, the data signal DIN is always input to the master latch 1, and the slave latches 2-1 to 2-3 are in the data holding state. Therefore, even if a soft error occurs in the master latch 1, there is no problem because there is no input from the master latch 1 to the slave latch 2. On the other hand, when the clock signal CLK is high,
The master latch 1 is in a data holding state and the slave latch 2 is in a data input state. But,
By providing the clock adjustment circuit 7, the time of the data holding state of the master latch 1 that is not subject to majority decision is shortened, so that the probability that the influence of the soft error becomes apparent as the output signal Q of the flip-flop is extremely low.

FIG. 2 is a circuit diagram showing a detailed example of the clock adjustment circuit 7, and FIG. 3 is a timing chart thereof. This circuit example includes a delay gate 8 that delays a clock signal CLK, an inverter 9, and a two-input AND gate 10. The clock signal CLK is input to the AND gate 10 and the delay gate 8. Based on the adjusted clock output, the delay gate 8 delays the clock signal CLK by the shortest time that the master latch 1 holds data and the slave latches 2-1 to 2-3 can input data. The output of the delay gate 8 is inverted by the inverter 9 and ANDed by the clock signal CLK and the AND gate 10, whereby the shortest high-state adjusted clock output that allows the master latch 1 to hold data can be created.

FIG. 4 is a timing chart showing the operation when a soft error occurs. As described above, the clock signal that has passed through the clock adjustment circuit 7 is shortened in the high state, and the time period of the data retention state of the master latch 1 is shortened. Now, assume that a soft error a occurs in the slave latch 2-3 at the timing t1 when the clock signal CLK is in the low state, and the output of the slave latch 2-3 drops from the high state to the low state. Since the slave latch 2-3 is in the data holding state, it holds the error state immediately after the soft error occurs. The outputs of the three slave latches 2-1 to 2-3 are input to the majority circuit 3.

The output signal of the slave latch 2-1 and the output signal of the slave latch 2-2 input to the majority circuit 3 output a low level by the logic of the NAND gate. On the other hand, the two NAND gates receiving the output signal of the slave latch 2-3 in which a soft error has occurred both output high. For this reason, the output of the 3-input NAND, that is, the output signal Q of the flip-flop is in a high state, and the soft error a generated in the slave latch 2-3 is not manifested.

Next, assume that a soft error b occurs in the master latch 1. As described above, since the high state of the output signal of the clock adjustment circuit 7 has a very short width, the master latch 1 has a very short data holding state. Therefore, there is a high probability that the soft error b occurs in the data input state in the master latch 1 as at the timing t2. This soft error b is not accepted by the slave latch 2 because the transfer gate 5 is closed.

Incidentally, if there is no clock adjusting circuit 7 and the data holding state of the master latch 1 is the same length as the data input state as shown in FIG. 5, the data holding state of the master latch 1 (the data input state of the slave latch 2). ) Is likely to cause soft error b. Since the soft error b is propagated to all the slave latches 2, even if the majority circuit 3 is provided, it cannot be recovered.

As described above, in the flip-flop circuit of the present invention, the probability of holding the soft error in the master latch 1 is reduced by providing the clock adjustment circuit 7, and three or more slave latches 2 are prepared, and each output is the majority circuit 3. Error correction is performed using the logic of

FIG. 6 shows an embodiment of a flip-flop circuit with a majority circuit in which the number of slave latches 2 is five. Compared to FIG. 1, slave latches 2-1 to 2-5 and transfer gate 5-1
The 5-input majority circuit 11 is incremented by 2 to 5-5. 7 is a circuit diagram of the 5-input majority circuit 11, and FIG. 8 is a truth table of the 5-input majority circuit 11.

In this embodiment, it is assumed that the slave latches 2-1 and 2-2 generate a soft error. For example,
If the soft error is changed from "1" to "0", the slave latch 2-3 to 2-5
Is “1”, and the output signal Q is “1” according to the eighth row of the truth table, and holds the correct value. If the soft error is changed from “0” to “1”, the outputs of the slave latches 2-3 to 2-5 are “0”, and the output signal Q is determined from the 25th row of the truth table. It is “0” and holds the correct value.

FIG. 9 shows an embodiment of a flip-flop circuit with a majority circuit in which a plurality of master latches are provided and a majority circuit is provided. The three-input majority circuit 12 makes sure that correct data is retained even when a soft error occurs in the master latches 1-1 to 1-3 during the data retention time period of the three master latches 1-1 to 1-3. is there. This example is shown in FIG.
However, the present invention can also be applied to the flip-flop circuit of FIG.

FIG. 10 is a timing chart showing the operation when a soft error occurs.
Assume that soft errors a and b occur in two of the slave latches 2 when the slave latches 2-1 to 2-5 are in the data holding state. Even if two soft errors occur at the same time, the outputs of the slave latches 2-1 to 2-5 will show normal values by majority vote, so that the manifestation of soft errors is avoided and the output signal Q of the flip-flop is normal. Output a correct value. Further, even if one of the master latches 1-1 to 1-3 holds the soft error c during the data holding time period, the three-input majority decision circuit 12 can avoid the occurrence of the soft error.

As described above, the error correction function is added to the master latch 1 which originally reduced the probability of occurrence of the soft error as shown in FIG. 1 and FIG. 6, and the error correction function of the slave latch 2 is improved. It becomes possible to keep the manifestation as low as possible.

  In the embodiment described above, for example, the slave latch 2-1 of the embodiment 1, when a soft error occurs in the data holding time zone as shown in FIG. 11, the slave latch 2-1 is erroneous during the data holding period. Keep retaining data. This state lasts until the output signal of the clock adjustment circuit 7 becomes the next high state (the slave latch is in the data input state). In this state, for example, if a soft error occurs in the slave latch 2-3, it can no longer be remedied by the three-input majority circuit 3.

  Therefore, in this embodiment, a majority circuit is provided in one-to-one correspondence with the slave latch. FIG. 12 corresponds to the first embodiment (FIG. 1), and three-input majority circuits 3-1 to 3-3 are provided in one-to-one correspondence with the slave latches 2-1 to 2-3. In the 3-input majority circuit 3-1, the majority of the outputs of the right-pointing inverters of the 3-input majority circuits 3-1 to 3-3 is determined, and the output is input to the left-side inverter of the 3-input majority circuit 3-1. The same applies to the 3-input majority circuits 3-2 to 3-3. The output of any of the 3-input majority circuits 3-1 to 3-3 can be the output signal Q of the flip-flop circuit.

  As a result of such a configuration, for example, even if a soft error a occurs in the data holding time zone in the 3-input majority circuit 3-1, it is corrected in a short time as shown in FIG. The time required for this correction is the time required for data to pass through the 2-input NAND and 3-input NAND in the 3-input majority circuit 3-1. Therefore, even if a soft error occurs in the three-input majority circuit 3-2 or the three-input majority circuit 3-3 in the same data holding time zone where the soft error a has occurred, the probability of overlapping is low, and the output of the flip-flop circuit Q is correct data.

  Of course, the idea of the fourth embodiment can be applied to the second or third embodiment.

  A part or all of the above embodiments can be described as in the following supplementary notes, but is not limited to the following.

  (Supplementary Note 1) An odd number of slave latches provided at the subsequent stage of the master latch, a master latch for controlling the passage of data to the master latch and the slave latch, a transfer gate corresponding to the slave latch, and an output of each slave latch A majority circuit that takes the majority as an output signal, and adjusts the ratio of the high and low states of the input clock signal to narrow the data retention time zone of the master latch and adjusts the clock supplied to the transfer gates of the master latch and slave latch A flip-flop circuit with a majority circuit, characterized by comprising a circuit.

  (Supplementary note 2) The flip-flop circuit with a majority circuit according to Supplementary note 1, wherein the data holding time zone of the master latch is a shortest time in which the master latch holds data and the slave latch can input data.

  (Supplementary note 3) The flip-flop circuit with a majority circuit according to Supplementary notes 1 and 2, wherein the master latch and the accompanying transfer gate are provided as one.

  (Supplementary Note 4) The flip-flop circuit with a majority circuit according to any one of Supplementary Notes 1 and 2, wherein an odd number of master latches and associated transfer gates are provided, and a majority circuit for taking a majority decision of the output of each master latch is provided.

  (Supplementary Note 5) The flip-flop circuit with a majority circuit according to any one of Supplementary Notes 1 to 4, wherein a majority circuit is provided in one-to-one correspondence with the slave latch.

  (Supplementary Note 6) The slave latch includes a first inverter that inputs the output of the corresponding transfer gate and a second inverter that outputs the output to the first inverter. Note 5 is characterized in that the output of one inverter is input and output to the second inverter, and either the slave latch or the one-to-one correspondence majority circuit is used as the output of the flip-flop circuit with the majority circuit. A flip-flop circuit with a majority circuit described in 1.

DESCRIPTION OF SYMBOLS 1 Master latch 2 Slave latch 3,12 3 input majority circuit 4,5 Transfer gate 6,9 Inverter 7 Clock adjustment circuit 8 Delay gate 10 AND gate 11 5 Input majority circuit

Claims (6)

An odd number of slave latches provided after the master latch; and
A master latch and a slave latch for controlling the passage of data to the master latch and the slave latch and a one-to-one correspondence transfer gate;
A majority circuit that takes the majority of the outputs of the slave latches as an output signal;
And a clock adjustment circuit for adjusting a ratio between a high state and a low state of the input clock signal so as to narrow a data holding time zone of the master latch and supplying the master latch and the slave latch with the transfer gate. Flip-flop circuit with majority circuit.   2. The flip-flop circuit with a majority circuit according to claim 1, wherein the data holding time zone of the master latch is a shortest time during which the master latch holds data and the slave latch can input data. 3. The flip-flop circuit with a majority circuit according to claim 1, wherein the master latch and the accompanying transfer gate are provided as one. 3. A flip-flop circuit with a majority circuit according to claim 1, further comprising a majority circuit that takes an odd number of master latches and associated transfer gates and that determines the majority of the outputs of the master latches.   5. The flip-flop circuit with a majority circuit according to claim 1, wherein a majority circuit is provided in one-to-one correspondence with the slave latch. The slave latch includes a first inverter that inputs an output of a corresponding transfer gate and a second inverter that outputs the first inverter.
The slave latch and a one-to-one correspondence majority circuit input the output of the first inverter and output it to the second inverter,
6. The flip-flop circuit with a majority circuit according to claim 5, wherein any one of the majority circuits corresponding to the slave latches is used as an output of the flip-flop circuit with the majority circuit.

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