JPS607224A - Data latch circuit - Google Patents

Abstract

PURPOSE:To attain low power consumption without giving limit conditions to the level of input data by allowing an input buffer circuit to be in operating state only when the input data is fed to a latch circuit, that is, to be in the normal operation while being connected to a power supply. CONSTITUTION:Either a P-channel MOSFET31 or an N-channel MOSFET32 constituting a CMOS inverter 33 is turned on by an output of a clocked CMOS inverter 38 in the data holding operation by a latch circuit 12. When a current path is produced between an output terminal 26 and a VDD supply terminal or a ground potential supply terminal in a series circuit 213 of the final stage of an input buffer circuit 11 in this case, a through-current flows between the VDD and ground in a circuit combining the input buffer circuit 11 and the latch circuit 12, but no current path is produced both for the P-channel and the N-channel side of each series circuit 21 in this period, and each output terminal 26 is brought into a high impedance state and no through-current is produced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a 0MO8 type data latch circuit that reduces power consumption.

[Technical background of the invention and its problems]

FIG. 1 is a circuit diagram of a conventional 0MO8 type data latch circuit. This data latch circuit consists of a manual buffer circuit 1 consisting of a cNas inverter for amplifying or level converting input data In to a voltage level necessary for latch circuit operation, and a latch circuit 2 for holding input data. It is being constructed.

In the conventional circuit shown in FIG. 1, input data In is taken into the latch circuit 2 during the low level period of the latch control signal as shown in the timing chart shown in FIG. It is held in circuit 2. During the period when the latch control signal is at a high level, the input data I
The data in the latch circuit 2 is held regardless of rI. Further, in FIG. 2, the area inside the hatching of the input data In and the latch data Out is an area where the data is undefined, and is the area a.

C is an interval in which the data held in the latch circuit 2 does not change, and in this interval, the input data In is changed to the latch data O
This is the section output as t.

By the way, in such a data latch circuit, if the latch circuit 2 stops operating, this latch circuit 2
Even if the circuit is configured such that only a small current flows in the input circuit 1, a large current will flow in the input pub circuit 1 when the voltage of the input data 1n reaches an intermediate level near the input 8fufufu threshold voltage VTHC.

FIG. 3 is a characteristic diagram showing the relationship between the through current ID and the voltage VIN of the input 8-fufufu data In. As shown in Figure 3, ■IN is V-cho,
, c, the largest through current flows through the input 8fufufu. For this reason, in the conventional circuit shown in FIG. 1, it is not possible to realize a low scanning current circuit as a whole. Therefore, in order to achieve low power consumption with this conventional circuit, the voltage level of the input data In must be fixed to the power supply voltage or ground level, and if 1 is better than 1, it is not necessary. The purpose of this design is to provide a data latch circuit that can realize low power consumption without imposing any restrictions on the level of input data.

[Summary of the invention]

In the data latch circuit according to the present invention, in order to input 8 fuff, the input 8 is in an operating state, that is, it is connected to the power supply and performs normal operation only during the period when the input is transmitted to the latch circuit, and the input 8 is set to be 8 fhuf during the other periods. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 4, 1 is a control signal generation circuit that generates a control signal for controlling the input 8 buffer circuit 11 and the latch circuit 12, 14 is an input terminal for input data In, and 15 is a latch control signal input terminal. The input buffer circuit 1 includes two P-channel MO8FETs 17 and 18 between the positive power supply potential vDD supply terminal and the output terminal 16.
Three series circuits 21, 211 to 213, are provided by connecting in series the output terminal 16 and the ground potential supply terminal, and further connecting two N-channel □□□5FETs 19 and 20 in series. .

Of each series circuit 2i1 to 213, one P channel M
) SFET i g and one N-channel MO8FET'
190 gate electrodes are commonly connected, and this common connection point serves as the data input terminal 22 of each series circuit 211-213. The three series circuits 21 to 213 are connected in multi-stage cascade by connecting the output terminal 16 of the previous stage to the data input terminal 22 of the latter stage, and the data input terminal 22 of the first stage circuit 211 is connected to the input terminal 14. . Furthermore, in the three series circuits 211 to 213, P channel 5FET J
7 dart electrodes are connected in parallel and similarly N-channel M) SFET, ? o dart electrodes are connected in parallel.

The child circuit 12 consists of a P-channel MO8FET s J and an N-channel M) SFET s z connected in series between the DD supply terminal and the ground potential supply terminal.
b) A CMOS inverter 33 to which the dirt electrodes of SFETs s A so-called clocked C...S inverter 38 is provided in which the MO8FETs s e and s 7 are connected in series, and the gate electrodes of the MO8FETs s s and s 7 are connected in common. The input terminal of the CMOS inverter 33 is connected to the output terminal 16 of the final stage series circuit 213 in the input buffer circuit 11, and the clocked CMOS inverter 38 is connected in antiparallel to the CMOS inverter 33. .

The control signal generation circuit No. 3 includes three stages of inverters 41 to 43.
A delay circuit 44 that delays and inverts the latch control signal for a predetermined period, a NAND dart 45 and another inverter 46, and a predetermined pulse width as shown in FIG. A pair of control signals L E having a complementary relationship with each other.
, LE is output. One of these control signals LE is applied to the parallel connection point of the r-to electrode of each P-channel M) SFET J7 in the input buffer circuit 1 and the N-channel Th/DSFET in the latch circuit 12.
, V7, and the other control signal L
F is each N-channel MO in the input buffer circuit 1
8FET 2o dart electrode parallel connection point and N channel 1lvK) SFET s in the latch circuit J2
It is supplied to the gate electrode of No. 4.

In the data latch circuit configured as shown in FIG. 4, each M)S
During the period when FET J 7 is on and the control signal LE is at a high level, each MO8FET 2o is on. As a result, the P-channel MO8FET J s and the N-channel MO8F of the input buffer circuit 11
Each impark consisting of ET 19 is connected to the power supply potential VDD and the ground potential, respectively, and functions as a normal inverter (during the buffer enable period), and transmits input data In to the latch circuit 12 in an inverted state. In addition, in this latch circuit 12, the control signal LE is at a low level and the control signal LE is at a high level' (clocked CM during the period) S4:
Since the P-channel MO8FET 34 and the N-channel MO8FET s7 in the inverter 37 are each turned off, the clocked CM)S inverter 38 does not operate. Therefore, in this case, the input buffer circuit 11
During a period in which the output is simply inverted by the CMOS inverter 33 in the latch circuit 12 and is at the output level, each of the N5FETs Jy and each MO8FET 20 in the input buffer circuit 1 are slightly turned off. Then, the P channel MO in each series circuit 211 to 213
Since each inverter consisting of 8FET18 and N-channel MO8FET J9 is disconnected from both the power supply potential and the ground potential (buffer disable period), the input buffer circuit 11 has a through-hole between VDD and ground regardless of the voltage level of the input data In. No current flows. On the other hand, in this period, the clocked C of latch circuit J2
MOSFET s 4 in the MOS inverter 37,
Both s and y are turned on, which causes the clocked CMOS inverter 38 to work, and the output from the input buffer circuit 11 is held stably by a feedback loop consisting of the CMOS inverter 33 and the clocked CMOS inverter 38 in the latch circuit 12. Ru. That is,
The latch circuit 12 takes in the data transmitted from the input buffer circuit 11 during a period when the control signal LE is at a low level and LE is at a high level, and then holds the data taken in during a period when the signal LE is at a high level and LE is at a low level. do. Here, during the data holding operation by the latch circuit 12, the CMO
P channel M) SFET that constitutes the S inverter 33
31 and the N-channel MO8FET s 2 are turned on by the output of the clocked CMOS inverter 38. Therefore, at this time, if a current path is generated between the output terminal 26 and the VDD supply terminal or the ground potential supply terminal in the final stage series circuit 213 of the input buffer circuit 11, the input buffer circuit 11 and the latch circuit 12 In a circuit that combines these, a through current will flow between VDD and ground. However, during this period, no current path occurs on the channel side and the N channel side of each series circuit 210P, and each output terminal 26 is all in a high impedance state, so there is no possibility that the above-mentioned through current will occur. .

Therefore, in this embodiment circuit, the input data In need only be set to the necessary level during the periods when the control signals LE and LE are at high and low levels, and the input buffer circuit sets the input data In to the level of the input data 1n during other periods. 11 becomes irrelevant, and the power consumption of the entire circuit can be reduced.

Note that the present invention is not limited to the above-mentioned embodiments, and various applications are possible. For example, although we have described the case where the circuit is configured with connected series circuits, any number of stages may be used as long as it is one or more stages. After latching, the input buffer circuit is disconnected from both the power supply potential and the ground potential, so it is possible to provide a data latch circuit that can achieve low power consumption regardless of the level of input data.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional data latch circuit, and Figure 2 is a circuit diagram of a conventional data latch circuit.
Fig. 3 is a voltage-current characteristic diagram of a general CMOS inverter, Fig. 4 is a circuit diagram of an embodiment of the present invention, and Fig. 5 is a timing chart of the circuit of Fig. 4. This is a timing chart. 11... Input buffer circuit, 12... Latch circuit,
13...Control signal generation circuit.

Claims (1)

[Claims] A first P channel between the first potential supply end and the output end;
A second MOSFET is inserted in series, and N-channel third and fourth MOSFETs are inserted between the second potential supply end and the output end.
A human-powered buffer circuit in which one or more stages of circuits are connected in series to serve as data input terminals by connecting the gate electrodes of the second and third edge 5FETs in series, and the output of this human-powered buffer circuit. and a means for making the first and fourth 5FETs conductive for a predetermined period and causing the latch circuit to take in the output from the manual buffer circuit within this period. Characteristic data latch circuit.