JPS6150421A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To speed up a delay time by the operation close to ratioless operation by detecting/accelerating/amplifying an input signal and outputting it when the input signal is inputted to an input buffer and the delay circuit so as to suppress the brought-current to a minimum value even if the input signal has a voltage change. CONSTITUTION:The titled circuit consists of series circuits S1, S2 and inverter circuits I1, I2. When the level of a signal input terminal D1 is low, a connecting point D2 goes to a high voltage level, a connecting point D3 goes to a low voltage level, and a signal output terminal D4 goes to a high voltage level. When the D1 goes to a high voltage level from a time t1 to t6, the D2 starts charging from a high voltage level to a low voltage level from the t2. The series circuit S1 is ratioless, no through-current exists at all, and the signal waveform at the D2 is sharper. The D3 starts changing from a low voltage to a high voltage level from a point of time delayed slightly from the t2. Further, the D4 starts changing from a high voltage to a low voltage at a point of time slightly delayed from the t3 and goes completely to a low voltage level at a point of time delayed slightly from the t5.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention comprises complementary MOS transistors;
The present invention relates to semiconductor integrated circuits, and is particularly suitable for use in input buffers, signal acceleration amplifier circuits, etc. in semiconductor integrated circuits.

[Technical Background of the Invention and Problems Therewith] In general, input buffers use ratio circuits and take 1 to 6 seconds, so when inputting at a TTL level, particularly through-current flows and the output waveform deteriorates.

Here, FIG. 5 shows an example of a level conversion circuit that converts a TTL level into a MOS level using a conventional input buffer.

In FIG. 5, 1 is a P-channel type MOS transistor (hereinafter referred to as PMOS transistor), 2 is an N-channel type MOS transistor (hereinafter referred to as NMOS transistor), which constitute an inverter circuit, and 3 is a signal The input terminal and 4 are signal output terminals. In addition,
FIGS. 6(a) and 6(b) show operating waveforms, and FIG. 6(C) shows current consumption characteristics.

In such a circuit, if we consider a case where a signal that changes from a low voltage level to a high voltage level is input to the signal input terminal 3, then the signal output terminal 4 changes from a high voltage level to O voltage levels. Start. but,
This circuit is a ratio circuit because it is an inverter circuit, and when the input voltage level of signal input terminal 3 is near the circuit threshold voltage of the inverter circuit, PMOS transistor 1 and NM
Both OS transistors 2 are in the on state, so a through current flows and the delay time also worsens. Therefore, access times in semiconductor integrated circuits have become extremely fast, which has led to faster cycle times.
In response to this, it is necessary to reconsider how to increase the speed and reduce power consumption in input buffers, and an input level conversion circuit that consumes less current and has a faster response speed has been desired.

[Object of the Invention] The present invention has been made in view of the above circumstances, and its purpose is to minimize the through current even when there is a voltage change in the input signal, and to achieve a ratioless design. It is an object of the present invention to provide a semiconductor integrated circuit that can achieve faster delay times due to closer operation.

[Summary of the Invention] The semiconductor integrated circuit of the present invention detects, accelerates, amplifies, and outputs an input signal when it is input to an input buffer sofa and a delay circuit.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, a PMOS transistor TI.

T2 and NMOS transistor T3. T4 are connected in series in that order to constitute a first series circuit S1. One end of the PMOS transistor T1 of this first series circuit S1 is connected to the positive power supply V1, and one end of the NMo5 transistor T4 is connected to the power supply (I
I ground potential) is connected to V2. And PMOSMOS
The transistor T2NMOS transistor T3-to is connected to the signal input terminal D1. Also, PMOSMO
S transistor T2 OSMOS transistor T3 connection point D
2 is connected to the input terminal of the first inverter circuit 11 and the connection point between the PMOSMOS transistor T6o5 and the transistor T7 of the second series circuit S2. Second series circuit S2
has the same configuration as the first series circuit S1, and PMOSMO
S transistor T5 and NMOS transistor T7.
The OFF transistors are connected in series in that order, the PMOSMOS transistor T5 is connected to the power supply ■1, and the NMOSMOS transistor
Transistor T8 is connected to power supply ■2.

Here, the first inverter circuit 11.15 and the second series circuit S2 constitute a delay holding circuit F1. The output terminal of the first inverter circuit 11 is connected to the PMOS of the second series circuit S2.
The MOS transistor T6NMo5 is connected to each gate of the transistor T7 and the input terminal of the second inverter circuit 2. The output terminal of the second inverter circuit I2 is connected to the signal output terminal D4 and the PMOS transistor T1 and the NMOS transistor T4 of the first series circuit S1. The PMOS transistor T5 and the NMOS transistor T8-to of the second series circuit S2 are connected to the signal input terminal D1.

Next, the operation of the above configuration will be explained with reference to the operation waveforms shown in FIG. Before time t1, when the signal input terminal D1 is at the low voltage level, a signal at the high voltage level is output to the connection point D2, a low voltage level to the connection point D3, and a high voltage level signal to the signal output terminal D4. In such a state, the signal input terminal D1 becomes
), the voltage starts changing to a high voltage level from time t1, and reaches a high voltage level from time t6.
PMOS transistor T2. T5 turns off and NMOSt
- transistor T3. T8 turns on. Also, NMOSM
Since the OS transistor T4 is active, the voltage level at the connection point D2 starts changing from the high voltage level to the low voltage level from time t2, as shown in FIG. 2(b). P.M.O.
Since the S transistor T1 is off, the first \L column circuit $1 is ratioless, so there is no through current at all, and although some current flows into the second series circuit $2, it is negligible and the connection point D2 signal 9 waveform u
*V)>v-7 "h!, connection point D comma 7) lit
.

Due to the power voltage, the voltage level at the connection point D3 starts changing from the low voltage level to the high voltage level at a time slightly delayed from time t2, as shown in FIG. 2(C). This turns off the PMOS transistor T6 and turns off the NMOS transistor T7. In addition, there is an NMOSMOS transistor T8, and the voltage level of the connection point D2 is at the second level.
A feedback circuit including a series circuit S2 maintains the level to a low voltage level. Also, due to the output voltage of the connection point D3, the signal output terminal D4 is output as shown in FIG. 2(d).
The voltage level of PMOS transistor T1 starts changing from a high voltage level to a low voltage level at a time slightly later than time t3, and completely becomes a low voltage level at a time slightly later than time t5. turns on,
NMOSMOS transistor T4. In this state, the first
The series circuit S1 has the next input signal, and as a result, the connection point D2 has no current path from the first series circuit S1, but the signal level is maintained due to the feedback action of the second series circuit S2. Furthermore, when the signal input terminal D1 changes from a high voltage level state to a low voltage level state, the signal changes in the same manner as described above. The operation is performed in m ways as described above.

Note that the input buffer circuit may be optimized by optimizing the threshold voltage of the MOS transistor in the first series circuit S1.

For example, the equivalent voltage of PMOS transistor 2 in the first series circuit S1 is -3.5 volts (V), and NMOS
When the OS transistor T3 voltage is set to 1.5 volts,
As shown in FIG. 3, since both transistors have the same voltage in the middle of the TTL level, even if a small amount of noise is added to the input level, the signal is difficult to be transmitted to the next stage. Therefore, a better circuit can be realized as a TTL level conversion circuit.

FIG. 4 shows another embodiment of the invention.

The difference between this embodiment and the previous embodiment is that the second series circuit S
2 is replaced with a third inverter circuit I3, and the circuit configuration includes a transmitting gate. That is, the output terminal of the first inverter circuit 1 is connected to the input terminal of the third inverter circuit I3, and the output terminal of the third inverter circuit I3 is connected to the PMOS transistor T9 and NMo.
It is connected to one end of each of five transistors T10. Also, P
MOS transistor T9 and NMo5 transistor T
Each other end of the transistor 10 is connected to a connection point between the PMOS transistor T2 and the NMo5 transistor T3 of the first series circuit s1. and PMos transistor T9 and NMO
Each gate of the s-transistor T1o is connected to a signal input terminal D1. Here, the first inverter circuit 11, the third inverter circuit 3, and the PMOS transistors T9 and N
M.

The S transistor T10 constitutes a holding circuit F2.

In such a configuration, if a low voltage level signal has been applied to the signal input terminal D1 for a long time, the PMOS transistor T9 is turned on and the holding circuit F2 closes the connection point D2.
is maintained at a high voltage level. In addition, the signal input terminal D1 is at the low voltage level (L or 5"'@JEL//<A'
Ni:i! NLfll・2"08 transistor T9 is turned off and NMo5 transistor T10 is turned on. Feedback inverter circuit (third inverter circuit) 13 of holding circuit F2
Although the output is at a high voltage level, since it passes through the NMOS transistor TIO, the output level decreases due to the back gate effect. Therefore, the output of the first series circuit S1 and the output of the holding circuit F2 are unlikely to interfere. As described above, the circuit performs almost the same operation as the circuit shown in FIG.

With the configuration described above, current consumption can be reduced, and since the input signal is accelerated and amplified, it becomes possible to cope with high speed with low current consumption.

[Effects of the Invention] As described in detail above, according to the present invention, even when there is a voltage change in the input signal, the through current can be suppressed to a small degree, and due to the nearly ratioless operation, there is no delay opening. It is possible to provide a semiconductor integrated circuit that can achieve higher speeds.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, FIG. 2 is an operation waveform diagram for explaining the operation of the embodiment, and FIG. 3 is a diagram for explaining an example of setting the equivalent voltage in the input buffer. 4 is a block diagram showing another embodiment of the present invention, and FIG. 5 is a block diagram showing a conventional input buffer (inverter circuit).
FIG. 6 is a diagram showing the operating waveforms and current consumption characteristics of FIG. 5. T1. I2. I5. I6. I9...-PMOS transistor, I3. I4. I7. I8. T10...
NMOS transistor, DI...signal input terminal, D4...signal output terminal, Vl...first power supply, ■2...second power supply, 11.・・・・・・
1st inverter circuit, I2...2nd inverter circuit, I3...3rd inverter circuit/circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 t''1t'26 侃碩61 Figure 4 Figure 5 Figure 6 $r side (1)

Claims (3)

[Claims] (1) A first MOS transistor of a first channel type, a second MOS transistor, a third MOS transistor of a second channel type opposite to the first channel type, and a fourth MOS transistor
S transistors are connected in series in that order, and the first
A fifth channel-type MOS transistor and a sixth MOS transistor, and a second channel-type seventh MOS transistor and an eighth MOS transistor are connected in series in that order, one end of each of the first and fifth MOS transistors is connected to a first power supply, One end of each of the fourth and eighth MOS transistors is connected to a second power source paired with the first power source, each gate of the second and third MOS transistor is connected to a signal input terminal, and one end of each of the second and third MOS transistors is connected to a second power source that is paired with the first power source. The connection point is connected to the input end of the first inverter circuit and the connection point of the sixth and seventh MOS transistors, and the output end of the first inverter circuit is connected to the input end of the second inverter circuit and the connection point of the sixth and seventh MOS transistors. an output terminal of the second inverter circuit is connected to a signal output terminal and each gate of the first and fourth MOS transistors;
A semiconductor integrated circuit characterized in that each gate of an OS transistor is connected to the signal input terminal. (2) A first MOS transistor and a second MOS transistor of a first channel type, and a third MOS transistor and a fourth MOS transistor of a second channel type opposite to the first channel type.
S transistors are connected in series in that order, and the first MOS
One end of the transistor is connected to a first power supply, and the fourth MO
One end of the S transistor is connected to a second power source paired with the first power source, each gate of the second and third MOS transistors is connected to a signal input terminal, and the second and third MOS transistors are connected to each other.
The connection point of the MOS transistor is connected to the input end of the first inverter circuit, and the output end of the first inverter circuit is connected to the second inverter circuit.
and each input terminal of the third inverter circuit, and the output terminal of the second inverter circuit is connected to a signal output terminal and each gate of the first and fourth MOS transistors,
The output terminal of the third inverter circuit is connected to a first channel type ninth MOS transistor and a second channel type first MOS transistor.
0 MOS transistor, the other ends of the ninth and tenth MOS transistors are connected to the connection point of the second and third MOS transistors, and each gate of the ninth and tenth MOS transistor is connected to the signal input terminal. A semiconductor integrated circuit characterized by being connected to. (3) the first channel type is a P channel type;
3. The semiconductor integrated circuit according to claim 1, wherein said second channel type is an N-channel type.