JP2765331B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit,
In particular, the present invention relates to a level conversion circuit for converting a balanced input ECL level to a CMOS level.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a conventional level conversion circuit for converting an ECL level input of a balanced input to a CMOS level.

The level conversion circuit shown in FIG.
Are connected to the source electrodes of the second P-channel MOS transistor 55 and the second P-channel transistor 58 and the gate electrodes of the first N-channel MOS transistor 53 and the second N-channel MOS transistor 52,
Connected to the source electrodes of the third P-channel MOS transistor 57 and the fourth P-channel transistor 56 of the negative-phase input terminal 2 and the gate electrodes of the third N-channel MOS transistor 51 and the fourth N-channel MOS transistor 54; The drain electrode and the gate electrode of the first P-channel MOS transistor 55 are connected to the gate electrode of the third P-channel MOS transistor 57 and the drain electrode of the third N-channel MOS transistor, respectively. The drain electrode and the gate electrode are connected to the gate electrode of the second P-channel MOS transistor 58 and the drain electrode of the second N-channel MOS transistor 52, and the drain electrode of the second P-channel MOS transistor 58 is connected to the fourth N-channel MOS transistor 58.
Connected to the drain electrode of the channel MOS transistor 54 and the input of the first inverter circuit 500,
The drain electrode of the channel MOS transistor 57 is connected to the drain electrode of the first N-channel MOS transistor 53 and the input of the second inverter circuit 600, the positive-phase output terminal 11 is connected to the output of the first inverter circuit 500, The inverted phase output terminal 12 is connected to the second inverter circuit 60.
0, the first, second, third and fourth N-channel M
In this configuration, the source electrodes of the OS transistors 51, 52, 53, and 54 are connected to a power supply terminal.

[0004] Here, the first inverter circuit 500 includes:
The inverter circuit 600 has P and N channel MOS transistors 501 and 302, and the second inverter circuit 600 has P and N channel MOS transistors 301 and 502. These circuits are provided between the GND terminal 8 and the power supply terminal 9.

Here, a first P-channel MOS transistor 55 and a third N-channel MOS transistor 5
The connection node of the drain electrode of FIG.
The connection node between the channel MOS transistor 56 and the drain electrode of the second N-channel MOS transistor 52 is (b), and the connection node between the third P-channel MOS transistor 57 and the drain electrode of the first N-channel MOS transistor 53 is ( c), the second P-channel MOS transistor 58 and the fourth N-channel MO
The connection node of the drain electrode of the S transistor 54 is represented by (d).

[0006] As shown in FIG.
When an L level balance signal is input, the node (a)
The waveforms of (b), (c), and (d) are as shown in FIG. 5B, and the positive-phase output terminals and the negative-phase output terminals 11 and 12 have CMOS levels as shown in FIG. Is output and EC
The L level signal is converted to a CMOS level signal.

[0007]

This type of input buffer has a low input impedance and requires a large input current in order to operate at high speed. When it is driven in parallel from the outside, it has a low current driving capability. There is a problem that a large buffer is required and a large fan-out cannot be obtained.

It is an object of the present invention to provide a level conversion circuit which solves the above-mentioned problems and can increase the fan-out.

[0009]

According to the construction of the level conversion circuit of the present invention, a first input terminal is connected to a first N-channel MOS.
A gate electrode of the transistor is connected to an input of the first level shift circuit, and a second input terminal is connected to a second N-channel MO.
The gate electrode of the S transistor is connected to the input of the second level shift circuit, the gate electrode of the first P-channel MOS transistor is connected to the output of the first level shift circuit, and the gate of the second P-channel MOS transistor is connected. Connecting an electrode to the output of the second level shift circuit;
A drain electrode of the first N-channel MOS transistor is connected to a drain electrode of the first P-channel MOS transistor, and a drain electrode of the second N-channel MOS transistor is connected to the second P-channel MOS transistor.
The drain electrode of the OS transistor is connected, and a third N
The drain electrode of the channel MOS transistor is connected to the source electrodes of the first and second N-channel MOS transistors, the gate electrode of the third N-channel MOS transistor is used as a bias terminal, and the source electrode is used as a first power supply terminal. Connect the first and second P-channel MOs
The source electrode of the S transistor is connected to the second power supply terminal, at least two fully differential amplifiers are connected in series, and the first input of the first stage full differential amplifier is connected to the first N-channel MOS transistor and the second input terminal. One P-channel MOS
A second input is connected to a connection point of a drain electrode of the transistor, and a second input is connected to a connection point of a drain electrode of the second N-channel MOS transistor and the second P-channel MOS transistor. Is connected to the input of the first inverter circuit, the second output is connected to the input of the second inverter circuit, the first output terminal is connected to the output of the first inverter circuit, the second output terminal It is characterized in that it is connected to the output of the second inverter circuit.

[0010]

FIG. 2 is a circuit diagram showing a level conversion circuit according to an embodiment of the present invention.

In FIG. 1, in the circuit of this embodiment, a positive-phase input terminal 1 is connected to a gate electrode of a first N-channel MOS transistor 3 and an input of a first level shift circuit 100, and a negative-phase input terminal is connected. Gate electrode of second N-channel MOS transistor 4 and second level shift circuit 200
, The gate electrode of the first P-channel MOS transistor 5 is connected to the output of the first level shift circuit 100, and the second P-channel MOS transistor
Are connected to the output of the second level shift circuit 200, and the drain electrodes of the third N-channel MOS transistor 7 are connected to the source electrodes of the first and second N-channel MOS transistors 3.4. The gate electrode of the third N-channel MOS transistor 7 is connected to the bias terminal 1
0, the source electrode is connected to the first power supply terminal 9,
The source electrodes of the second P-channel MOS transistors 5 and 6 are connected to the GND terminal 8, and the first fully differential amplifier 30
0 positive-phase input to the first P-channel MOS transistor 5
Connected to the drain electrode of the first N-channel MOS transistor 3, and connected to the train electrode of the second channel MOS transistor 6 and the second P-channel MOS transistor 4, and connected to the second full differential amplifier. 40
0 positive phase input and negative phase input to the first fully differential amplifier 300
, And the first inverter circuit 500 is connected to the input and the second inverter circuit 60.
0 is connected to the positive-phase output and the negative-phase output of the second fully-differential multiplication field regulator 400, the positive-phase output terminal 11 is connected to the output of the first inverter circuit 500, and the negative-phase output terminal 1 is connected.
2 is connected to the output of the second inverter circuit 600.

The first and second level shift circuits 10
Reference numeral 0 · 200 connects the input to the gate electrode of the fourth N-channel MOS transistor 101, and connects the output to the source electrode of the fourth N-channel MOS transistor 101 and the drain electrode of the fifth N-channel MOS transistor 102. , The gate electrode of the fifth N-channel MOS transistor 102 is connected to the bias terminal 10, and the source electrode is connected to the first power supply terminal 9.
In this configuration, the drain electrode of the S transistor 101 is connected to the GND terminal 8.

The first pre-differential amplifier 300 has a positive-phase input and a negative-phase input connected to the gate electrodes of a sixth N-channel MOS transistor 301 and a seventh N-channel MOS transistor 302, respectively. Channel M
The drain electrode of the OS transistor 305 is connected to the source electrodes of the sixth and seventh N-channel MOS transistors 301 and 302, and the source electrode is connected to the power supply terminal 9, so that the third and fourth P-channel MOS transistors and the transistors 303 and 304 are connected.
Are connected to the power supply terminal, and the source electrodes of the third and fourth P-channel MOS transistors 303 and 304 are connected to the GND terminal 8. The second fully differential amplifier 400 has the same configuration as the second fully differential amplifier 300.

The first and second inverter circuits 500
• 600 is a fifth P-channel MOS input
Connected to the gate electrodes of the transistor 501 and the ninth N-channel MOS transistor 502, and outputs the fifth P-channel MOS transistor
The source electrode of the fifth P-channel MOS transistor 501 is connected to the GND terminal 8, and the source electrode of the ninth N-channel MOS transistor 502 is connected to the drain electrodes of the channel MOS transistor 501 and the ninth N-channel MOS transistor 502. In this configuration, the power supply terminal 9 is connected.

Here, the output of the first level shift circuit 100 is set to the node (a), and the output of the second level shift circuit 20 is
0 is the node (b), and the first fully differential amplifier 30
The positive-phase input / negative-phase input / positive-phase output / negative-phase output of 0 are nodes (c), (d), (f), and (e), respectively. Assuming that the negative-phase outputs are nodes (h) and (g), respectively, as shown in FIG. 2A, when the ECL level balance signal is input to the positive-phase input terminal 1 and the negative-phase input terminal 2, the node (a) 5A, a waveform obtained by level-shifting the waveform input to the positive-phase input terminal as shown in FIG. 5 (A) is output. Is output. First, second and third N-channel MOS transistors 3.
4.7 and the first and second P-channel MOS transistors 5.6 constitute a first N-channel MOS transistor.
The circuit composed of the S transistors 5 and 6 is connected to the gate electrode of the first N-channel MOS transistor 3 in a positive phase,
The second N-channel MOS and the gate electrode of the transistor 4 have opposite phase inputs, the node (c) has a negative phase output, and the node (d).
Is set to the positive-phase output, and the first P-channel MOS transistor 5 is connected to the second P-channel MOS
Transistor 6 is an active-load fully-differential amplifier controlled by node (b);
FIG. 2D shows the normal phase input terminal 1, the negative phase input terminal 2, the positive phase input terminal 1 and the negative phase input terminal as shown in FIG. 2 is output in an amplified form. Further, node (c).
The waveform of (d) shows the first and second fully differential amplifiers 300 and 4.
2 and amplified by the first and second inverter circuits 500 and 600 to the CMOS level, and output from the positive-phase output terminal 11 and the negative-phase output terminal 12 as shown in FIG.

FIG. 3 is a circuit diagram showing a level conversion circuit according to another embodiment of the present invention.

In FIG. 3, another embodiment of the present invention is different from the above-mentioned embodiment in that a bias terminal is connected to a GND terminal 9 and a bias potential is set to G without a bias terminal 10.
The level is set to the level of the ND terminal 8, and the gate electrodes of the P-channel MOS transistors 501 are connected to the power supply terminal 9 in the inverter circuits 500 and 600.

The operation is the same as that of the above-described embodiment, but since no special bias potential is required, no external bias circuit is required. The input of the inverter circuit is connected to the gate electrode of an N-channel MOS transistor. The operation is further accelerated because the input capacitance is reduced.

[0019]

As described above, according to the present invention, since the input is received by the gate electrode of the MOS transistor, no current flows through the input, and thus there is an effect that a large fan-out can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a level conversion circuit according to an embodiment of the present invention.

FIGS. 2A, 2B, and 2C are output waveform diagrams at each node in the embodiment of FIG.

FIG. 3 is a circuit diagram of another embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional conversion circuit.

5 (A), (B), and (C) are output waveform diagrams at each node in the conventional example of FIG. 4;

[Explanation of symbols]

1 Positive phase input terminal 2 Negative phase input terminal 3,4,7,51,52,53,54,101,10
2,301,302,305,401,402,40
5,502 N-channel MOS transistors 5,6,55,56,57,58,303,304,4
03,404,501 P channel MOS transistor 8 GND terminal 9 Power supply terminal 10 Bias terminal 11 Normal phase output terminal 12 Negative phase output terminal 100,200 Level shift circuit 300,400 Fully differential amplifier 500,600 Inverter circuit

Claims (1)

(57) [Claims] 1. A first input terminal is connected to a first N channel M
A gate electrode of the OS transistor is connected to an input of the first level shift circuit, and a second input terminal is connected to a gate electrode of the second N-channel MOS transistor and an input of the second level shift circuit. A gate electrode of a P-channel MOS transistor is connected to an output of the first level shift circuit, a gate electrode of a second P-channel MOS transistor is connected to an output of the second level shift circuit, Connecting a drain electrode of a channel MOS transistor to a drain electrode of the first P-channel MOS transistor;
Connecting a drain electrode of an OS transistor to a drain electrode of the second P-channel MOS transistor, connecting a drain electrode of a third N-channel MOS transistor to source electrodes of the first and second N-channel MOS transistors, The gate electrode of the third N-channel MOS transistor is connected to a bias terminal, the source electrode is connected to a first power supply terminal, and the source electrodes of the first and second P-channel MOS transistors are connected to a second power supply terminal. And connecting at least two fully differential amplifiers in series,
The first input of the first-stage fully differential amplifier is connected to the first N-channel MOS transistor and the first P-channel MO.
A second input is connected to a connection point of the drain electrode of the S transistor, and a connection point of the drain electrode of the second N-channel MOS transistor and the connection point of the drain electrode of the second P-channel MOS transistor. An output connected to the input of the first inverter circuit, a second output connected to the input of the second inverter circuit, a first output terminal connected to the output of the first inverter circuit, a second output terminal Is connected to the output of the second inverter circuit.