JP2809932B2 - Input buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS input buffer circuit and, more particularly, to a CMOS input buffer circuit having a small amplitude level of an input signal.
High level of input is lower than power supply voltage and low level is CMO
An input signal greater than the threshold voltage of the S inverter
It relates to a device capable of interfacing to a level equal to the MOS amplitude level.

[0002]

FIG. 2 shows a conventional CMOS input buffer circuit. In the figure, reference numeral 27 denotes a power source Vcc (first
Connected to 5V which is the potential of the power supply node of
A transistor (a first conductivity type MOS transistor; hereinafter, referred to as a PMOS Tr) 28 is an N-type transistor whose source is connected to the ground (0 V which is the potential of the second power supply node).
A MOS transistor (a second conductivity type MOS transistor, hereinafter referred to as an NMOS Tr);
The drains of the NMOS transistor 27 and the NMOS transistor 28 are connected to each other.

[0003] Reference numeral 1 denotes an input signal terminal, which is a PMOS.
It is connected to the gates of Tr27 and NMOS Tr28. Reference numeral 29 denotes an output signal terminal.
And the drain of the NMOS Tr28.

Next, the operation will be described. This circuit is
When an input signal from the input signal terminal 1 is a PMOS Tr 27,
When input to the gate of the NMOS Tr 28, a signal whose logic level is inverted is output from the output signal terminal 29.

That is, if the input signal is "H", the PMO
The STr 27 is turned off, the NMOS Tr 28 is turned on, and “L” is output from the output terminal 29. If the input signal is “L”, the PMOS Tr 27 is turned on and the NMOS
r28 is turned off, and "H" is output from the output terminal 29.

[0006]

Since the conventional CMOS input buffer circuit is constructed as described above, the logic amplitude level .DELTA.V of the input signal is small, and the input signal V1 is VDD.
>V1>Vth> 0 (VDD: power supply voltage, Vth: NMOST
When the ECL circuit is driven by a positive power supply, for example, 3.3 V−
When an input signal having a logical amplitude of between 4.1 V is input, both the PMOS Tr and the NMOS Tr are turned on, and the output voltage responds to the power supply voltage level or the ground voltage level even if the input signal swings at ΔV. However, there is a problem that a through current always flows.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. A circuit which can respond as an input signal having an amplitude level of ΔV: VDD>ΔV> 0 and operate as an input buffer circuit is provided. To provide.

[0008]

An input buffer circuit according to the present invention comprises three amplifiers operating at a difference potential between two inputs.
Of the three amplifiers, the front stage of the three amplifiers is configured symmetrically with the two amplifiers, and a signal having the same phase and mutually inverted logic levels is input to two input terminals. A signal whose level has been amplified is obtained at the output terminals of the two sets of amplifiers at the preceding stage, and this signal is further input to the two input terminals of another differentially operating amplifier, so that the output level is changed to the power supply voltage or the ground. The logic amplitude is set between the voltage levels, and the output of the logic circuit makes the transistor of the CMOS inverter respond.

In the input buffer circuit according to the present invention, third to fifth Nch transistors are provided between the three amplifiers and the ground node, respectively, and between the output of the third amplifier and the input of the CMOS inverter. And 2
An input NAND circuit is provided, a control signal is supplied to the gates of the third to fifth transistors, and the control signal is supplied to the other input of the two-input NAND circuit to which the output of the third amplifier is input. Is input.

Further, in the input buffer circuit according to the present invention, third to fifth Pch transistors are provided between the three amplifiers and the ground node, respectively, and between the output of the third amplifier and the input of the CMOS inverter. And 2
An input NAND circuit is provided, a control signal is applied to the gates of the third to fifth transistors, and the control signal is applied to an inverting input of the two-input NAND circuit whose non-inverting input receives the output of the third amplifier. A signal is input.

[0011]

According to the present invention, of the three amplifiers, two sets of symmetrical circuits are provided in the front stage, and two input terminals receive in-phase and inverted signals, so that the outputs of the two sets of amplifiers in the front stage are output. By amplifying the level of the terminal and inputting it to the two input terminals of another differentially operating amplifier, the output level is made to swing to the power supply voltage or the ground voltage level so that the final-stage buffer circuit responds. .

Further, in the present invention, third to fifth Nch transistors are provided between the three amplifiers and the ground node, and a two-input NAND is provided between the output of the third amplifier and the input of the CMOS inverter. Circuit,
Since the third to fifth transistors and the two-input NAND circuit are controlled by a common control signal, it is possible to prevent a through current from flowing when operation is unnecessary.

Further, in the present invention, third to fifth Pch transistors are provided between the three amplifiers and the ground node, and the output of the third amplifier is connected to the CMOS.
A two-input NAND circuit is provided between the input of the inverter and the third to fifth transistors and the two-input NAN.
Since the inverting input of the D circuit is controlled by the common control signal, it is possible to prevent a through current from flowing when operation is unnecessary.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an input buffer circuit device according to one embodiment of the present invention. In the figures, the same reference numerals and symbols as those in the conventional example indicate the same or corresponding parts, and a description thereof will be omitted.

Reference numeral 2 denotes the same input terminal as the input terminal 1, but a signal having the same phase and a mutually inverted logic level is inputted. Reference numerals 3, 4 and 6, 5 denote a pair of NMOS Trs as first and second MOS transistors of the second conductivity type, respectively, which receive a differential potential of an input signal input from the input terminals 1 and 2, The sources are commonly connected and connected to a ground node via transistors 21 and 22 described later. 7, 8 and 9, 10 are NMO
PMOS as first and second MOS transistors of the first conductivity type, which load STr3, 4, and 5, 6
Tr, whose source is commonly connected and connected to the power supply node, and whose drain is
The gates of the transistors 7, 3 and 9, 5 are connected to the drains of the transistors 4, 5, and 6, respectively, and the gates thereof are connected to each other.

The transistors 3, 4, 7,.
8 and 21, the amplifier 25a as the first amplifier is
The transistors 5, 6, 9, 10, and 22 form an amplifier 25 b as a second amplifier.

Also, 11 and 12 are amplifiers 2 respectively.
1st and 2nd of the second conductivity type receiving differential potentials of input signals input from output terminals 16 and 18 of 5a and 25b.
Are connected in common and connected to a ground node via a transistor 23 described later. Reference numerals 13 and 14 denote PMOS Trs as first conductivity type first and second MOS transistors serving as loads on the NMOS Trs 11 and 12, the sources of which are connected in common and connected to a power supply node, and the drains of which are transistors. Connected to the drains of 11 and 12, respectively;
And the gates thereof are connected in common, and the transistors 13,
11 common drains.

The above-described transistors 11, 12, 1
The amplifier 25 as a third amplifier is provided by 3, 14, and 23.
c is configured.

The first amplifier 25a and the second amplifier 25a
Of the amplifier 25b and the third amplifier 25c.
3V-4.1V is set as a logic amplitude, and the amplitudes of a pair of input signals having the same phase and mutually inverted logic levels are amplified, and the CM is amplified.
An amplitude amplifying circuit 25 for converting the signal into an OS level signal is configured.

This is, as described above, the first amplifier 25
a and a second amplifier 25b receive the pair of input signals in a symmetrical manner, differentially amplify the amplified outputs of the first and second amplifiers 25a and 25b by the third amplifier 25c, and amplify the amplitude of the amplified signals by CMOS. The output is output to a buffer circuit 30 described later.

Reference numeral 30 denotes a PMOS Tr27 and an NMOS Tr27.
And a buffer circuit (CMOS inverter) composed of a transistor Tr28.

Reference numeral 26 denotes the buffer circuit 30 and the amplifier 25
c, a two-input NAND circuit having one input connected to the output terminal 20 of the amplifier 25c and the other input connected to the control signal terminal 24 together with the gates of the transistors 21, 22, and 23. .

Since the gates and the drains of the PMOS Trs 7, 9, and 13 are respectively connected, the PMOS Trs 7, 9, and 13 are connected to each other.
8, 9, 10, 13, and 14 each operate as a constant current source. In addition, NMOS Trs 3, 4, 5, 6, 11, 1
NMOS Trs 21, 22, 23 connected to the source of
When a high-level (second power supply potential) control signal is supplied to the control signal terminal 24, the amplifier operates as an amplifier.

Next, the operation will be described. The NMOS Trs 4, 6 of the amplifiers 25a, 25b configured as described above.
Output terminals 16 and 18 from the drain of the NMOS
11, 12, and 23 and the PMOS Trs 13 and 14 are connected to the NMOS Trs 11 and 12 of the amplifier 25c configured similarly to the amplifiers 25a and 25b.
That is, the apparatus of the present embodiment includes three sets of amplifiers 25a to 25c.

The NMO of the final stage amplifier 25c
The output terminal 20 from the STr 12 and the control signal terminal 24 are connected to a two-input NAND gate 26, and the output is transmitted to the CMOS buffer circuit 30.

Here, it is assumed that the potential V1 of the input terminal 1 and the potential V2 of the input terminal 2 are given by VDD>V1>V2>Vth> 0. Where VDD is the power supply voltage and Vth is NM
This is the threshold voltage of OSTr.

Then, since the conductivity of the NMOS Tr6 of the amplifier 25b increases and the conductivity of the NMOS Tr4 of the amplifier 25a decreases, the output terminal 16 of the amplifier 25a is at a high level and the output terminal 18 of the amplifier 25b is at a low level. Each change. These two output terminals 16,
The output signal from 18 is the NMOS of the final stage amplifier 25c.
The input is transmitted to Trs 11 and 12, the conductivity of NMOS Tr11 increases, and the conductivity of NMOS Tr11 decreases, whereby output terminal 20 becomes high level and is transmitted to two-input NAND circuit 26.

At this time, since the amplifier is operating, 2
The input NAND circuit 26 goes low, the PMOS Tr 27 of the CMOS buffer circuit becomes conductive, and the NMOS Tr 27
28 is in a non-conductive state, and a voltage substantially at the power supply voltage level appears at the output terminal 29 as an output signal.

On the other hand, when the relationship between the voltages at the input terminals 1 and 2 is VDD>V2>V1>Vth> 0, a voltage substantially at the ground level appears at the output terminal 29 as an output signal.

When the output signal of the input buffer circuit is unnecessary, a voltage of the ground level is input to the control signal terminal 24, so that the amplifier becomes inactive and the input signal is turned off.
The output of the input NAND is fixed to the power supply voltage, and the output terminal 2
9 is fixed to the ground level. Therefore, it is possible to prevent a through current from flowing.

As described above, according to the above-described embodiment, the logical amplitude level ΔV is applied to the two input terminals of the two amplifiers preceding the amplifier, which are constituted by the two amplifiers and the one subsequent amplifier. , V DD> V 1, V 2>Vth> 0 when ΔV
= | V1-V2 | (△ V is the amplitude level), when the input signals having a small amplitude are inputted as a pair of input signals having the same phase and mutually inverted, the output terminals thereof become high level, respectively. Then, the voltage changes to a low level, and the amplifier at the subsequent stage further amplifies the voltage to a higher or lower level, so that the output terminal of the buffer circuit can output the power supply voltage level and the ground level.

Further, according to the above embodiment, the NMOS transistor is connected between the pair of NMOS Trs constituting each amplifier and the ground terminal.
Tr and the output of the last stage amplifier and CMO
A two-input NAND circuit is provided between the S-buffer circuit and
When the operation of the circuit is necessary, these are driven by the control signal. By setting the control signal to "L" level, the voltage of the output terminal can be fixed to the ground level and the flow of through current can be prevented. Therefore, there is an effect that the power consumption of the circuit can be reduced.

FIG. 3 shows an input buffer circuit according to another embodiment of the present invention. This embodiment is similar to the NMO of the embodiment of FIG.
PMOS transistors 31, 32, and 33 are provided in place of the S transistors 21, 22, and 23, and the output of the amplifier 25c is received by a non-inverting input instead of the two-input NAND inverter 26 that inputs a non-inverting signal. , 32, 33 receiving a control signal to be input to the gates of inverted, inverting input.
Is provided.

According to this embodiment, a PMOS Tr is provided between a pair of NMOS Trs constituting each amplifier and a ground terminal, and a two-input NAND circuit is provided between the output of the final stage amplifier and the CMOS buffer circuit. When the operation of the circuit is required, these are driven by the control signal. Therefore, by setting the control signal to “H” level, the voltage of the output terminal can be fixed to the ground level, and the through current flows. And the power consumption of the circuit can be reduced.

[0035]

As described above, according to the input buffer circuit of the present invention, the first and second MOs of the second conductivity type are provided.
The sources of the S transistors are commonly connected to each other and connected to a second power supply node, and the sources of the first conductivity type first and second MOS transistors are commonly connected to each other and connected to the first power supply node. The drain is commonly connected to the drains of the first and second MOS transistors of the second conductivity type, and their gates are commonly connected to form a common drain of the first MOS transistor of the first and second conductivity types. , The gates of the first and second MOS transistors of the second conductivity type are used as first and second inputs, and the common drain of the second MOS transistor of the first and second conductivity types is used as an output. Prepare three amplifiers, the first one of the first amplifier
A signal having the same phase and a mutually inverted logic level is input to the second input and the second and first inputs of the second amplifier, and the amplified outputs of the first and second amplifiers are connected to the third amplifier of the third amplifier. 1, input to the second input and set the logical amplitude of the first and second inputs to CM
An amplitude amplification circuit that expands to the OS level;
Is input to the CMOS inverter, so that signals having small logical amplitudes input to the first and second amplifiers can be sequentially amplified, and the logical amplitude between the first and second power supply potentials is equal to the logical amplitude. Can be output from the CMOS inverter.

Further, according to the input buffer circuit of the present invention, the first and second MOS transistors of the second conductivity type forming the first to third amplifiers are connected between the second power supply node and the second power supply node. Two-conductivity third to fifth NMOS transistors are provided, and the output of the third amplifier and the CMOS
A two-input NAND circuit is provided between the inverter and the third to fifth MOS transistors and the two-input NAN.
Since the D circuit is turned off when it is not operated by the control signal, the voltage of the output terminal can be fixed at the second power supply potential level by setting the control signal to the “L” level, and a through current can be prevented. Power consumption can be reduced.

Further, according to the input buffer circuit of the present invention, the first and second MOS transistors of the second conductivity type forming the first to third amplifiers are connected between the second power supply node and the second power supply node. A third to fifth PMOS transistors of two conductivity type are provided, and the output of the third amplifier and the CMO
A two-input NAND circuit is provided between the S inverter and
The third to fifth MOS transistors and the two-input NA
Since the ND circuit is turned off during non-operation by the control signal, the voltage of the output terminal can be fixed at the second power supply potential level by setting the control signal to the "L" level, and a through current can be prevented. Power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an input buffer circuit according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating a conventional input buffer circuit.

FIG. 3 is a circuit diagram showing an input buffer circuit according to another embodiment of the present invention.

[Explanation of symbols]

1, 2, input terminal 29 output terminal 3, 4, 5, 6, 11, 12, 21, 22, 23 NM
OS transistor 7, 8, 9, 10, 13, 14, 31, 32, 33 P
MOS transistor 25 Amplitude amplifier circuit 25a, 25b, 25c Amplifier 26, 36 2-input NAND inverter 30 Buffer circuit

Claims (3)

(57) [Claims] A first conductive type first and second MOS transistor having their sources connected to each other and connected to a first power supply node; and their sources connected to each other and connected to a second power supply node. First and second MOS transistors of the second conductivity type connected to each other, wherein the gates of the first and second MOS transistors of the first conductivity type are connected together and the first and second MOS transistors of the first conductivity type are connected to each other. And the drains of the first and second MOS transistors of the first conductivity type and the first and second MOS transistors of the second conductivity type are connected in common, respectively. First and second input nodes are connected to the gates of the first and second MOS transistors, respectively, of the first and second MOS transistors; MOS
The transistor includes first to third amplifiers each having an output node connected to a drain commonly connected to the transistors. The first and second input nodes of the first amplifier have low amplitude levels and have low amplitude levels. The first and second input signals whose first level is lower than the potential of the first power supply node and whose second level is higher than the threshold value of the CMOS inverter and whose signal levels are in phase with each other and inverted mutually are shown. The second and first input signals are respectively input to the first and second input nodes of the second amplifier, and the first and second input nodes of the third amplifier are respectively input to the first and second input nodes of the third amplifier. Is connected to output nodes of the first and second amplifiers, respectively, and an amplitude amplifier circuit for expanding the logical amplitude of the first and second input signals to a CMOS level; and inverting an output of the amplitude amplifier circuit. did, Serial first and second
And a CMOS inverter that outputs a signal having a logical amplitude between the potentials of the power supply nodes. 2. A power supply according to claim 1, wherein said first and second MOS transistors of said second conductivity type are connected to a common source and a second power supply potential. Third to fifth MOS transistors of the second conductivity type are provided; a two-input NAND gate circuit is provided between an output node of the third amplifier and an input node of the CMOS inverter; The gate of the MOS transistor No. 5 is connected to a control signal. One input of the two-input NAND circuit is connected to the output signal of the third amplifier, and the other input is connected to the control signal. 2. The input buffer circuit according to claim 1, wherein a through current is controlled by a control signal when operation is unnecessary. 3. A method according to claim 1, wherein said first and second MOS transistors of said second conductivity type, which constitute said first to third amplifiers, are connected between a commonly connected source and a second power supply potential. Third to fifth MOS transistors of the first conductivity type are provided, and between the output node of the third amplifier and the input node of the CMOS inverter, two inputs, one of which is a non-inverting input and the other is an inverting input. A NAND gate circuit is provided, and the gates of the third to fifth MOS transistors are connected to a control signal. The non-inverting input of the two-input NAND circuit is connected to the output signal of the third amplifier and inverted. 2. The input buffer circuit according to claim 1, wherein the input is connected to the control signal, and the control signal controls the through current when the operation is unnecessary.