JP4672883B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a CMOS output circuit.
[0002]
[Prior art]
An operational amplifier in an electronic device is provided with an output stage for driving an additional device connected to the amplifier in a specific application. In order to suit a wide range of applications, it is preferable to provide such output stages with various features such as relatively large and symmetrical output swings, preferably rail-to-rail. It is also desirable to have an output that can supply and sink a significant amount of current to drive a load having a significant capacity. Furthermore, the output should consume relatively low static power and minimize power consumption when such loads are not driven. Obviously, other features such as stability and manufacturability are also important considerations.
[0003]
Most prior art output stages that can operate at 1 volt are push-pull class A output stages. In this case, the pull-up device or pull-down device is a current source, and the other devices are configured in a source ground configuration. As a result, the power loss in driving a large output load becomes a high level.
[0004]
Class AB stages are often used to minimize power loss in the output stage. Such a stage has a relatively low quiescent power loss, but can still drive large amounts of current.
[0005]
In bipolar technology, the low voltage push-pull output stage generally relies on control of the base current drive to the output transistor. Since bipolar transistors are current driven devices, the output current of the device can be controlled when the base is driven by a controlled current source. Since the collector current exponentially depends on the base-emitter voltage, a large change in the output current can be realized with a small change in the base-emitter voltage. Thus, in a bipolar design that can operate at 1 volt, the circuit can be designed to control the base current drive of the device and still achieve high output current. However, in CMOS circuits, the amount of output current is strictly a function of the amount of voltage (V _GS ) between the gate and source of the device, so such a technique is not effective.
[0006]
CMOS push-pull output stages are generally designed so that one transistor is driven directly from the input of the output stage and complementary transistors are driven by an output circuit network. However, conventional CMOS output circuits are problematic in that conventional CMOS output circuit networks may or may not drive complementary transistors that are strong enough to produce symmetric outputs. This problem becomes even greater at low voltages such as 1 volt.
[0007]
FIG. 1 (Prior Art) is a schematic diagram of a conventional CMOS output stage 100. The conventional output stage 100 includes a P-channel transistor 102 and an N-channel transistor 104 set in a push-pull configuration. The output stage 100 further includes a P-channel transistor 106, N-channel transistors 108, 110, and 112, and a current source 114.
[0008]
The conventional output stage 100 is an example of a 1V CMOS push-pull output stage. In essence, the drain of P-channel transistor 102 and N-channel transistor 104 are connected together. Further, the source of the P-channel transistor 102 is connected to the positive power supply _Vcc , while the source of the N-channel transistor 104 is connected to the negative power supply _VEE . In this manner, the conventional output stage 100 achieves near-to-rail performance until a load is placed at the output.
[0009]
[Problems to be solved by the invention]
To provide negative drive capability, the conventional output stage 100 must operate at a high static current. The current source 114 sets the maximum sink current capability of the output stage along with the area ratio of the NMOS transistors 108 and 104. The output sink current in NMOS 104 is controlled by replica PMOS transistor 106 that controls the bias to NMOS transistors 110 and 112. The NMOS 110 then modulates the bias to the output NMOS 104. The output drive capability of the circuit 100 is not symmetrical because the drain current in the PMOS 102 is limited only by its V _GS , while the NMOS ₁₀₄ has I ₁₁₄ ((W / L ₁₀₄ ) / (W / L ₁₀₈ )). Can only carry. This limits the types of application circuits that function correctly with the output stage 100.
[0010]
In view of the above, what is needed is an output stage that provides approximately rail-to-rail performance and does not require high static currents to provide negative drive capability. Furthermore, the output stage should be able to operate from a low supply voltage, such as a voltage slightly higher than a single V _GS voltage.
[0011]
[Means for Solving the Problems]
The present invention addresses this need by providing an output stage that provides rail-to-rail performance in nature and operates from a supply voltage that is lowered to a voltage slightly higher than a single V _GS voltage. Is.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
In one embodiment, an output stage suitable for low voltage operation and capable of providing an essentially contrasting rail-to-rail output voltage is disclosed. The output stage includes a first field effect device having a first source connected to a first drain, a first gate, and a power supply V _CC . The output stage is complementary to the first field effect device and includes a second drain, a second gate, and a second source connected to a power supply having a nominal voltage V _EE . It further includes a field effect device. Further, the second drain is connected to the first drain. The output stage includes an output sink circuit connected to the second field effect device. The output sink circuit drives the second field effect device such that the product of the current in the first field effect device and the current in the second field effect device is approximately equal to a predetermined constant during operation of the output stage. To do.
[0013]
In another embodiment, a method for providing an output signal from an output stage of a low voltage amplifier capable of providing a substantially rail-to-rail output voltage is disclosed. The method includes providing an input signal to a first field effect device having a first source connected to a first drain, a first gate, and a power supply V _CC . The output sink circuit is then utilized to complement the product of the current in the first field effect device and the current in the second field effect device so that they are approximately equal to a predetermined constant during operation of the amplifier. The second field effect device is driven.
[0014]
In yet another embodiment, an application specific integrated circuit (ASIC) comprising an output stage for a low voltage operational amplifier is disclosed. The ASIC includes a first field effect device having a first drain, a first gate, and a first source connected to a power supply V _CC . The ASIC further includes a second source that is complementary to the first field effect device and connected to a power source having a second drain, a second gate, and a nominal voltage V _EE . Further, the second drain is connected to the first drain. The output stage includes an output sink circuit connected to the second field effect device. The output sink circuit drives the second field effect device such that the product of the current in the first field effect device and the current in the second field effect device is approximately equal to a predetermined constant during operation of the output stage. To do.
[0015]
An operational amplifier output stage is disclosed in a further embodiment of the invention. The operational amplifier output stage comprises a push-pull output circuit that receives a first input signal and a second input signal, where the first input signal is provided by the input signal V _IN . The operational amplifier output stage is provided with an output sink circuit that provides the second input signal to the push-pull output circuit.
[0016]
Finally, an operational amplifier suitable for operation at low input voltages and capable of providing a substantially symmetrical rail-to-rail output voltage is disclosed. The operational amplifier includes an input stage and an output stage connected to the input stage. Furthermore, the output stage comprises an output sink circuit network.
[0017]
Advantageously, the present invention provides intrinsic rail-to-rail performance and does not require high static currents to provide negative drive capability. Furthermore, the output stage of the present invention can operate from a supply voltage as low as slightly higher than a single V _GS voltage.
[0018]
【Example】
An invention is disclosed that achieves an essentially symmetric rail-to-rail performance and provides an output stage that can operate with a power supply slightly higher than a single V _GS voltage. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, one skilled in the art will understand that the invention may be practiced without all or some of these specific details. In other instances, well known process steps have not been described in detail in order not to unnecessarily obscure the present invention.
[0019]
FIG. 1 has been described with respect to the prior art. FIG. 2 is a block diagram illustrating an operational amplifier 200 according to one embodiment of the present invention. The operational amplifier 200 includes an input stage 202 and an output stage 204.
[0020]
In operation, input stage 202 receives differential input signal V _IN . Next, input stage 202 converts the differential input signal to a single output stage input signal and then provides the output stage input signal to output stage 204. The output stage 204 receives the output stage input signal and converts it to an amplified output voltage V _O.
[0021]
The output stage 204 inherently provides rail-to-rail performance and can be operated with a power supply as low as approximately a single V _GS voltage. As will be described in more detail below, output stage 204 utilizes an output sink circuit to achieve this functionality.
[0022]
FIG. 3 is a block diagram of output stage 204 according to one embodiment of the invention. The output stage 204 includes a push-pull output 300 and an output sink circuit 302. In use, push-pull output 300 receives two input signals. One signal is received from the source V _IN and the other signal is received from the output sink circuit 302.
[0023]
As shown in FIG. 3, one side of the push-pull output 300 is driven directly by the source signal V _IN while the other side is controlled by the output sink circuit 302. The result is an output stage 204 that provides a symmetric rail-to-rail output when driven at 1 volt.
[0024]
Turning now to FIG. 4, an output stage 400 according to one embodiment of the present invention is shown. The output stage 400 includes an output sink circuit 302 and a push-pull output 300 that includes a P-channel transistor 402 and an N-channel transistor 404. The source of P-channel transistor 402 is connected to V _CC while the source of N-channel transistor 404 is connected to V _EE . Finally, the drains of both P-channel transistor 402 and N-channel transistor 404 are connected together.
[0025]
In use, P-channel transistor 402 is driven directly by source voltage V _IN while N-channel transistor 404 is driven by output sink circuit 302. In order to provide a push-pull output, the current in P-channel transistor 402 and N-channel transistor 404 is always equal to a constant when multiplied together.
[0026]
Thus, the present invention provides an output sink circuit so that the P-channel transistor 402 is driven directly using the source voltage V _IN and the product of the current in the P-channel transistor 402 and the N-channel transistor 404 is always equal to a predetermined constant. Is used to drive the N-channel transistor. In other words, as the current in the P-channel transistor 402 increases, the current in the N-channel transistor 404 decreases and vice versa. One skilled in the art will recognize that a similar approach is to connect the voltage V _IN to the gate of NMOS transistor 404 and cause the output source circuit to drive PMOS 402.
[0027]
FIG. 5 is a schematic diagram of an output stage 500 in accordance with an aspect of the present invention. The output stage 500 includes a push-pull output 300 having a P-channel transistor 402 and an N-channel transistor 404, an output sink circuit 302, and P-channel transistors 502, 504, and 506.
[0028]
P-channel transistor 402 is configured in a common source configuration. P-channel transistor 502 is configured to replicate P-channel transistor 402 to track the current in transistor 402 to a predetermined ratio, such as 6: 1. Therefore, the P-channel transistor 402 has a current that is six times that of the P-channel transistor 502. This current is then sent to output sink circuit 302 to provide a constant product of the above-described currents of transistors 402 and 404 as will be described in more detail below.
[0029]
The output sink circuit 302 includes a loop of the V _GS voltage. Starting from the left side of FIG. 5, N-channel transistor 508 is connected to a diode connection that provides one V _GS , and diode 510 provides a voltage change for one diode to node n6. N-channel transistor 508 and diode 510 both have a current I. Thus node n6 is essentially a bias node with one V _GS and one diode drop. Next, there is one V _GS drop from the gate to the source of N-channel transistor 512 at node n6. N-channel transistor 514 provides one V _GS rise from the source to the gate to node n13. Next, one diode drop from diode 516. Finally, N-channel transistor 404 provides one V _GS drop.
[0030]
Therefore, when passing through the loop of the V _GS voltage, the V _GS of the N-channel transistor 508, the diode drop of the diode 510 is added, subtracted V _GS of the N-channel transistor 512, the V _GS of the N-channel transistor 514 is added, the diode Subtract 516 diode drops and subtract V _GS of N-channel transistor 404, all of which are equal to zero, as described in the equation below.
[0031]
(1) (I _{P / 3} -I) / (W / L ₅₁₂ ) = I _D512
(2) I _D = I _D0 (W / L) exp (V ₈₈ / nV _T ) exp (−V _S / V _T ) −exp (−V _d / V _T )
(3) nV _{T In} (I / (I _D0 (W / L ₅₀₈ )) + V _{T In} (I / I _S ) −nV _{T In} ((I _{P / 3} −I) / (I _D0 (W / L ₅₁₂ ))) + NV _T ln (2I / (I _D0 (W / L ₅₁₄ ))) − V _T ln (2I / 2I _s ) −nV _T ln (I _N / (I _D0 (W / L ₄₀₄ ))) = 0
(4) 2I ² / ((W / L ₅₀₈ ) (W / L ₅₁₄ )) = ((I _{P / 3} −I) (I _N )) / ((W / L ₅₁₂ ) (W / L ₄₀₄ ))
K ₁ ? ((I _P ) (I _N )) / (K ₂ )-> Push pull action At the zero input point, I _P = I _N = I _Q
In the above equation, it is assumed that all MOSFETs operate in the subthreshold region. To calculate the quiescent current I _Q can be used the following equation.
[0032]
(5) (2I ² ) / ((W / L ₅₀₈ ) (W / L ₅₁₄ )) = ((1/3) (I _Q ² ) − (I _Q ) (I) / ((W / L ₅₁₂ ) (W / L ₄₀₄ ))
-> (1/3) (I _Q ² )-(I _Q ) (I)-(2I ² ) / (((W / L ₅₁₂ ) (W / L ₄₀₄ )) / ((W / L ₅₀₈ ) (W / L ₅₁₄ ))) = 0
This can be solved using a quadratic equation.
[0033]
Similar equations can be derived for MOSFETs operating at saturation. In essence, in saturation
(1) I _N + I _P = K
In the formula, K is a constant value.
[0034]
As can be seen from the above equation, diodes 510 and 516 cancel each other. The main purpose of this is to generate current so that the current source can operate by generating voltage at the sources of N-channel transistors 512 and 514 at node n10. In alternative embodiments, diodes 510 and 516 may be replaced with resistors that perform essentially the same function.
[0035]
Referring to equation (3) above, twice the I ² set by N-channel transistors 506 and 504 divided by the size of N-channel transistors 508 and 514 is the current in P-channel transistor 402 I _P Is multiplied by I _N , the current in N-channel transistor 404, divided by 3 derived from the ratio of transistors 402, 502, 520, and 522, and multiplied by the size of transistors 402 and 404. equal. Thus, a symmetric rail-to-rail push-pull output is achieved.
[0036]
In use, the output stage 500 is connected to the output of the input stage and the P-channel device is directly connected, as shown in FIG. The output sink circuit 302 determines how to bias the output N-channel transistor 404 so that a push-pull output is achieved.
[0037]
In the present invention, there is only one V _GS plus two V _Dsat between both rails. Thus, the present invention operates at less than 1 volt.
[0038]
Further, unlike the conventional output stage, the present invention can drive the gate voltage of the N-channel transistor 404 to approximately V _CC . For example, when the transistor 402 is turned off, the gate voltage of the transistor 402 becomes close to V _CC , so that the current in the transistor 502 is reduced. However, transistor 504 is biased with 2I while transistor 518 is biased with I. For this reason, the voltage at the gate of transistor 404 increases to the saturation voltage of transistor 504 plus the diode drop of diode 516. Thus, when the amplifier is open loop (ie, the differential input voltage is large), if the output is driven very strongly, the voltage at the gate of transistor 404 will increase dramatically and thereby be very good Provides output drive.
[0039]
Again, the output stage 500 has been described with an output sink circuit to control the NMOS 404, but an alternative approach is to drive the PMOS 402 using an output source circuit similar to the circuit 302 and pull the NMOS 404 from the input V _IN. Note that it is driven directly.
[0040]
Although the invention has been described with reference to several preferred embodiments, there are many alternatives, modifications, and equivalents that may be within the scope of the invention. It should also be noted that there are many alternative methods and apparatus of the present invention. Accordingly, the claims appended hereto are intended to be construed to include all such alternatives, modifications and equivalents that are within the spirit and scope of the invention.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of a conventional output stage.
FIG. 2 is a block diagram illustrating an operational amplifier according to an embodiment of the present invention.
FIG. 3 is a block diagram of an output stage according to an embodiment of the present invention.
FIG. 4 is a schematic diagram of an output stage in accordance with an aspect of the present invention.
FIG. 5 is a schematic diagram of an output stage according to another aspect of the present invention.
[Explanation of symbols]
100 CMOS output stage 102, 402, 502, 504, 506 P-channel transistors 104, 108, 110, 112, 404, 504, 506, 508, 512, 514 N-channel transistor 114 Current source 200 Operational amplifier 202 Input stage 204 Output stage 300 Push-pull output 302 Output sink circuit 400, 500 Output stage 510, 516 Diode

Claims (1)

A semiconductor device having a CMOS output circuit that outputs a substantially symmetrical rail-to-rail output voltage to an output terminal based on a voltage input to an input terminal ,
A first field effect device having a drain connected to the output terminal, a gate connected to the input terminal, and a source connected to a power supply V _CC ;
An output stage comprising: a second field effect device complementary to the first field effect device, having a drain connected to the output terminal and a source connected to a power supply _VEE ;
Is connected to the gate of the second field effect device, the sum of the current in the first current and the second field effect device in the field effect device, during operation of the output stage is substantially equal to a predetermined constant as such, Bei example and an output sink circuit for driving the second field effect device,
The output sink circuit is
A third field effect device having a gate connected to the input terminal and the gate of the first field effect device and a source connected to a power supply V _CC ;
A current mirror circuit having an input terminal connected to the drain of the third field effect device;
A first current source connected in series between a power supply V _CC and a power supply V _EE, a first diode, and a diode-connected fourth field effect device;
A fifth field effect device having a gate connected to a connection node of the first current source and the first diode, and a drain connected to a power supply V _CC ;
A sixth field effect device having a drain connected to a source of the fifth field effect device and a source connected to a power supply _VEE ;
A second current source, a second diode, and a diode-connected first connected in series between the power source V _CC and the connection node of the drain of the sixth field effect device and the other terminal of the current mirror circuit 7 field effect devices,
A connection node of the second diode and the drain of the seventh field effect device is connected to a gate of the second field effect device;
A semiconductor device.

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