JPH1127062A - Differential amplifier and operational amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential amplifier having its extended range of input voltage and also to provide an operational amplifier which can obtain its normal output. SOLUTION: A differential amplifier 10 has an input stage 1 and an output stage 2. The stage 2 includes a bias stage 3 which shifts the level of output voltage of a 1st NOMS 4 of the amplifier 10 and biases the input voltage of 4th and 5th PMOS 7 and 8. In such a constitution, the voltage drop of the stage 2 can be minimized and the range of input voltage that can be supplied to the stage 1 is extended up to the power voltage Vdd+. An operational amplifier 40 has a level shift stage 20 which shifts the level of and outputs the output voltage of a 2nd NOMS 5 of the amplifier 10 at the next stage of the amplifier 10, and an output buffer stage 30 which outputs the output voltage of the stage 20 to the outside. Thus, the stage 30 operates to obtain the normal output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier and an operational amplifier used in a semiconductor integrated circuit, and more particularly, to expanding the input voltage range of the differential amplifier and normalizing the output of the operational amplifier. Regarding what you can get.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, as a means for amplifying an input signal, for example, a differential amplifier composed of a complementary MOS transistor (hereinafter referred to as CMOS), a bipolar transistor or the like is used. As a differential amplifier, there is known a COMS type differential amplifier having a very small temperature drift and a high operation speed.

FIG. 3 is a block diagram showing a conventional general COMS type differential amplifier 100. As shown in FIG. Differential amplifier 100
Is the power supply voltage V _dd + (for example, 5.0 V) and the ground potential (G
ND), and is configured to perform differential amplification according to the difference between the input voltages supplied from the positive-phase input terminal Vin + and the negative-phase input terminal Vin− and output the result to the node N1. .

[0006] The differential amplifier circuit 100 mainly includes an input stage 101 and an output stage 102. The input stage 101
It comprises first and second N-channel MOS transistors (hereinafter referred to as NMOS) 103 and 104 for input and a third NMOS 105 for constant current source. The output stage 102 includes fourth and fifth P-channel transistors (hereinafter, referred to as PMOS) 106, 1 for an active load.
07.

In the input stage 101, the first NMOS 1
03 is connected to the positive-phase input terminal Vin +, and the gate of the second NMOS 104 is connected to the negative-phase input terminal Vin−.
And the first and second NMOSs 103 and 104
Is a differential pair in the differential amplifier 100. The gate of the third NMOS105 is connected to a bias voltage V _bb, drain, first and second NMOS 103,
The drain is connected in common to the drain 104, and the source is connected to the ground potential.

In the output stage 102, the gates of the fourth and fifth PMOSs 106 and 107 are connected to the node N2.
And the drain of the fourth PMOS 106 is connected to the drain of the first NMOS 103 via the node N2, and the drain of the fifth PMOS 107 is connected to the node N2.
The source of each of the fourth and fifth PMOSs 106 and 107 is connected to the power supply voltage V _dd + via the first NMOS 1 and the drain of the second NMOS 104. The fourth and fifth PMOSs 106 and 107 are configured as so-called current mirror circuits, and are configured so that the fourth and fifth PMOSs 106 and 107 are turned on and off by the voltage of the node N2.

The differential amplifier 100 configured as described above
, The positive-phase input terminal Vin + and the negative-phase input terminal Vi
When an input voltage is supplied from n− to the first and second NMOSs 103 and 104, the input voltage is differentially amplified by the differential amplifier 100 and output to the node N1.

[0008]

In the conventional differential amplifier 100, the fourth and fifth PMOS transistors 10
6 and 107 are turned on, the fourth and fifth PMOSs 106 and 107 are connected to the first and second NMOSs 1 and 2, respectively.
03 and 104 each function as a load transistor to cause a voltage drop. First NMOS 103
From the power supply voltage V _dd + to the fourth PMO
The voltage becomes lower by the voltage drop of S106, and
Of the drain of the NMOS 104 is the power supply voltage V _dd +
To a voltage lower by the voltage drop of the fourth PMOS 106. Further, the fourth and fifth PMOSs 106 and 107
However, in order to perform a normal ON operation, the fourth and fifth P
It is necessary that the voltage between the gate and the source of each of the MOS transistors 106 and 107 be at least about a threshold voltage V _th (for example, 0.8 V). That is, the fourth and fifth PMOSs 106 and 10
When the voltage of the gate 7 becomes lower than the power supply voltage _Vdd + by the threshold voltage _Vth (for example, 4.2 V), the fourth and fifth PMOSs 106 and 107 operate normally. Here, the first and second NMOSs 10
When an input voltage is supplied to each of the gates 3 and 104, the first and second NMOSs 103 and 104 are turned on, and the voltage of the node N2 drops. And the node N2
From the power supply voltage V _dd + to the threshold voltage V _th
When the voltage becomes lower by the amount, the fourth and fifth PMOSs 10
6 and 107 are connected to the node N2, the voltage of each gate of the fourth and fifth PMOSs 106 and 107 is changed from the power supply voltage _Vdd + to the threshold voltage _Vdd +.
_th and the fourth and fifth PMOS 10
6 and 107 are both turned on.

However, the voltage at the drain of the first NMOS 103 connected to the gate and the drain of the fourth PMOS 106 is reduced at least from the power supply voltage V _dd + to the threshold voltage V _th due to the voltage drop due to the ON operation of the fourth PMOS 106. The voltage becomes lower by the same amount. In this state, in order for the first NMOS 103 to normally turn on, the input voltage supplied to the gate of the first NMOS 103 is slightly lower than the voltage lower than the power supply voltage V _dd + by the threshold voltage V _th. Limited to higher or lower voltages. That is, the power supply voltage V _dd + is, for example, 5.0 V
And the threshold voltage V _th of the fourth PMOS 106
Is 0.8 V, for example, the voltage lower than the power supply voltage V _dd + by the threshold voltage V _th becomes, for example, 4.2 V, and the drain voltage of the first NMOS 103 also becomes, for example, 4.2 V. Here, in a normal transistor, the gate-drain voltage is designed so as to allow a reverse voltage of at most 0.2 V. In the illustrated example, the input voltage of the input voltage that can be supplied to the gate of the first NMOS 103 is set. The maximum value is, for example, up to 4.4V.

Thus, depending on the characteristics of the transistor used for input, the input voltage is limited from the power supply voltage V _dd + to a predetermined voltage, for example, a voltage lower by about 0.6 V to 1.0 V. Usually, the second NMOS 104 includes:
An input voltage having a phase opposite to that of the input voltage supplied to the first NMOS 103 is supplied. Therefore, the range of the input voltage supplied to the first and second NMOSs 103 and 104 is at most the power threshold voltage V _th of the fourth PMOS 106 from the power supply voltage V _dd + due to the voltage drop of the fourth PMOS 106. Just below the lower potential. In particular, for example, when the power supply voltage source V _dd + has a low power supply voltage of, for example, about 1 V, there is a fear that the input voltage cannot be supplied due to a voltage drop by the output stage.

Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a differential amplifier capable of supplying a voltage to an input stage while minimizing a voltage drop due to an output stage. An object of the present invention is to provide a new and improved differential amplifier capable of expanding an input voltage range.

Another object of the present invention is to provide a new and improved operational amplifier capable of obtaining a normal output even when the input voltage range is improved to near the power supply voltage.

[0013]

In order to solve the above-mentioned problems, an invention according to claim 1 is characterized in that first and second input transistors to which an input signal is supplied via each gate, and a gate are provided. An input stage comprising a third transistor for a constant current source connected to a bias voltage, a drain commonly connected to the sources of the input first and second transistors, and a source connected to the ground potential; , Each gate is connected in common, and each drain is connected to the corresponding first and second inputs.
And an output stage composed of active load fourth and fifth transistors each having a source connected to a power supply voltage, and differentially amplifying an input signal input from the input stage. In the differential amplifier outputting from the output stage, a bias stage for level-shifting one output of the differential amplifier to bias the input voltages of the fourth and fifth transistors is provided in the output stage. It is characterized by having been provided.

According to the first aspect of the present invention, one output of the differential amplifier is level-shifted by the bias stage to bias the input voltages of the fourth and fifth transistors. The biased fourth and fifth transistors turn on, and the fourth and fifth transistors function as load transistors with respect to the first and second transistors, respectively, causing a voltage drop. Here, the voltage drops of the fourth and fifth transistors are equal to the fourth and fifth source-drain voltages. Thus, the voltage drop due to the output stage can be minimized.

In the differential amplifier according to the present invention, the bias stage has a gate connected to one output of the differential amplifier and a drain connected to a power supply voltage or a ground potential. And the source is commonly connected to each gate of the fourth and fifth transistors.
Transistor and the gate are connected to the bias voltage,
It is preferable that a drain is commonly connected to each gate of the fourth and fifth transistors, and a seventh transistor for a constant current source whose source is connected to the ground potential is good.

According to the second aspect of the present invention, the sum of the threshold voltage of the sixth transistor and the source-drain voltage of the fourth and fifth transistors is the fourth and fifth.
Operates so as to be equal to the threshold voltage of the transistor.

[0017] The invention of claim 3 is based on claim 1 or 2
And a level shift stage for level-shifting and outputting the other output of the differential amplifier, and an output buffer stage for outputting the output of the level shift stage to the outside. A feature of the present invention is to configure an operational amplifier.

According to the third aspect of the invention, the other output voltage of the differential amplifier, which has risen to the vicinity of the power supply voltage, is level-shifted toward the ground by the level shift stage, and is output to the output buffer stage. , The output buffer stage operates and a normal output can be obtained.

According to a third aspect of the present invention, in the operational amplifier according to the fourth aspect, the level shift stage has a gate connected to the other output of the differential amplifier,
An eighth transistor having a drain connected to the power supply voltage, a gate connected to the bias voltage, a source connected to the ground potential, a drain commonly connected to a source of the eighth transistor, and an output of the level shift stage. And a ninth transistor for a constant current source connected to the second transistor. According to a fifth aspect of the present invention, in the output buffer stage, a gate is connected to an output of the level shift stage, and a source is connected to a power supply voltage.
A tenth transistor having a drain connected to the output terminal; an eleventh transistor for a constant current source having a gate connected to the bias voltage, a source connected to the ground potential, and a drain connected to the drain of the tenth transistor; It is preferable that the transistor is constituted by the following transistors.

[0020]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. In addition,
In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals, and redundant description will be omitted.

(First Embodiment) FIG. 1 is a circuit diagram of a differential amplifier 10 showing an embodiment of the present invention. The differential amplifier circuit 10 mainly includes an input stage 1, an output stage 2, and a bias stage 3, and has an input power supply voltage V _dd + (for example, 5.0 V).
And ground potential (GND). And
The differential amplifier circuit 10 is configured to perform differential amplification according to the difference between the input voltages supplied from the positive-phase input terminal Vin + and the negative-phase input terminal Vin− and output the result to the node N1.

The input stage 1 includes first and second input NMs.
OSs 4 and 5 and a third NMOS 6 for a constant current source. The output stage 2 includes fourth and fifth PMOSs 7 and 8 for an active load. Bias stage 3
The differential amplifier 10 includes a sixth NMOS 9 for level-shifting the output voltage on the first NMOS 4 side and a seventh NMOS 11 for a constant current source.

In the input stage 1, the gate of the first NMOS 4 is connected to the positive-phase input terminal Vin +,
The gate of OS5 is connected to the negative-phase input terminal Vin−,
The first and second NMOSs 4 and 5 form a differential pair in the differential amplifier 10. Here, the first and second NMOSs
The gate-drain voltages of 4 and 5 are designed to be allowed up to, for example, 0.2 V as a reverse voltage. The gate of the third NMOS6 is connected to a bias voltage V _bb, drain, first and second NMOS4,5
, And the source is connected to the ground potential.

In the output stage 2, the fourth and fifth PMOs
The gates of S7 and S8 are commonly connected to the node N3, the drain of the fourth PMOS 7 is connected to the drain of the first NMOS 4, and the drain of the fifth PMOS 8 is connected to the second
, And the fourth and fifth P
The sources of the MOSs 7 and 8 are connected to the power supply voltage V _dd +. The source-drain voltage in the ON state of the fourth and fifth PMOSs 7 and 8 is designed to be, for example, 0.2V.

In the bias stage 3, the sixth NMOS 9
Is connected to the output of the first NMOS 4 side of the differential amplifier 10, the drain is connected to the power supply voltage V _dd +, and the source is commonly connected to the gates of the fourth and fifth PMOSs 7, 8. And is connected to the node N3. The gate of the seventh NMOS11 is connected to a bias voltage V _bb, the drain is connected to the fourth and the gate of the first 5 PMOS7,8 transistor via a node N3, the source is connected to a ground potential Have been. Although the seventh NMOS 11 functions as a constant current source, the seventh NMOS 11 may be replaced with another unit such as a resistor.

The bias stage 3 includes a differential amplifier 10
The level of the output voltage of the first NMOS 4 is shifted in the direction of the ground potential and output to the node N3, and the input voltages of the fourth and fifth PMOSs 7 and 8 are biased. That is, since the gates of the fourth and fifth PMOSs 7 and 8 are connected to the node N3, the fourth and fifth PMOSs 7 and 8 are configured to perform on / off operations at the voltage of the node N3. The voltage of the node N3 is changed from the power supply voltage V _dd + to the fourth and fifth PMOSs 7, 8
A voltage lower by the threshold voltage V _th (for example, 4.
4V), the fourth and fifth PMOSs 7 and 8 are configured to normally turn on. The voltage at the node N3 is lower than the voltage at the node N2 by the threshold voltage _Vth of the sixth NMOS 9, and the voltage at the node N2 is equal to the source-drain voltage of the fourth PMOS 7 from the power supply voltage _Vdd +. Only lower voltage. Therefore, the fourth
And a sixth NM having characteristics different from those of the fifth PMOSs 7 and 8.
The sum of the threshold voltage V _th (for example, 0.6 V) of the OS 9 and the source-drain voltage (for example, 0.2 V) of the fourth PMOS 7 is the threshold voltage V _th (for example, 0 V) of the fourth and fifth PMOSs 7 and 8. .8V).

The operation of the differential amplifier 1 configured as described above will be described.

First, input first and second NMOSs 4 and 4 are input from the positive-phase input terminal Vin + and the negative-phase input terminal Vin−.
The input voltage is supplied to each of the gates of the NMOS transistors 5, and the first and second NMOSs 4, 5 are turned on. First NMOS
4 is in the ON state, the voltage of the node N2 drops. At the same time, the output voltage on the first NMOS 4 side of the differential amplifier 10 is output to the gate of the sixth NMOS 9 via the node N2.

The bias stage 3 uses the sixth NMOS 9 to output the output voltage of the differential amplifier 10 on the first NMOS 4 side.
The level is shifted to the ground direction, and the fourth
And output to the respective gates of the fifth PMOSs 7 and 8. Sixth
Of the NMOS 9 is equal to the threshold voltage V _th (for example, 0.6 V) of the sixth NMOS 9, and the voltage of the node N 3 is changed from the voltage of the node N 2 to the sixth NMOS 9.
Becomes lower by the threshold voltage V _{th of}
As the voltage of the node N2 decreases, the voltage of the node N3 is increased from the power supply voltage V _dd + (for example, 5.0 V) by the threshold voltage V _th of the fourth and fifth PMOSs 7 and 8 (for example, 0.8 V). It becomes a low voltage (for example, 4.2V).
Thus, the bias stage 3 includes the fourth and fifth PMOSs.
7 and 8 are biased, and the fourth and fifth PMOs are biased.
S7 and S8 are turned on. Fourth and fifth Ps in the ON state
The MOSs 7 and 8 function as load transistors for the first and second NMOSs 4 and 5, and cause a voltage drop. Here, the voltage drop of the fourth and fifth PMOSs 7 and 8 becomes equal to the source-drain voltage (for example, 0.2 V) of the fourth and fifth PMOSs 7 and 8. First NMO
The drain voltage of S4 is changed from the power supply voltage V _dd + to the fourth PM
The voltage becomes lower (for example, 4.8 V) by the source-drain voltage of the OS 7, and similarly, the drain voltage of the second NMOS 5 is lower than the power supply voltage V _dd + by the source-drain voltage of the fifth PMOS 8. Voltage.

The gate-drain voltage of the first and second NMOSs 4 and 5 is, for example, 0.2 V as a reverse voltage.
Since the input voltage is designed to be up to V, the input voltage expanded to the power supply voltage V _dd + can be supplied to each gate of the first and second NMOSs 4 and 5.

As described above, according to the differential amplifier 10 of the present embodiment, the ON and OFF operations of the fourth and fifth PMOSs 7 and 8 are performed via the bias stage 3 so that the output stage 2 can be minimized by lowering the power supply voltage V _dd + by the voltage between the source and drain of the fourth and fifth PMOSs 7 and 8. If the source-drain voltages of the fourth and fifth PMOSs 7 and 8 are equal to or less than the reverse voltage allowed in the gate-drain voltage of the first NMOS 4, the first and second NMOSs 4 , 5 can be extended to the power supply voltage V _dd +. Therefore, in a semiconductor integrated circuit operating at a low power supply voltage, by using the differential amplifier of the present invention, the range of the input voltage is expanded to the power supply voltage, and the input voltage cannot be supplied due to the voltage drop by the output stage. The situation is avoided. As a result, a semiconductor integrated circuit operating at a low power supply voltage can be effectively used.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
The schematic configuration of the operational amplifier 40 according to the embodiment is shown. The operational amplifier 40 has a configuration in which a level shift stage 20 and an output buffer stage 30 are provided after the differential amplifier 10. Therefore, the configuration and operation of the differential amplifier 10 are the same as those of the first embodiment described above, and the description thereof will not be repeated.

The level shift stage 20 has a power supply voltage V _dd +
(For example, 5.0 V) and a ground potential, and is mainly constituted by an eighth NMOS 21 and a ninth NMOS 22 for a constant current source. The eighth NMOS 21 gate is
It is connected to the node N1 and its drain is connected to the power supply voltage V _dd +. Here, the threshold voltage V _th of the eighth NMOS 21 is, for example, 0.8V. The ninth
The gate of NMOS22 of is connected to a bias voltage V _bb, the drain is connected to the output of the level shift stage 20 while being commonly connected to the 8 NMOS 21 sources of,
The source is connected to the ground potential.

The output buffer stage 30 comprises a tenth PMOS 31 and an eleventh NMOS 32 for a constant current source connected in series between the power supply voltage V _dd + and the ground potential. The gate of the tenth PMOS 31 is connected to the node N4, the drain is connected to the output terminal 33, and the source is connected to the power supply voltage _Vdd . Here, the threshold voltage V _th of the tenth PMOS 31 is, for example, 0.8
V. The gate of the eleventh NMOS32 is connected to a bias voltage V _bb, drain, of the 10 PMOS 3
2 and the source is connected to the ground potential.

Next, the operation of the operational amplifier 40 configured as described above will be described with reference to FIG.

First, an input voltage is supplied from the positive-phase input terminal Vin + and the negative-phase input terminal Vin−, and the differential amplifier 10
, And is output to the gate of the eighth NMOS 21 of the level shift stage 20 via the node N1. In the level shift stage 20, the power supply voltage V _dd + (for example, 5.0
V), the voltage of the node N1 (for example, 4.
8V) is shifted to the ground direction by the eighth NMOS 21 and the output buffer stage 30 is shifted through the node N4.
To the gate of the tenth PMOS 31. At this time, since the eighth NMOS 21 is turned on, the eighth NMOS 21 is turned on.
The voltage drop of the MOS 21 is equal to the threshold voltage V _th (for example, 0.8 V) of the eighth NMOS 21. Then, the threshold voltage V _th of the eighth NMOS 21 is applied to the gate of the tenth PMOS 31 from the voltage of the node N1.
A voltage (for example, 4.0 V) that is lower by an amount is input. Thus, the input voltage close to the power supply voltage _Vdd + is supplied to the differential amplifier 10, and the voltage of the node N1 and the power supply voltage _Vdd +
_{Even if} the potential difference between the differential amplifier 10 and the _dd + becomes equal to or lower than the threshold voltage V _th (for example, 0.8 V) of the tenth PMOS 31, the output voltage of the differential amplifier 10 is level-shifted by the level shift stage 20, and the Tenth PMOS3 of stage 30
Since the signal is output to the first gate, the gate-source voltage of the tenth PMOS 31 does not become lower than the threshold voltage _Vth , and the tenth PMOS 31 is turned on. Then, when the tenth PMOS 31 is turned on, the output buffer stage 30 is operated, and an output can be normally obtained at the output terminal 23.

As described above, according to the operational amplifier 40 according to the present embodiment, the level shift stage 20 and the output buffer stage 30 are provided after the differential amplifier 10 so that the range of the input voltage can be reduced by the power supply voltage. By expanding to V _dd +, even if the output voltage range of the differential amplifier 10 rises to near the power supply voltage V _dd +, the level shift stage 20
Then, the output voltage of the differential amplifier 10 is level-shifted, and the output buffer stage 30 operates to obtain a normal output. Therefore, in a semiconductor integrated circuit operating at a low power supply voltage, a normal output can be obtained by using the operational amplifier of the present invention. As a result, a semiconductor integrated circuit operating at a low power supply voltage can be effectively used.

Although the preferred embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to such examples. It is clear that a person skilled in the art can conceive various changes or modifications within the scope of the technical idea described in the claims, and those modifications naturally fall within the technical scope of the present invention. It is understood to belong. Various changes or modifications include, for example, the following. (1) The same advantages can be obtained by replacing the MOS transistor shown in the embodiment of the present invention with a bipolar transistor. (2) The ground potential may be the power supply voltage _Vdd- . Also, a circuit configuration in which the power supply voltage V _dd + and the ground potential are replaced in FIG. 1 and the NMOS is replaced with a PMOS and the PMOS is replaced with an NMOS in accordance with the same has substantially the same advantages as those in the above embodiment.

[0039]

As described above, according to the first and second aspects of the present invention, the range of the input voltage of the differential amplifier is extended to the power supply voltage. In the amplifier, a normal output can be obtained even if the range of the input voltage is extended to the vicinity of the power supply voltage. Therefore,
The semiconductor integrated circuit can be effectively used even at a low power supply voltage, and a semiconductor integrated circuit with low power consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a differential amplifier according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an operational amplifier according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional differential amplifier.

[Explanation of symbols]

 Reference Signs List 1 input stage 2 output stage 3 bias stage 9 sixth transistor 10 differential amplifier 11 seventh transistor 20 level shift stage 21 eighth transistor 22 ninth transistor 30 output buffer stage 31 tenth transistor 32 eleventh Transistor 40 Operational amplifier

Claims (5)

[Claims] An input first and second transistor to which an input signal is supplied via each gate, a gate connected to a bias voltage, and a drain connected to the input first and second transistors. An input stage including a third transistor for a constant current source commonly connected to each source and having a source connected to the ground potential; each gate being commonly connected and each drain corresponding to the first and second input sources; An output stage comprising an active load fourth and fifth transistor connected to the power supply voltage, each source being connected to the drain of a second transistor; In a differential amplifier that performs dynamic amplification and outputs from the output stage: one of the outputs of the differential amplifier is level-shifted to the output stage to input the input voltages of the fourth and fifth transistors. A differential amplifier comprising a bias stage for biasing. 2. The bias stage: a gate is connected to one output of the differential amplifier, a drain is connected to a power supply voltage or a ground potential, and a source is common to each gate of the fourth and fifth transistors. A sixth transistor connected; a gate connected to a bias voltage, a drain commonly connected to the gates of the fourth and fifth transistors, and a seventh connected to a ground potential, the source being connected to a ground potential. 2. The transistor of claim 1, further comprising:
4. The differential amplifier according to 1. 3. A stage subsequent to the differential amplifier according to claim 1 or 2, a level shift stage for level-shifting and outputting the other output of the differential amplifier; and an output of the level shift stage to the outside. And an output buffer stage. 4. The level shift stage includes: an eighth transistor having a gate connected to the other output of the differential amplifier and a drain connected to a power supply voltage; a gate connected to a bias voltage, and a drain connected to the bias voltage. 9. A ninth transistor for a constant current source, commonly connected to the source of the eighth transistor, connected to the output of the level shift stage, and having the source connected to the ground potential. An operational amplifier according to claim 1. 5. The output buffer stage includes: a tenth transistor having a gate connected to an output of the level shift stage, a drain connected to an output terminal, and a source connected to a power supply voltage; And the drain is connected to the drain of the tenth transistor;
The operational amplifier according to claim 3, further comprising: an eleventh transistor for a constant current source having a source connected to the ground potential.