JP2550942B2 - CMOS type logic integrated circuit - Google Patents
CMOS type logic integrated circuitInfo
- Publication number
- JP2550942B2 JP2550942B2 JP61083501A JP8350186A JP2550942B2 JP 2550942 B2 JP2550942 B2 JP 2550942B2 JP 61083501 A JP61083501 A JP 61083501A JP 8350186 A JP8350186 A JP 8350186A JP 2550942 B2 JP2550942 B2 JP 2550942B2
- Authority
- JP
- Japan
- Prior art keywords
- channel mos
- transistor
- mos transistor
- power supply
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は同一基板上に構成された２組のCMOSトランジ
スタを同一入力電圧に対して異なる２種の電源電圧で動
作させるCMOS型論理集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention is a CMOS type logic integrated circuit for operating two sets of CMOS transistors formed on the same substrate with two different power supply voltages for the same input voltage. Regarding
従来、この種のCMOS型論理集積回路は、第３図に示す
ように、入力端子10と、ＰチャネルMOSトランジスタ31
とＮチャネルMOSトランジスタ32からなり、入力端子10
と接続され、電源電圧VDD1がＰチャネルMOSトランジス
タ31のソースに接続されている初段のCMOSトランジスタ
と、ＰチャネルMOSトランジスタ34とＮチャネルMOSトラ
ンジスタ35からなり、入力端子10および出力端子15に接
続され、電源電圧VDD2がＰチャネルトランジスタ34のソ
ースに接続されている次段のCMOSトランジスタで構成さ
れている。ここで電源電圧VDD1と電源電圧VDD2の関係
は、VDD1＞VDD2となっているので、論理レベルはVDD1か
らVDD2に変換される。Conventionally, a CMOS type logic integrated circuit of this type has an input terminal 10 and a P channel MOS transistor 31 as shown in FIG.
And N-channel MOS transistor 32, input terminal 10
It is connected to a first stage CMOS transistors supply voltage V DD1 is connected to the source of P-channel MOS transistor 31, a P-channel MOS transistor 34 and N-channel MOS transistor 35, connected to the input terminal 10 and output terminal 15 The power supply voltage V DD2 is composed of the CMOS transistor of the next stage connected to the source of the P-channel transistor 34. Since the relationship between the power supply voltage V DD1 and the power supply voltage V DD2 is V DD1 > V DD2 , the logic level is converted from V DD1 to V DD2 .
上述した従来のCMOS型論理集積回路は、同一基板（Ｎ
基板）上にＰチャネルMOSトランジスタ31および34を作
るため、ＰチャネルMOSトランジスタ31および34のサブ
ストレート電極は同一バイアスとなっており、Ｐチャネ
ルMOSトランジスタ34は高い電源電圧VDD1でバイアスさ
れることになるため、基板バイアス効果により閾値電圧
VTPが変化し、出力電圧が電源電圧VDD2より閾値電圧VTP
の変化した分だけ低くなるという欠点がある。The conventional CMOS type logic integrated circuit described above has the same substrate (N
Since the P-channel MOS transistors 31 and 34 are formed on the substrate), the substrate electrodes of the P-channel MOS transistors 31 and 34 have the same bias, and the P-channel MOS transistor 34 is biased with a high power supply voltage V DD1. Therefore, due to the substrate bias effect, the threshold voltage
V TP changes and the output voltage exceeds the power supply voltage V DD2 and the threshold voltage V TP
There is a drawback that it becomes lower by the changed amount.
本発明のCMOS型論理集積回路は、入力端子にＮ、Ｐチ
ャネルMOSトランジスタのゲートが、ＰチャネルMOSトラ
ンジスタのソースに第１の電源端子が、ＮチャネルMOS
トランジスタのソースにグランドがそれぞれ接続され、
さらにＮ、ＰチャネルMOSトランジスタの共通ドレイン
を出力としたCMOSトランジスタと、 前記CMOSトランジスタの前記出力にゲートが、第２の
電源端子にドレインが、出力端子にソースがそれぞれ接
続されたＮチャネルMOSトランジスタと、 前記入力端子にゲートが、前記出力端子にドレイン
が、グランドにソースがそれぞれ接続されたＮチャネル
MOSトランジスタと、 を同一基板上に構成したことを特徴とする。In the CMOS type logic integrated circuit of the present invention, the gates of N and P channel MOS transistors are connected to the input terminals, the first power supply terminal is connected to the source of the P channel MOS transistors, and the N channel MOS transistor is connected.
The ground is connected to the source of the transistor,
Further, a CMOS transistor having a common drain of N and P channel MOS transistors as an output, and an N channel MOS transistor having a gate connected to the output of the CMOS transistor, a drain connected to a second power supply terminal, and a source connected to an output terminal. And an N channel in which a gate is connected to the input terminal, a drain is connected to the output terminal, and a source is connected to the ground.
The feature is that the MOS transistor and are formed on the same substrate.
したがって、出力はドレインおよびサブストレート電
極がともに第２の電源端子に接続されたＮチャネルMOS
トランジスタより与えられるので、第１の電源端子の電
圧による閾値への影響を受けない論理レベル変換が実現
される。Therefore, the output is an N-channel MOS whose drain and substrate electrodes are both connected to the second power supply terminal.
Since the voltage is supplied from the transistor, the logic level conversion that is not affected by the threshold value by the voltage of the first power supply terminal is realized.
次に本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明のCMOS型論理集積回路の第１の実施例
を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of a CMOS logic integrated circuit according to the present invention.
本実施例は、入力端子10と、出力端子15と、電源電圧
VDD1が供給される電源端子16と、電源電圧VDD2が供給さ
れる電源端子17と、入力端子10にN,PチャネルMOSトラン
ジスタ12,11のゲートが接続され、ＰチャネルMOSトラジ
スタ11のソースが電源端子16に接続され、ＮチャネルMO
Sトランジスタ12のソースがグランドに接続されたCMOS
トランジスタと、CMOSトランジスタの出力、電源端子1
7,出力端子15がそれぞれゲート、ドレイン、ソースに接
続されたＮチャネルMOSトランジスタ13と、入力端子10,
出力端子15,グランドがそれぞれゲート、ドレイン、ソ
ースに接続されたＮチャネルMOSトランジスタ14とで構
成されている。In this embodiment, the input terminal 10, the output terminal 15, the power supply voltage
The power supply terminal 16 to which V DD1 is supplied, the power supply terminal 17 to which the power supply voltage V DD2 is supplied, and the input terminal 10 are connected to the gates of N and P channel MOS transistors 12 and 11, and the source of the P channel MOS transistor 11 is connected. Is connected to the power supply terminal 16, and N channel MO
CMOS with the source of S-transistor 12 connected to ground
Output of transistor and CMOS transistor, power supply terminal 1
7, an N-channel MOS transistor 13 whose output terminal 15 is connected to the gate, drain and source, and an input terminal 10,
The output terminal 15 and the ground are composed of an N-channel MOS transistor 14 connected to the gate, drain and source, respectively.
次に本実施例の動作について説明する。入力端子10に
電源電圧VDD1とほぼ同じ高レベルの入力があるとＰチャ
ネルトランジスタ11はオフし、Ｎチャネルトランジスタ
12はオンする。したがって、CMOSトランジスタの出力は
低レベル（グランドとほぼ同じ電位）となりＮチャネル
MOSトランジスタ13はオフする。一方、ゲートが入力端
子10に接続されているＮチャネルトランジスタ14はオン
するので出力端子15は低レベルとなる。入力端子10に低
レベルの入力があると、ＰチャネルMOSトランジスタ11
はオンし、ＮチャネルMOSトランジスタ12はオフする。
したがって、CMOSトランジスタの出力は高レベルとなり
ＮチャネルMOSトランジスタ13はオンする。一方、ゲー
トが入力端子10に接続されているＮチャネルトランジス
タ14はオフするので出力端子15には電源電圧VDD2とほぼ
等しい高レベルの出力が出力される。Next, the operation of this embodiment will be described. When the input terminal 10 has a high level input which is almost the same as the power supply voltage V DD1 , the P-channel transistor 11 is turned off and the N-channel transistor 11 is turned off.
12 turns on. Therefore, the output of the CMOS transistor becomes low level (almost the same potential as the ground) and N channel
The MOS transistor 13 is turned off. On the other hand, since the N-channel transistor 14 whose gate is connected to the input terminal 10 turns on, the output terminal 15 becomes low level. If there is a low level input at the input terminal 10, the P-channel MOS transistor 11
Turns on and the N-channel MOS transistor 12 turns off.
Therefore, the output of the CMOS transistor becomes high level and the N-channel MOS transistor 13 is turned on. On the other hand, since the N-channel transistor 14 whose gate is connected to the input terminal 10 is turned off, the output terminal 15 outputs a high level output which is substantially equal to the power supply voltage V DD2 .
第２図は本発明の第２の実施例を示す回路図である。 FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
本実施例は、第３図の従来例の初段のCMOSトランジス
タと次段のCMOSトランジスタの間にＮチャネルMOSトラ
ンジスタ36を追加したものである。入力端子10に高レベ
ルの入力があったときは、ＮチャネルMOSトランジスタ3
5がオンし出力端子15は低レベルとなる。入力端子10に
低レベル入力があったときは、ＰチャネルMOSトランジ
スタ31はオンし、ＮチャネルMOSトランジスタ32はオフ
し、ＰチャネルMOSトランジスタ34もオンし、Ｎチャネ
ルMOSトランジスタ35もオフするため、初段のCMOSトラ
ンジスタの出力は高レベルVDD1となり、次段のCMOSトラ
ンジスタの出力は電源電圧VDD1＞電源電圧VDD2の条件よ
り、基板バイアス効果を受け、電源電圧VDD2よりＰチャ
ネルトランジスタ34の閾値の変化分VTPだけ低いレベル
となるが、初段のCMOSトランジスタの出力が高レベルで
あり、ＮチャネルMOSトランジスタ36もオンするため、
出力端子15には、高レベルの電源電圧VDD2が出力され
る。In this embodiment, an N-channel MOS transistor 36 is added between the first stage CMOS transistor and the second stage CMOS transistor of the conventional example shown in FIG. When there is a high level input at the input terminal 10, the N-channel MOS transistor 3
5 turns on and output terminal 15 goes low. When there is a low level input at the input terminal 10, the P-channel MOS transistor 31 turns on, the N-channel MOS transistor 32 turns off, the P-channel MOS transistor 34 turns on, and the N-channel MOS transistor 35 also turns off. the output is at the high level V DD1 next stage of the CMOS transistors, the output of the next-stage CMOS transistors than the conditions of the supply voltage V DD1> supply voltage V DD2, receives the substrate bias effect, the power source voltage V DD2 of P-channel transistor 34 Although it becomes a level lower by the threshold change V TP, the output of the first-stage CMOS transistor is at a high level and the N-channel MOS transistor 36 is also turned on.
A high level power supply voltage V DD2 is output to the output terminal 15.
以上説明したように本発明は、次段を直列に接続した
２つのＮチャネルMOSトランジスタで構成し、初段のCMO
Sトランジスタの出力を次段の第２の電源端子側のＮチ
ャネルMOSトランジスタのゲートに接続し、入力端子を
次段のグランド側のＮチャネルMOSトランジスタのゲー
トに接続し、次段の２つのＮチャネルMOSトランジスタ
の接続点を出力端子に接続することにより同一基板上に
構成された初段のCMOSトランジスタのＰチャネルMOSト
ランジスタの基板バイアス効果をなくし、第１の電源電
圧の論理レベルを第１の電源電圧に影響されないで第２
の電源電圧の論理レベルに変換することができる効果が
ある。As described above, according to the present invention, the next stage is composed of two N-channel MOS transistors connected in series.
The output of the S transistor is connected to the gate of the N-channel MOS transistor on the second power supply terminal side of the next stage, the input terminal is connected to the gate of the N-channel MOS transistor on the ground side of the next stage, and the two N transistors of the next stage are connected. By connecting the connection point of the channel MOS transistor to the output terminal, the substrate bias effect of the P channel MOS transistor of the first stage CMOS transistor formed on the same substrate is eliminated, and the logic level of the first power supply voltage is set to the first power supply. Second without being affected by voltage
The effect is that it can be converted to the logic level of the power supply voltage.
第１図は本発明のCMOS型論理集積回路の第１の実施例を
示す回路図、第２図は第２の実施例を示す回路図、第３
図は従来例の回路図である。 10……入力端子、11,31,34……ＰチャネルMOSトランジ
スタ、12,13,14……ＮチャネルMOSトランジスタ、32,3
5,36……ＮチャネルMOSトランジスタ、16……出力端
子、16,17……電源端子、VDD1，VDD2……電源電圧。FIG. 1 is a circuit diagram showing a first embodiment of a CMOS logic integrated circuit of the present invention, FIG. 2 is a circuit diagram showing a second embodiment, and FIG.
The figure is a circuit diagram of a conventional example. 10 …… Input terminal, 11,31,34 …… P-channel MOS transistor, 12,13,14 …… N-channel MOS transistor, 32,3
5,36 ... N-channel MOS transistor, 16 ... output terminal, 16, 17 ... power supply terminal, V DD1 , V DD2 ... power supply voltage.
Claims (1)
タのゲートが、ＰチャネルMOSトランジスタのソースに
第１の電源端子が、ＮチャネルMOSトランジスタのソー
スにグランドがそれぞれ接続され、さらにＮ、Ｐチャネ
ルMOSトランジスタの共通ドレインを出力としたCMOSト
ランジスタと、 前記CMOSトランジスタの前記出力にゲートが、第２の電
源端子にドレインが、出力端子にソースがそれぞれ接続
されたＮチャネルMOSトランジスタと、 前記入力端子にゲートが、前記出力端子にドレインが、
グランドにソースがそれぞれ接続されたＮチャネルMOS
トランジスタと、 を同一基板上に構成したことを特徴とするCMOS型論理集
積回路。1. An N- and P-channel MOS transistor gate is connected to an input terminal, a P-channel MOS transistor source is connected to a first power supply terminal, and an N-channel MOS transistor source is connected to ground. A CMOS transistor having a common drain of the MOS transistor as an output, an N-channel MOS transistor having a gate connected to the output of the CMOS transistor, a drain connected to a second power supply terminal, and a source connected to an output terminal, and the input terminal Has a gate, the output terminal has a drain,
N-channel MOS with source connected to ground
A CMOS type logic integrated circuit characterized in that the transistor and are formed on the same substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61083501A JP2550942B2 (en) | 1986-04-11 | 1986-04-11 | CMOS type logic integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61083501A JP2550942B2 (en) | 1986-04-11 | 1986-04-11 | CMOS type logic integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62239565A JPS62239565A (en) | 1987-10-20 |
| JP2550942B2 true JP2550942B2 (en) | 1996-11-06 |
Family
ID=13804224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61083501A Expired - Lifetime JP2550942B2 (en) | 1986-04-11 | 1986-04-11 | CMOS type logic integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2550942B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877319A (en) * | 1981-11-02 | 1983-05-10 | Hitachi Ltd | Level converting circuit |
-
1986
- 1986-04-11 JP JP61083501A patent/JP2550942B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877319A (en) * | 1981-11-02 | 1983-05-10 | Hitachi Ltd | Level converting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62239565A (en) | 1987-10-20 |
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