JPS62239565A - Cmos logical integrated circuit - Google Patents
Cmos logical integrated circuitInfo
- Publication number
- JPS62239565A JPS62239565A JP61083501A JP8350186A JPS62239565A JP S62239565 A JPS62239565 A JP S62239565A JP 61083501 A JP61083501 A JP 61083501A JP 8350186 A JP8350186 A JP 8350186A JP S62239565 A JPS62239565 A JP S62239565A
- Authority
- JP
- Japan
- Prior art keywords
- channel mos
- transistor
- mos transistor
- output
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は同一」１ξ板にに構成された２組のＣＭＯＳト
ランジスタを同一人力′１゛ニ圧に対して異なる２神の
電源電圧で動作させるＣＭＯＳ型論理集積回路に関する
。[Detailed Description of the Invention] [Industrial Application Field] The present invention operates two sets of CMOS transistors configured on the same 1ξ board with two different power supply voltages for the same human power and 1ξ pressure. The present invention relates to a CMOS type logic integrated circuit.
従来、この種のＣＭ Ｑ Ｓｌａｇ、論理集積回路は、
第３図に示すように、入力端７ＡＯと、Ｐチヘ・ネルＭ
ＯＳトランジスタ３１とＮチャンネルＭＯＳトランジス
タ：Ｉ２かうなり、入力端Ｙ＝１０と接続され、電源電
圧ｖ１１１１１がＰチャンネルＭＯ５）−ランジスタ３
１のソースに接続されている初段のＣＭＯＳｌ−ランジ
スタと、ＰチャネルＭＯＳトランジスタ：１４とＮチｉ
’ネルＭＯＳトランジスタ：１５からなり１人力９ｉ１
１゜１’−１０および出力端子１５に接続され、電源電
圧Ｖ １１０２がＰチャネルトランジスタ３４のソース
に接続されている次段のＣＭＯＳトランジスタで構成さ
れている。ここで電源電圧Ｖｌｌｌｌ＋と電源電圧Ｖ
１１１１２の関係は、ｖｌｌ、□＞Ｖｌ１０２となって
いるので、１論理レヘルはＶＤＩ）ｌからＶ １１１１
２に変換される。Conventionally, this type of CM Q Slag, logic integrated circuit,
As shown in FIG.
OS transistor 31 and N-channel MOS transistor: I2 output, connected to input terminal Y=10, power supply voltage v11111 is P-channel MO5)-transistor 3
The first stage CMOS transistor connected to the source of 1, the P channel MOS transistor: 14 and the N transistor
'Nel MOS transistor: Consisting of 15, one-man operation 9i1
1°1'-10 and the output terminal 15, and the power supply voltage V1102 is connected to the source of the P-channel transistor 34. Here, the power supply voltage Vllll+ and the power supply voltage V
The relationship between 11112 is vll,□>Vl102, so 1 logical level is VDI)l to V1111
Converted to 2.
〔発明が解決しようと１−る問題点〕
１−述した従来のＣＭ ＯＳ Ｊ１￥論理集禎回路は、
同一 Ｊ、ｔ、板（ＮＪ、Ｃ板） ｌ−ニＰチャネルＭ
ＯＳ ト’／ ンシスタ３１および３４を作るため、Ｐ
チャネルＭＯＳトランジスタ３１および３４のサブスト
レート電極は同一バ°イアスとなっており、Ｐチヤネル
ＭＯＳトランジスタ：１４は高い′１°ｉＪ、源電圧Ｖ
ｌｌ１３＋でバイアスされることになるため、ＪｌＬ板
バイアス効果により閾値型／ＥＶ１ｐが変化し、出力電
圧が電源電圧Ｖ。ｏ２より閾値電圧■ア９．の変化した
分だけ低くなるという欠点かある。[1-Problems that the invention seeks to solve] 1-The conventional CM OS J1 logic integrated circuit described above has the following problems:
Same J, t, plate (NJ, C plate) l-ni P channel M
In order to create OS/systems 31 and 34, P
The substrate electrodes of the channel MOS transistors 31 and 34 have the same bias, and the P channel MOS transistor 14 has a high '1°iJ, source voltage V.
Since it will be biased at ll13+, the threshold type /EV1p changes due to the JIL plate bias effect, and the output voltage becomes the power supply voltage V. Threshold voltage from o2 ■A9. The disadvantage is that the value decreases by the amount of change in .
（問題点を解決するだめの手段）
本発明のＣＭＯ５型Ｏ５集積回路は、入力端Ｙ−と、出
力端子と、第１の′ｌ’ｌｉ＋源端子と、第２の電源端
ｒと、人力、５Ｑ ｒ−にＮ、ＰチャネルＭＯＳトラン
ジスタのゲートか接続され、ＰチャネルＭＯＳトランジ
スタのソースか第１の電源端Ｙ−に接続され、Ｎチャネ
ルＭＯ５Ｉ−ランジスタのソースがグランドに接続され
たＣＭＯＳトランジスタと、ＣＭＯＳトランジスタの出
力、第２の′１′にｄ！；（端子、出力端ｒ・にそれぞ
れケート、トレーｒン、ソースか接続されたＮチャネル
ＭＯＳトランジスタと、入力端ｉ 、／、、出力端ｒ゛
、クランドにそれぞれケート、トレイン、ソースか接続
されたＮチャネルＭＯＳトランジスタを４１−１−る。(Means for Solving the Problem) The CMO5 type O5 integrated circuit of the present invention has an input terminal Y-, an output terminal, a first 'l'li+ source terminal, a second power supply terminal r, and a human power terminal. , 5Q r- is connected to the gate of the N, P-channel MOS transistor, the source of the P-channel MOS transistor is connected to the first power supply terminal Y-, and the source of the N-channel MO5I- transistor is connected to the ground. and the output of the CMOS transistor, d! to the second '1'. (An N-channel MOS transistor whose gate, train, and source are connected to the terminal and output terminal r, respectively, and whose gate, train, and source are connected to the input terminal i, /, and the output terminal r' and ground, respectively. 41-1- is an N-channel MOS transistor.
したがって、出力はトレインおよびサブストレート＋７
Ｂ極がともに第２の電源端子に接続されたＮチャネルＭ
ＯＳトランジスタより与えられるので、第１の電源端子
−の電圧による閾値への影響を受けない論理レベル変換
が実現される。Therefore, the output is train and substrate +7
N-channel M with both B poles connected to the second power supply terminal
Since the voltage is applied from the OS transistor, logic level conversion is realized in which the threshold value is not affected by the voltage of the first power supply terminal -.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明のＣＭＯ３へ１！論理集積回路の第１の
実施例を示す回路図である。FIG. 1 shows 1! to CMO3 of the present invention! 1 is a circuit diagram showing a first example of a logic integrated circuit; FIG.
本実施例は、入力端一１’−１０と、出力端子１５と、
電源′１「圧Ｖｌｌ［１１が供給される電源端子−１６
と、電源’＋−ｔｊ圧Ｖ ｌ）Ｄ ２か供給される電源
端Ｙ−１７と、入力端ｊ’−１０にＮ、ＰチャネルＭＯ
Ｓトランジスタ１２．１１のゲートか接続され、Ｐチャ
ネルＭＯＳトランジスタ１１のソースがｒＩｔ源端子１
６に接続され、ＮチャネルＭＯＳトランジスタ１ｚのソ
ースがグランドに接続されたＣＭＯＳトランジスタと、
ＣＭＯＳトランジスタの出力、電源端子１７．出力端子
１５がそれぞれケート、ドレイン、ソースに接続された
ＮチャネルＭＯＳトランジスタ１：１と、入力端子１０
．出力Ｑ：８ 、ｒ−ｌ ５．グランドがそれぞれゲー
ト、ドレイン、ソースに接続されたＮチャネルＭＯＳト
ランジスタ目とで構成されている。In this embodiment, the input terminal 1'-10, the output terminal 15,
Power supply terminal -16 to which voltage Vll[11 is supplied
, the power supply terminal Y-17 to which the power supply '+-tj pressure V l)D 2 is supplied, and the N and P channel MOs are connected to the input terminal j'-10.
The gates of S transistors 12 and 11 are connected, and the source of P channel MOS transistor 11 is connected to rIt source terminal 1.
6, and the source of the N-channel MOS transistor 1z is connected to the ground;
CMOS transistor output, power supply terminal 17. An N-channel MOS transistor 1:1 with the output terminal 15 connected to the gate, drain, and source, respectively, and the input terminal 10
．． Output Q: 8, r-l 5. It consists of an N-channel MOS transistor whose gate, drain, and source are respectively connected to the ground.
次に本実施例の動作について説明する。入力端子−１０
に電源電圧Ｖｌｌｌｌ＋とほぼ同じ高レベルの人力があ
るとＰチャネルトランジスタ１１はオフし、Ｎチャネル
トランジスタＩ２はオンする。したがって、ＣＭＯＳト
ランジスタの出力は低レベル（グランドとほぼ同じ電位
）となりＮチャネルＭＯＳトランジスタ１３はオフ′Ｘ
＋−る。一方、ゲートが人力０：１−１０に接続されて
いるＮチャネルトランジスタロはオンするので出力端子
１５は低レベルとなる。Next, the operation of this embodiment will be explained. Input terminal -10
When there is a human power at a high level almost equal to the power supply voltage Vllll+, the P-channel transistor 11 is turned off and the N-channel transistor I2 is turned on. Therefore, the output of the CMOS transistor becomes a low level (approximately the same potential as ground), and the N-channel MOS transistor 13 is turned off.
+-ru. On the other hand, since the N-channel transistor whose gate is connected to the input voltage 0:1-10 is turned on, the output terminal 15 becomes a low level.
人力鑞１子ｌＯに低レベルの人力かあると、Ｐチャネル
ＭＯＳトランジスタ１１はオンし、ＮチャネルＭＯ３Ｉ
−ランシスタ１２はオフする。したかって、ＣＭＯＳト
ランジスタの出力は高レベルとなりＮチャネルＭＯＳト
ランジスタ１３はオンする。一方、ゲートか入力端子・
１０に接続されているＮチャネルトランジスタＩ４はオ
フするので出力端子１５には電源電圧Ｖ １１＋１２と
ほぼ等しい高レベルの出力か出力される。When a low level of human power is applied to the human power source 1O, the P channel MOS transistor 11 is turned on, and the N channel MO3I
- Runsistor 12 is turned off. Therefore, the output of the CMOS transistor becomes high level, and the N-channel MOS transistor 13 is turned on. On the other hand, gate or input terminal
Since the N-channel transistor I4 connected to V10 is turned off, a high level output approximately equal to the power supply voltage V11+12 is output to the output terminal 15.
第２図は本発明の第２の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
本実施例は、第３図の従来例の初段のＣＭＯＳトランジ
スタと次段のＣＭＯＳトランジスタの間にＮチャネルＭ
ＯＳトランジスタ３６を追加したものである。人力Ｇ５
ｉ ’ｆ ｌ Ｏに高レベルの人力かあったときは、Ｎ
チャネルＭＯＳトランジスタ３５かオンし出力幅＋、
−（、ｌ ５は低レベルとなる。人力Ｑｒ−１ｏに低レ
ベル人力があったときは、ＰチャネルＭＯＳトランジス
タ３１はオンし、ＮチャンネルＭＯＳｌ−ランジスタ：
１２はオフし、ＰチャネルＭＯ５Ｉ−ランシメタ３イも
オンレ、ＮチャネルＭＯ３）ランシスタ３５もオフ−ｊ
−るため、初段のＣＭＯＳトランジスタの出力は高レベ
ルｖ１，１□となり、次段のＣＭＯＳトランジスタの出
力は電源電圧Ｖｌ）Ｌ）１＞電源電圧Ｖ。１．２の条ヂ
］より、Ｊ、ｃ板バイアス効果を受け、電源電圧ＶＤＤ
２よりＰチャンネルトランジスタ３４の閾値の変化分■
１．１．たけ低いレベルとなるが、初段のＣＭＯＳトラ
ンジスタの出力が高レベルであり、ＮチャネルＭＯＳト
ランジスタ：１にもオンするため、出力端子１５には、
高レベルの電源電圧Ｖ ｌ）＋１２が出力される。In this embodiment, an N-channel M is connected between the first stage CMOS transistor and the next stage CMOS transistor of the conventional example shown in
An OS transistor 36 is added. Human power G5
When i 'f l O had a high level of manpower, N
Channel MOS transistor 35 is turned on and output width +,
-(, l5 becomes a low level. When there is a low level human power in the human power Qr-1o, the P channel MOS transistor 31 is turned on, and the N channel MOS transistor 31 is turned on, and the N channel MOS transistor 31 is turned on.
12 is off, P-channel MO5I-Ranshimeter 3 is also on, N-channel MO3) Runsister 35 is also off-j
- Therefore, the output of the first-stage CMOS transistor becomes a high level v1,1□, and the output of the next-stage CMOS transistor becomes the power supply voltage Vl)L)1>power supply voltage V. 1.2], due to the J and C plate bias effects, the power supply voltage VDD
From 2, the change in the threshold of the P-channel transistor 34■
1.1. Although the level is quite low, the output of the first-stage CMOS transistor is at a high level, and the N-channel MOS transistor:1 is also turned on, so the output terminal 15 has a
A high level power supply voltage Vl)+12 is output.
以上説明したように本発明は、次段を直列に接続した２
つのＮチャネルＭＯＳトランジスタで構成し、初段のＣ
ＭＯＳトランジスタの出力を次段の第２の電諒端子側の
ＮチャネルＭＯＳトランジスタのケートに接続し、入力
端子を次段のグランド側のＮチャネルＭＯＳトランジス
タのゲートに接続し、次段の２つのＮチャネルＭＯＳト
ランジスタの接続点を出力端Ｙ−に接続することにより
同−一」、ｔ、板上に構成された初段のＣＭＯＳトラン
ジスタのＰチャネルＭＯＳトランジスタのノ１（板バイ
アス効果をなくし、第１の電源電圧の論理レベルを第１
の電源室ＪＬにｊＪ９ ＭＰされないで第２の電源電圧
の論理レベルに変換１−ることかできる効果かある。As explained above, the present invention provides two
It consists of two N-channel MOS transistors, and the first stage C
The output of the MOS transistor is connected to the gate of the N-channel MOS transistor on the second voltage terminal side of the next stage, and the input terminal is connected to the gate of the N-channel MOS transistor on the ground side of the next stage. By connecting the connection point of the N-channel MOS transistor to the output terminal Y-, the connection point of the P-channel MOS transistor of the first-stage CMOS transistor configured on the board is eliminated, and the 1 logic level of the power supply voltage to the first
There is an effect that jJ9 in the power supply room JL can be converted to the logic level of the second power supply voltage without being converted to MP.
る。Ru.
第１図は本発明のＣＭ ＯＳ ｒＨ２論理集Ｊ＋？回路
の第１の実施例を示す回路図、第２図は第２の実施例を
示す回路図、第３図は従来例の回路図である。
１０・・・入力端子、
＋１．：ｌ＋、３４−・・ＰチャネルＭＯＳトランジス
タ。
１２．１：１．１４・・・ＮチャネルＭＯ３Ｉ−タンジ
スタ、：１２．：１５．：Ｉｔｉ・・・ＮチャネルＭＯ
Ｓトランジスタ、１５ ＝−出力Ｉ＞；、） （−１
１６、１７・・弓に源幅１ｒ゛、
Ｖｌｌｌ）１． Ｖｌ＋。２・・・′−゛「源′１°「
圧。FIG. 1 shows the CM OS rH2 logic collection J+? of the present invention. FIG. 2 is a circuit diagram showing the first embodiment of the circuit, FIG. 2 is a circuit diagram showing the second embodiment, and FIG. 3 is a circuit diagram of a conventional example. 10...input terminal, +1. :l+, 34-...P channel MOS transistor. 12.1:1.14...N-channel MO3I-tanister:12. :15. :Iti...N channel MO
S transistor, 15 =-output I>;,) (-1 16, 17... source width 1r゛, Vllll)1. Vl+. 2...'-゛"Source'1°"
Pressure.
Claims (1)
が接続され、ＰチャネルＭＯＳトランジスタのソースが
第１の電源端子に接続され、ＮチャネルＭＯＳトランジ
スタのソースがグランドに接続されたＣＭＯＳトランジ
スタと、 ＣＭＯＳトランジスタの出力、第２の電源端子、出力端
子にそれぞれゲート、ドレイン、ソースが接続されたＮ
チャネルＭＯＳトランジスタと、 入力端子、出力端子、グランドにそれぞれゲート、ドレ
イン、ソースが接続されたＮチヤネルＭＯＳトランジス
タを有するＣＭＯＳ型論理集積回路。[Claims] An input terminal, an output terminal, a first power supply terminal, a second power supply terminal, the gates of N and P channel MOS transistors are connected to the input terminal, and the source of the P channel MOS transistor is connected to the input terminal. A CMOS transistor is connected to the first power supply terminal, and the source of the N-channel MOS transistor is connected to the ground;
A CMOS logic integrated circuit having a channel MOS transistor and an N-channel MOS transistor whose gate, drain, and source are connected to the input terminal, output terminal, and ground, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61083501A JP2550942B2 (en) | 1986-04-11 | 1986-04-11 | CMOS type logic integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61083501A JP2550942B2 (en) | 1986-04-11 | 1986-04-11 | CMOS type logic integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62239565A true JPS62239565A (en) | 1987-10-20 |
| JP2550942B2 JP2550942B2 (en) | 1996-11-06 |
Family
ID=13804224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61083501A Expired - Lifetime JP2550942B2 (en) | 1986-04-11 | 1986-04-11 | CMOS type logic integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2550942B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877319A (en) * | 1981-11-02 | 1983-05-10 | Hitachi Ltd | Level converting circuit |
-
1986
- 1986-04-11 JP JP61083501A patent/JP2550942B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877319A (en) * | 1981-11-02 | 1983-05-10 | Hitachi Ltd | Level converting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2550942B2 (en) | 1996-11-06 |
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