JPS6195617A - Cmos logic circuit - Google Patents
Cmos logic circuitInfo
- Publication number
- JPS6195617A JPS6195617A JP59216259A JP21625984A JPS6195617A JP S6195617 A JPS6195617 A JP S6195617A JP 59216259 A JP59216259 A JP 59216259A JP 21625984 A JP21625984 A JP 21625984A JP S6195617 A JPS6195617 A JP S6195617A
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- Prior art keywords
- input
- output
- turned
- nmos
- gate
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
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- Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は論理回路に係り、特に、相補型ＭＯ３ＦＥＴ（
ＣＭＯ３）を使用した排他的ＯＲ回路及び排他的ＮＯＲ
回路の改良に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a logic circuit, and particularly to a complementary MO3FET (
Exclusive OR circuit and exclusive NOR using CMO3)
Regarding circuit improvement.
排他的ＯＲ回路（以下ＦＯＲと略す、）として、従来、
第３図の回路が使用されている。この回路の入力、出力
の関係は次式で示される。Conventionally, as an exclusive OR circuit (hereinafter abbreviated as FOR),
The circuit of FIG. 3 is used. The relationship between the input and output of this circuit is shown by the following equation.
Ｃ＝ＡψＢ＋Ａ−Ｂ
また、排他的ＮＯＲ回路（以下、 ＥＮＯＲと略す、）
として、従来、第４図の回路が使用されている。C=AψB+A-B Also, exclusive NOR circuit (hereinafter abbreviated as ENOR)
Conventionally, the circuit shown in FIG. 4 has been used.
この回路の入力、出力の関係は。What is the relationship between the input and output of this circuit?
Ｃ＝Ａ−Ｂ＋Ａ−Ｂ
ところで、上記の回路をＣＭＯ５で構成した場合、夫々
、１２ケのトランジスタを必要とし、集積回路の面積が
大きくなる欠点がある。C=A-B+A-B By the way, when the above circuit is constructed using CMO5, 12 transistors are required for each, which has the disadvantage that the area of the integrated circuit becomes large.
この欠点を改良したＦＯＲ，ＥＮＯＲ回路が特開昭５０
−１４０２５５号の第２図、第３図に示されている。FOR and ENOR circuits that improved this drawback were developed in 1983.
This is shown in Figures 2 and 3 of No.-140255.
第５図は、改良された従来のＥＯＲ回路を示す。FIG. 5 shows an improved conventional EOR circuit.
図において、５１はＰＭＯ５であり、ソースが電源子Ｖ
に、ゲートが入力Ａに接続され、ドレインがＮＭＯＳ５
２のドレインに接続される。 ＮＭＯＳ５２のゲートは
入力Ａに接続され、ソースは接地電位ＧＮＤに接続され
る。また、ＰＭＯＳ５１とＮＭＯＳ５１の共通接点Ｐは
ＮＭＯＳ ５４のソースに接続される。５３はＰＭＯ５
であり、ソースは入力Ａに、ゲートは入力Ｂに接続され
、ドレインは出力Ｃに接続される。In the figure, 51 is PMO5, and the source is the power supply V
, the gate is connected to input A, and the drain is connected to NMOS5.
Connected to the drain of 2. The gate of NMOS 52 is connected to input A, and the source is connected to ground potential GND. Further, a common contact P between the PMOS 51 and the NMOS 51 is connected to the source of the NMOS 54. 53 is PMO5
, the source is connected to input A, the gate is connected to input B, and the drain is connected to output C.
５４はＮＭＯＳであり、ドレインは出力Ｃに、ゲートは
入力Ｂに接続され、ソースはＰ点に接続される。54 is an NMOS whose drain is connected to output C, gate is connected to input B, and source is connected to point P.
この回路の入力Ａ、Ｂと出力Ｃの関係及び出力（Ｃの電
圧レベルは表１に示すとおりである。以下。The relationship between inputs A, B and output C of this circuit and the voltage level of output (C) are as shown in Table 1. Below.
この回路の動作を説明する。The operation of this circuit will be explained.
この回路の動作を説明する。The operation of this circuit will be explained.
第 １ 表 いま、入力Ａが“１”、入力Ｂが＃ Ｏ＃のとき。Table 1 Now, when input A is "1" and input B is #O#.
ＰＭＯ３６３はオン、ＮＭＯＳ５４はオフになる。その
結果、出力Ｃは“１”になり電源＋Ｖまで充電される０
次に、入力Ａ、Ｂが共にｌ（Ｉ １１のとき、 ＰＭＯ
３５３はオフ、ＮＭＯＳ５４はオンになる。一方、Ｐ点
はＯｖまで下がれるので出力ＣはＮＭＯＳ５４ 、 Ｎ
に０８５２を通してＯｖまで放電され、０”レベルにな
る。PMO363 is turned on and NMOS54 is turned off. As a result, the output C becomes “1” and is charged to the power supply +V.
Next, when inputs A and B are both l (I 11, PMO
353 is turned off and NMOS 54 is turned on. On the other hand, since the P point can be lowered to Ov, the output C is NMOS54, N
It is discharged to Ov through 0852 and becomes 0'' level.
入力Ａ、Ｂが共に“０ルベルのとき、ＮＭＯＳ５４はオ
フ、ＰＭＯ３５３はオンになる。その結果。When inputs A and B are both "0 level", NMOS54 is turned off and PMO353 is turned on.The result.
出力Ｃは“０”になる。このとき、出力ＣがＰＭＯ５５
３のＶ□以下になると、ＰＭＯ３５３はオンを維持でき
なくなる。従って、出力Ｃの“０”レベルは表１のよう
にΔｖ１のオフセットを持つ。Output C becomes "0". At this time, the output C is PMO55
When the voltage drops below 3 V□, the PMO 353 cannot remain on. Therefore, the "0" level of the output C has an offset of Δv1 as shown in Table 1.
次に、入力Ａが＃ Ｑ １１．入力Ｂが１”のときＰＭ
Ｏ５５３はオフ、ＮＭＯＳ５４はオンになる。一方、Ｐ
点は“ｌ”になるので出力Ｃは“ｌ”になる。Next, input A is #Q 11. PM when input B is 1”
O553 is turned off and NMOS54 is turned on. On the other hand, P
Since the point becomes "l", the output C becomes "l".
このとき、ＮＭＯＳ ５４の基板効果により出力Ｃは電
源＋Ｖまで上昇できず、表１のようにΔｖ２だけのオフ
セットを持つ。At this time, the output C cannot rise to the power supply +V due to the substrate effect of the NMOS 54, and has an offset of Δv2 as shown in Table 1.
第６図は改良された従来のＥＮＯＲ回路を示す１図にお
いて、６１はＰＭＯ５であり、ソースは電源Ｖ＋に、ゲ
ートは入力Ａに接続され、ドレインはＮＭＯＳ６２のド
レインに接続される。 ＮＭＯＳ６２のゲートは入力Ａ
に接続され、ソースはＧＮＤに接続される。６３はＰＭ
Ｏ５テあり、ソースはＰＭＯ５６１、ＮＭＯＳ６２の共
通ドレイン接続点Ｐに接続される。 ＰＭＯ３６３のゲ
ートは入力Ｂに、ドレインは出力Ｃに接続される。６４
はＮＭＯＳであり、ドレイン′は出力Ｃに、ゲートは入
力Ｂに接続され、ソースは入力Ａに接続される。FIG. 6 shows an improved conventional ENOR circuit, in which 61 is a PMO 5 whose source is connected to the power supply V+, whose gate is connected to input A, and whose drain is connected to the drain of NMOS 62. The gate of NMOS62 is input A
The source is connected to GND. 63 is PM
There is an O5 terminal, and the source is connected to the common drain connection point P of PMO561 and NMOS62. The gate of PMO363 is connected to input B, and the drain is connected to output C. 64
is an NMOS, the drain' is connected to the output C, the gate is connected to the input B, and the source is connected to the input A.
この回路の入力Ａ、Ｂと出力Ｃの関係及び出力Ｃの電圧
レベルは表２に示すとおりである。以下。The relationship between inputs A, B and output C of this circuit and the voltage level of output C are as shown in Table 2. below.
この回路の動作を説明する。The operation of this circuit will be explained.
いま、入力Ａ、Ｂがともに“０″のとき、Ｐ点は“ｌ”
になり、ＮＭＯＳ６４はオフ、 ＰＭＯ３８３はオンに
なる。その結果、出力ｃ４“１”になり電源＋Ｖまで充
電される２次に入力Ａがｌｏ＃ＺＢが“１″のときＰＭ
Ｏ３６３はオフ、ＮＭＯＳ６４はオンになる。その結果
、出力Ｃはｊｊ Ｏｊ７レベルになりＯＶまで放電され
る。Now, when inputs A and B are both “0”, point P is “l”
, NMOS64 is turned off and PMO383 is turned on. As a result, the output c4 becomes "1" and the secondary input A is charged to the power supply +V.When lo#ZB is "1", PM
O363 is turned off and NMOS64 is turned on. As a result, the output C becomes the jj Oj7 level and is discharged to OV.
入力Ａが“１”、Ｂが“０″のとき、Ｐ点は”Ｏ”に？
、＋ｌＪ、ＮＭＯＳ６４１；！オフ 、 ＰＭＯ５６３
１Ｌオンになる。その結果、出力Ｃは“０”になる。こ
のとき、出力ＣがＰＭＯ３６３のｖ０以下になると。When input A is “1” and input B is “0”, does point P become “O”?
, +lJ, NMOS641;! Off, PMO563
1L turns on. As a result, the output C becomes "0". At this time, when the output C becomes less than v0 of PMO363.
ＰＭＯ５６３はオンを維持できなくなる。従って、出力
Ｃのレベルは表２のようにＡＶ、のオフセットを持つ。PMO 563 will no longer be able to remain on. Therefore, the level of output C has an offset of AV as shown in Table 2.
入力Ａ、Ｂが共に“１″のとき、Ｐ点は１”になり、Ｐ
ＭＱＳ６３はオフ、８ＭＯ８６４はオンになる。When inputs A and B are both “1”, point P becomes “1” and P
MQS63 is turned off and 8MO864 is turned on.
このとき、ＮＭＯＳ６４の基板効果により出力Ｃは電源
子Ｖまで上昇できず１表２のようにＡＶ、だけのオフセ
ットを持つ。At this time, due to the substrate effect of the NMOS 64, the output C cannot rise to the power supply voltage V, and has an offset of AV as shown in Table 1.
このように、改良された従来のＥＯＲ，ＥＮＯＲ回路で
は少ない素子数で構成できる反面、出力電圧レベルにオ
フセットを持つため、その出力に接続される論理回路の
消費電力が増大する欠点がある。As described above, although the improved conventional EOR and ENOR circuits can be configured with a small number of elements, they have the disadvantage that the output voltage level has an offset, which increases the power consumption of the logic circuit connected to the output.
本発明の目的はこのような従来技術の欠点を除去した排
他的ＯＲ回路、排他的ＮＯＲ回路を提供することにある
。An object of the present invention is to provide an exclusive OR circuit and an exclusive NOR circuit that eliminate the drawbacks of the prior art.
本発明の要点は、一方の入力と出力の間にｐｓｏｓと８
ＭＯ５を並列接続した相補スイッチを設け、夫々のゲー
トを他方入力の正又は反転信号で駆動することにある。The key point of the invention is that between one input and output there is a psos and an 8
A complementary switch is provided in which MO5s are connected in parallel, and each gate is driven by a positive or inverted signal input from the other.
以下、図面に従って本発明の詳細な説明する。 Hereinafter, the present invention will be described in detail with reference to the drawings.
第１図は本発明のＥＯＲ回路である０本発明ではＰＭＱ
Ｓ１５と８ＭＯ３１６からなる相補スイッチが新たに設
けられている。 ＰＭＱＳ １５とＮＨＱＳ １６の一
方の電極は共通接続され、入力Ｂに接続される。 ＰＭ
ＱＳ１５と８ＭＯ５１６の他方の電極は共通接続され、
出力Ｃに接続される。また、ＰＭＱＳ１５のゲートは入
力Ａに接続され、８ＭＯ５１６のゲートは入力Ａの反転
出力であるＰ点に接続される。Figure 1 shows the EOR circuit of the present invention.0 In the present invention, PMQ
A complementary switch consisting of S15 and 8MO316 is newly provided. One electrode of PMQS 15 and NHQS 16 are commonly connected and connected to input B. PM
The other electrodes of QS15 and 8MO516 are commonly connected,
Connected to output C. Further, the gate of PMQS15 is connected to input A, and the gate of 8MO516 is connected to point P, which is the inverted output of input A.
この回路の動作は次のとおりである。いま、入力Ａ、Ｂ
が共にＩＩ Ｏ”のとき、ＮＭＯＳ５４はオフになり、
Ｐに０８５３とＰＭＱＳ１５がオンになる。 ＰＭＱＳ
５３とＰＭＱＳ１５による放電で出力ＣはＡＶ、まで下
がる。一方、このときＰ点は″１″になっているので、
８ＭＯ３１６もオンになる。この結果、出力Ｃは完全に
０まで放電され、１１０ Ｉ＋レベルになる。The operation of this circuit is as follows. Now input A, B
When both are IIO”, NMOS54 is turned off,
0853 and PMQS15 are turned on. PMQS
53 and PMQS15, the output C drops to AV. On the other hand, since the P point is "1" at this time,
8MO316 is also turned on. As a result, the output C is completely discharged to 0 and reaches the 110 I+ level.
次に、入力Ａが１１０”、Ｂが“１″のとき、Ｐ点はＩ
Ｉ ｌ ＋１になり、 ＰＭＱＳ５３はオフ、ＮＭＯＳ
５４と８ＭＯ３１６がオンになる。ＮＭＯＳ５４と８Ｍ
Ｏ３１６による充電圧で出力Ｃは＋Ｖ−ａＶ２まで上昇
する。Next, when input A is 110'' and input B is 1, point P is I
I l +1, PMQS53 is off, NMOS
54 and 8MO316 are turned on. NMOS54 and 8M
The output C rises to +V-aV2 due to the charging pressure caused by O316.
一方、このとき、ＰＭＱＳ１５はオンになっているので
出力Ｃは＋■まで充電され、６１″レベルになる。On the other hand, since the PMQS 15 is on at this time, the output C is charged to +■ and reaches the 61'' level.
次に、入力Ａが“１”、Ｂが“ＯＮのとき、Ｐ点は“０
＃になり、ＮＨＱＳ ５４とＮＭＯＳ １６ 、 ＰＭ
ＱＳ１５はオフ、ＰＭＱＳ５３がオンになる。その結果
、出力Ｃは＋Ｖまで充電圧され“１”レベルになる。Next, when input A is “1” and input B is “ON”, point P is “0”.
#, NHQS 54 and NMOS 16, PM
QS15 is turned off and PMQS53 is turned on. As a result, the output C is charged to +V and becomes the "1" level.
次に、入力Ａ、Ｂが共に“１”のとき、Ｐ点は１／ Ｏ
ＩＩになり、ＰＭＱＳ５３ 、 ＰＭＯ５Ｉ ５ 、
ＮＮＱＳＩ ６はオフ、ＮＭＯＳ５４はオンになる。そ
の結果、出力ＣはＯｖまで放電され、“０ルベルになる
。Next, when inputs A and B are both “1”, point P is 1/O
II, PMQS53, PMO5I 5,
NNQSI 6 is turned off and NMOS 54 is turned on. As a result, the output C is discharged to Ov and becomes "0 level."
第２図は本発明のＥＭＯＲ回路である。FIG. 2 shows the EMOR circuit of the present invention.
本発明ではＰＭＱＳ１５と８ＭＯ３１６からなる相補ス
イッチが新たに設けられている。 ＰＭＯ５Ｉ ５と８
ＭＯ３１６の一方の電極は共通接続され、入力Ｂに接続
される。ＰＭＱＳ ｌ ５と８ＭＯ５１６の他方の電極
は共通接続され、出力Ｃに接続される。また、ＰＭＱＳ
１５のゲートは入口Ａの反転出力であるＰ点に接続され
、８ＭＯ５１６のゲートは入力Ａに接続布れる。In the present invention, a complementary switch consisting of PMQS15 and 8MO316 is newly provided. PMO5I 5 and 8
One electrode of MO 316 is connected in common and connected to input B. The other electrodes of PMQS l 5 and 8MO516 are connected in common and connected to output C. Also, PMQS
The gate of 8MO516 is connected to point P, which is the inverted output of input A, and the gate of 8MO516 is connected to input A.
この回路の動作は次のとおりである。いま、入力Ａ、Ｂ
が共に′０”のとき、Ｐ点は１１１１１になり、ＰＭＯ
５Ｉ ５ 、 ＮＮＱＳＩ ８ 、 ＮＨＱＳ５４がオ
フニなる。The operation of this circuit is as follows. Now input A, B
When both are '0'', the P point becomes 11111, and PMO
5I 5, NNQSI 8, and NHQS54 are off.
その結果、出力Ｃは電源＋ｖまで充電され、ＩＪ”にな
る。As a result, the output C is charged to the power supply +v and becomes IJ''.
次に入力Ａが“０”、Ｂが“１″のとき、Ｐ点は“１”
になり、ＰＭＱＳ ６３ 、 ＮＭＯＳ １６はオフ。Next, when input A is “0” and input B is “1”, point P is “1”
PMQS 63 and NMOS 16 are turned off.
ＮＭＯＳ６４はオンになる。その結果、出力Ｃはｏｖで
放電され、′０”になる。NMOS 64 is turned on. As a result, the output C is discharged at ov and becomes '0'.
次に入力Ａが１１”、Ｂが′Ｏ″のとき、Ｐ点は” ｏ
” ニなり、ＰＭＱＳ １５ 、 ＮＨＱＳ ６４が
オフニなり、ＰＭＱＳ６３がオンニなり、出ＯＣはＰＭ
ＱＳ６３を通してＡＶ、まで放電される。一方、このと
き、８ＭＯ５１６もオンになっているので出力Ｃは完全
にＯｖまで放電されｌｌ Ｏ１１となる。Next, when input A is 11" and input B is 'O', point P is "o"
” PMQS 15, NHQS 64 is off-ni, PMQS63 is on-ni, exit OC is PM
It is discharged to AV through QS63. On the other hand, at this time, since the 8MO516 is also on, the output C is completely discharged to Ov and becomes llO11.
次に、入力Ａ、Ｂが共にＩＩ Ｉ １１のとき、Ｐ点が
１１０”になり、ＰＭＱＳ６３がオフ、ＮＨＱＳ ｌ
６ 、 ＮＭＯＳ６４がオンニなり、出力Ｃは８ＭＯ５
１６と８ＭＯ５６４の基板効果があるので＋Ｖ−Δｖ２
まで上昇する。Next, when inputs A and B are both II I 11, point P becomes 110'', PMQS63 is off, and NHQS l
6, NMOS64 is turned on, output C is 8MO5
Since there is a substrate effect of 16 and 8MO564, +V-Δv2
rises to.
され、′１”になる。and becomes '1'.
本発明によれば、ＥＯＲ，ＥＮＯＲ回路は夫々、６素子
で実現でき、しかも、出力レベルにオフセットが無いた
め、集積回路の高集積、低消費電力化に効果大である。According to the present invention, each of the EOR and ENOR circuits can be realized with six elements, and since there is no offset in the output level, it is highly effective in achieving high integration and low power consumption of integrated circuits.
第１図は本発明のＥＯＲ回路図、第２図は本発明のＥＮ
ＯＲ回路図、第３図は従来のＦＯＲ回路図、第４図は従
来のＥＮＯＲ回路図、第５図は従来の改良されたＦＯＲ
回路図、第６図は従来の改良された皐１図
も２図
十ｖ
士ＶFig. 1 is an EOR circuit diagram of the present invention, and Fig. 2 is an EN circuit diagram of the present invention.
OR circuit diagram, Figure 3 is a conventional FOR circuit diagram, Figure 4 is a conventional ENOR circuit diagram, and Figure 5 is a conventional improved FOR circuit diagram.
The circuit diagram, Figure 6, is the conventional improved version.
Claims (1)
して出力とし、夫々のゲートを共通接続して第１の入力
とし、前記第１のＰＭＯＳのソースを第２の入力に接続
し、第２のＮＭＯＳのソースを前記第２の入力の反転出
口に接続した排他的ＯＲ回路において、前記第１の入力
と前記出力の間に夫々のソースおよびドレインが接続さ
れる第２のＰＭＯＳと第２のＮＭＯＳを設け、前記第２
のＰＭＯＳのゲートは前記第２の入力に、前記第２のＮ
ＭＯＳのゲートは前記第２の入力の反転出力に接続する
ことを特徴とするＣＭＯＳ論理回路。 ２、第１のＰＭＯＳと第１のＮＭＯＳのドレインを接続
して出力とし、夫々のゲートを共通接続して第１の入力
とし、前記第１のＰＭＯＳのソースを第２の入力の反転
出力に接続し、第１のＮＭＯＳのソースを前記第２の入
力に接続した排他的ＮＯＲ回路において、前記第１の入
力と出力の間に、夫々のソースおよびドレインが接続さ
れる第２のＰＭＯＳと第２のＮＭＯＳを設け、前記第２
のＮＭＯＳのゲートは前記第２の入力の反転出力に接続
し、前記第２のＮＭＯＳのゲートは前記第２の入力に接
続したことを特徴とするＣＭＯＳ論理回路。[Claims] 1. The drains of the first PMOS and the first NMOS are connected as an output, the gates of each are commonly connected as the first input, and the source of the first PMOS is connected as the second input. and a source of a second NMOS is connected to an inverting outlet of the second input, the respective sources and drains being connected between the first input and the output. a second PMOS and a second NMOS;
The gate of the PMOS of
A CMOS logic circuit characterized in that a gate of the MOS is connected to an inverted output of the second input. 2. The drains of the first PMOS and the first NMOS are connected as an output, the gates of each are commonly connected as a first input, and the source of the first PMOS is an inverted output of the second input. and a second PMOS and a second PMOS whose respective sources and drains are connected between the first input and the output. 2 NMOS is provided, and the second
A gate of the NMOS is connected to an inverted output of the second input, and a gate of the second NMOS is connected to the second input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59216259A JPH0622328B2 (en) | 1984-10-17 | 1984-10-17 | Semiconductor integrated circuit device having CMOS logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59216259A JPH0622328B2 (en) | 1984-10-17 | 1984-10-17 | Semiconductor integrated circuit device having CMOS logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6195617A true JPS6195617A (en) | 1986-05-14 |
| JPH0622328B2 JPH0622328B2 (en) | 1994-03-23 |
Family
ID=16685748
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59216259A Expired - Lifetime JPH0622328B2 (en) | 1984-10-17 | 1984-10-17 | Semiconductor integrated circuit device having CMOS logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0622328B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01292912A (en) * | 1988-05-19 | 1989-11-27 | Nec Corp | Logic circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5219058A (en) * | 1975-08-04 | 1977-01-14 | Nippon Telegr & Teleph Corp <Ntt> | Exclusive logical sum circuit |
| JPS5649022A (en) * | 1979-09-25 | 1981-05-02 | Sumitomo Chem Co Ltd | Production of carbon fiber tow |
-
1984
- 1984-10-17 JP JP59216259A patent/JPH0622328B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5219058A (en) * | 1975-08-04 | 1977-01-14 | Nippon Telegr & Teleph Corp <Ntt> | Exclusive logical sum circuit |
| JPS5649022A (en) * | 1979-09-25 | 1981-05-02 | Sumitomo Chem Co Ltd | Production of carbon fiber tow |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01292912A (en) * | 1988-05-19 | 1989-11-27 | Nec Corp | Logic circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0622328B2 (en) | 1994-03-23 |
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