JP2003273724A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of initializing a node for providing an output signal of a level converter to a required level when a power supply is turned on. <P>SOLUTION: The semiconductor integrated circuit device is provided with the level converter 6 and two capacity elements N10, C0. The level converter 6 receives an input signal, converts the input signal into a signal in which voltage amplitude is larger than that of the input signal and applies the converted signal to a node D3. The capacity element N10 is connected to the node D3 and the capacity element C0 is connected to the capacity element N10 in series. The capacity element N10 is constituted of a MOS transistor in which a gate is connected to the node D3 and source and drain are connected to the capacity element C0 in common. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a level converter for converting an input signal into a signal having a larger voltage amplitude.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor processing technology, the number of transistors that can be integrated in one chip in a semiconductor integrated circuit device has increased dramatically in recent years. In order to suppress power consumption due to the increase in the number of integrated transistors,
Reduction of power supply voltage is inevitable. MOS (meta), which is one of the most widely used field effect transistors at present
In the case of transistors, the minimum processing dimensions are 0.25 μm, 0.18 μm, 0.15 μm,
The power supply voltage is 2.5V, 1.8V,
It has dropped to 1.5V. Since these power supply voltages are used in the core of the integrated circuit, they are called the power supply voltage VDD of the core circuit section.

On the other hand, the power supply voltage of the interface section provided for exchanging signals with other chips is irrespective of the progress of the process technology, and the power supply voltage V of the core circuit section is used.
The power supply voltage VDDH having a constant value higher than DD is set. Currently, 3.3V is common. Not all chips on the board are manufactured with state-of-the-art process technology, and changing interface standards causes a lot of confusion. The most advanced process transistors used in the core are:
It cannot be used with a power supply voltage of 3V. Although the performance deteriorates, the transistor in the interface section has a larger gate oxide film thickness than the transistor in the core section to increase the gate breakdown voltage.

When using two or more kinds of power supply voltages in this way, a level converter (level shifter) for converting the potential amplitude of a signal is required between the circuit blocks using the respective power supply voltages. FIG. 11 shows a semiconductor integrated circuit device including a conventionally known level converter. The high level of the signal Din is the power supply voltage VDD level,
It is a digital signal whose low level is the ground voltage GND level, and is generated in the core circuit unit 2. Core circuit section 2
Generates two sets of two signals which are logically complementary to each other based on the signal Din via the logic gates IN0, IN1, IN2, G0 and G1. The signal Din
Has the same voltage amplitude as. The level converter 16 is an NMOS
The gate electrodes of the transistors N0 and N1 receive the complementary signals of one set, and the level converter 18 receives the complementary signals of the other set by the gate electrodes of the NMOS transistors N2 and N3.

The same logic is input to the gates of the NMOS transistors N0 and N2, and the NMOS transistors N1 and N2
Since the reverse logic is input to the gate of N3, the level converters 16 and 18 output signals having the same logic level from the nodes D1 and D2 and swinging between the power supply voltage VDDH and the ground potential GND. To do. Level converter 16, 18
The PMOS transistor PD and the NMOS transistor ND of the driver unit 10 are complementarily turned on according to the signal output from the driver unit 10.

When the enable signal EN indicates a high level, a signal Dout having the same logic as the signal Din but having a potential amplitude larger than that of the signal Din according to the operation described above.
Appears at node 23. When the enable signal EN indicates the low level, the PMOS transistor PD and the NMOS transistor ND of the driver unit 10 are turned off at the same time, and the node 23 is in the high impedance state.

[0007]

When there are two or more types of power supplies for the integrated circuit device, the PMOS transistor PD may be turned on when the power is turned on, particularly depending on the order in which the power is turned on.
And the NMOS transistor ND may be turned on at the same time. When the power supply voltage is applied to the external power supply terminal of the semiconductor integrated circuit device, the power supply node inside the device rises from the ground voltage level and is set to the power supply voltage level.

When the power supply voltage VDDH is set in the core circuit section 2 and then the power supply voltage VDDH is set in the interface section 4, there is no problem. Since the logic levels of the two signal pairs supplied from the core circuit unit 2 to the interface unit 4 are set first, the PMOS transistor PD and the NMOS transistor ND are not turned on at the same time. Therefore, a current passing through the transistors PD and ND does not occur. However, on the contrary, there is a problem when the power supply voltage VDDH is set in the interface circuit 4 after the power supply voltage VDD is first set in the core circuit section 2.

At the time when the power supply voltage VDDH is set,
Since the gate electrodes of the NMOS transistors N0 and N1 of the level converter 16 are both low level (GND),
The potential of the output node D1 is indefinite and may be set to low level (GND), for example. At the same time, since the gate electrodes of the NMOS transistors N2 and N3 of the level converter 18 are both low level (GND), the potential of the output node D2 is indefinite, and for example, high level (VDD
H) may be set. At this time, the PMOS transistor PD and the NMOS transistor ND are simultaneously turned on until the levels of the signals input to the level converters 16 and 18 are determined. Since the driving power of the transistors PD and ND as an output driver is larger than that of the other transistors, a large amount of current is generated by turning on the PMOS transistor PD and the NMOS transistor ND at the same time. If a large current flows, it may lead to breakage of the wiring or destruction of the semiconductor device.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit device capable of setting a desired value to a node to which a signal converted by a level converter is applied when power is turned on. Another object of the present invention is to provide a semiconductor integrated circuit device which can operate at high speed in normal operation after power is turned on. Still another object of the present invention is to provide a semiconductor integrated circuit device capable of stably operating a circuit connected to the output of the level converter when the power is turned on.

[0011]

A first semiconductor integrated circuit device according to the present invention further includes at least two capacitance elements in addition to the level converter. On the other hand, the first capacitive element sandwiches an insulating film between a conductive portion electrically connected to the first node to which a signal after level conversion by the level converter is provided and the conductive portion. It includes a first semiconductor portion and a second semiconductor portion having a conductivity type different from that of the first semiconductor portion and joined to the first semiconductor portion. The second capacitive element, which is the other one, is connected to the second semiconductor portion of the first capacitive element at the second node which is separated from both the power supply node receiving the power supply voltage and the ground node receiving the ground voltage. Connected in series.

When the power is turned on, the capacitance between the conductive portion and the first semiconductor portion of the first capacitance element sets the first node to about the potential level of the first semiconductor portion. In addition, after the power is turned on, the capacitance between the conductive portion and the second semiconductor portion of the first capacitance element becomes the first capacitance.
A second capacitance element connected in series with the second semiconductor portion to contribute to the capacitance added to the node of
The capacity added to the node is apparently reduced. As a result, in the normal operation after the power is turned on, the operation of the level converter is accelerated due to the decrease in the capacity of the first node. Therefore, high speed operation of the semiconductor integrated circuit device is realized. Preferably, the first semiconductor portion is electrically connected to the ground node, and the second capacitive element is electrically connected between the second node and the ground node.

A second semiconductor integrated circuit device according to the present invention includes, in addition to a level converter, a capacitive element connected to a predetermined node to which a signal level-converted by the level converter is provided. The capacitive element has a conductive portion electrically connected to a predetermined node, a first semiconductor portion sandwiching an insulating film between the conductive portion, and a first semiconductor portion having a conductivity type different from that of the first semiconductor portion. A second semiconductor portion that joins the portion.

When the power is turned on, the first node is set to about the potential level of the first semiconductor portion by the capacitance between the conductive portion and the first semiconductor portion of the first semiconductor portion in the capacitive element. . The second semiconductor portion is connected to a power supply node that receives a power supply voltage supplied as a power supply for the core circuit portion. After the power is turned on, a reverse bias voltage can be applied to the second semiconductor portion with respect to the first semiconductor portion of the capacitive element. As a result, the capacitance between the conductive portion and the first semiconductor portion is reduced, and in normal operation after power is turned on, the capacitance added to a predetermined node is reduced, so that the level converter operates faster.
Therefore, high speed operation of the semiconductor integrated circuit device is realized. The first semiconductor portion may be electrically connected to a ground node, for example.

In the above first and second semiconductor integrated circuit devices, the second semiconductor portion forming the capacitive element is separated with the first semiconductor portion interposed therebetween and is electrically connected to each other in the wiring layer. As a form having two regions, the capacitance element connected to the level converter may be formed of a field effect transistor.

According to a third conductor integrated circuit device of the present invention, in addition to the level converter, a capacitive element having a first electrode to which a certain voltage is applied and a second electrode connected to the first node, And a switch element connected between the first node and the second node to which the signal level-converted by the level converter is provided, and controlling conduction between them.

By controlling this switch element, the capacitance of the capacitance element viewed from the second node can be made apparently variable. When the power is turned on, the second node can be set to the level of the potential applied to the first electrode of the capacitor by turning on the switch element.

In the normal operation after the power is turned on, the capacitance element is separated from the second node or the capacitance element is separated from the second node by turning off the switch element or weakening the on state from when the power is turned on. A resistance is artificially inserted in. This reduces the capacity added to the second node during normal operation, and speeds up the operation of the level converter. Therefore, high speed operation of the semiconductor integrated circuit device is realized.

The switch element includes, for example, a field effect transistor. A semiconductor integrated circuit device includes a core circuit portion that generates a signal to be supplied to a level converter, and a gate electrode of the field effect transistor is electrically connected to a power supply node of a power supply voltage applied to the core circuit portion. on the other hand,
The second electrode of the capacitor may be electrically connected to the power supply node of the power supply voltage applied to the level converter.

A fourth semiconductor integrated circuit device according to the present invention is
It is connected to a first node receiving a first voltage and a second node receiving a second voltage, receives two logically complementary input signals, and has a logically larger voltage amplitude than the two signals. It includes a level converter for converting into two complementary signals and providing them to the third and fourth nodes, respectively, and a capacitive element connected between the first node and the third node. When the power is turned on, the capacitance of the capacitive element is set to about the level of the potential of the first node at the third node where the signal after conversion by the level converter appears.

The semiconductor integrated circuit device further includes one or a plurality of electric fields each electrically connected between the first and second nodes and having the gate connected to the third or fourth node. Includes effect transistors. The field effect transistor constitutes a circuit that performs a predetermined operation such as a logical operation according to the signal output from the level converter.

For the level converter of the form in which the two logically complementary input signals are received and converted into the two logically complementary signals as described above, between the second and fourth nodes. It is possible to set the fourth node to a logic level opposite to that of the third node when the power is turned on without providing a capacitive element that forms a capacitor. Therefore, in the normal operation after the power is turned on, the level converter operates at high speed because the second node does not have the capacity for setting the initial value, and the high speed operation of the semiconductor integrated circuit device is realized.

A fifth semiconductor integrated circuit device according to the present invention is
A first signal that receives two logically complementary first signals, converts them into two logically complementary signals that have a larger voltage amplitude than the two first signals, and supplies the two signals to the first and second nodes, respectively. 1 level converter receives two logically complementary second signals, converts them into two logically complementary signals having a larger voltage amplitude than the two second signals, and respectively converts them into third and fourth signals. A second level converter provided to the node of.
The semiconductor integrated circuit device further includes first and second capacitance elements, the first capacitance element is connected between a fifth node receiving a certain voltage and the first node, and the second capacitance element is the first capacitance element. It is connected between the fifth node and the third node. First
The second capacitance element sets both the first and third nodes receiving the signal converted by the level converter when the power is turned on to about the potential level of the fifth node.

Further, the semiconductor integrated circuit device is connected to the first field effect transistor whose conduction is controlled according to the signal on the second node and the first charge effect transistor, and according to the signal on the fourth node. A second field effect transistor having a conductivity type different from that of the first field effect transistor whose conduction is controlled is included.

When the power is turned on, the initial values are set in the first and third nodes, so that the first and second level converters drive the second and fourth nodes and the first and third nodes. Set the opposite logic level to the node. The potential levels set on the second and fourth nodes are more stable than the potential levels on the first and third nodes set by the capacitive element. By obtaining signals for driving the first and second field effect transistors from the second and fourth nodes, it is possible to correctly set each of the first and second field effect transistors to ON or OFF at power-on. it can. The state of the circuit formed by the first and second field effect transistors is stabilized.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
A description will be given with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals. Embodiment 1. FIG. 1 shows a circuit configuration diagram of a semiconductor integrated circuit device 100 according to the first embodiment. Semiconductor integrated circuit device 100 in which integrated circuit is formed on a single semiconductor chip
Is a core circuit unit 2 that realizes main functions of the integrated circuit.
And an interface section 4 for converting the digital signal Din generated by the core circuit section 2 into a digital signal having a larger voltage amplitude and supplying it as a signal Vout to another semiconductor chip. The other semiconductor chip is connected to the node 23.

Core circuit portion 2 is connected to a power supply node supplied with power supply voltage VDD and a ground node supplied with ground voltage GND (0V), and operates using power supply voltage VDD as an operating power supply. On the other hand, the interface unit 4 operates using the power supply voltage VDDH, which is higher than the power supply voltage VDD, as the operating power supply. The ground voltage GND is commonly applied to the core circuit unit 2 and the interface unit 4. Therefore, the MOS transistor forming the interface section 4 has a gate breakdown voltage higher than that of the core circuit section 2 by increasing the thickness of the gate oxide film.

The power supply voltages VDD and VDDH may both be generated outside the semiconductor chip and received by the chip. Further, only one of the power supply voltages VDD and VDDH may be generated outside the semiconductor chip. At this time, a voltage generation circuit may be provided inside the chip, and one power supply voltage received from the outside may be used to generate the other power supply voltage.

In this semiconductor integrated circuit device 100, when the enable signal EN is at high level (VDD), the signal D
in increases the voltage amplitude and is output from the node 23. When the enable signal EN is at low level (GND), the node 23 is in a high impedance state. Therefore, the core circuit unit 2 includes the inverters IN0, IN1, IN2.
And 2-input logic circuits G0 and G1. The logic circuit G0 inputs the signal Din on the node 21 and the enable signal EN on the node 22 and outputs its NAND logic. The inverter IN1 inverts the logic output from the logic circuit G0. The inverter IN0 inverts the logic of the enable signal EN. The logic circuit G1 has a signal Din and an inverter I.
It outputs NOR logic with the output of N0. Inverter IN
2 inverts the logic output from the logic circuit G1. The outputs of the inverters IN0 to IN2 and the logic circuits G0 and G1 are all digital signals with the power supply voltage VDD at the high level and the ground voltage GND at the low level.

When the enable signal EN is at high level,
The logic signal G0 outputs the inverted logic of the signal Din, and the inverter IN1 outputs the same logic as the signal Din. The logic circuit G1 outputs the inverted logic of the signal Din, and the inverter IN
2 outputs the same logic as the signal Din. When the enable signal EN is at low level, the logic signal G0 is at high level, the inverter IN1 is at low level, regardless of the signal Din.
The logic circuit G1 outputs a low level and the inverter IN2 outputs a high level.

The interface section 4 comprises two level converters 6 and 8 and a driver section 10. Each of level conversion units 6 and 8 is connected to power supply node D10 receiving power supply voltage VDDH and ground node D11 receiving ground voltage GND, and converts an input signal into a signal having a voltage amplitude larger than the signal. In this embodiment, the level converter receives two signals that are logically complementary to each other and provides two signals that are logically complementary to each other and has a voltage amplitude larger than these signals to predetermined two nodes. belongs to.

The level converter 6 includes PMOS transistors P0 and P1 and NMOS transistors N0 and N1. The sources of the PMOS transistors P0 and P1 are commonly connected to the power supply node D10 and are connected to the power supply voltage VDDH.
Receive. The drain of the PMOS transistor P0 and PM
The gate of the OS transistor P1 is connected to the node D3. The drain of the PMOS transistor P1 and the PMOS
The gate of the transistor P0 is connected to the node D1. The sources of the NMOS transistors N0 and N1 are commonly connected to the ground node D11 and receive the ground voltage GND. The drains of the NMOS transistors N0 and N1 are nodes D3 and D1, respectively, and the PMOS transistor P
0 and the drains of P1 are connected respectively.

The level converter 6 receives two signals, which are logically complementary to each other and which swing between the power supply voltage VDD and the ground voltage GND, at the gates of the NMOS transistors N0 and N1, respectively. When a high level and a low level are applied to the gates of the transistors N0 and N1, respectively, N
The MOS transistor N0 turns on and the NMOS transistor N1 turns off. The potential of the node D3 drops and the PMOS
The transistor P1 is turned on. On the other hand, the potential of the node D1 rises to turn off the PMOS transistor P0. Therefore, the potentials of the nodes D1 and D3 are respectively the power supply voltage VDD.
It becomes H and the level of the ground voltage GND.

On the contrary, when low level and high level are applied to the gates of the transistors N0 and N1, respectively, NM
The OS transistor N1 turns on and the NMOS transistor N
0 turns off. The potential of the node D1 drops and turns on the PMOS transistor P0. On the other hand, the potential of the node D3 rises to turn off the PMOS transistor P1. Therefore, the potentials of the nodes D1 and D3 are the ground voltage GND,
It becomes the level of the power supply voltage VDDH.

The level converter 8 includes PMOS transistors P2 and P3 and NMOS transistors N2 and N3. The sources of the PMOS transistors P2 and P3 are commonly connected to the power supply node D10 and are connected to the power supply voltage VDDH.
Receive. The drain of the PMOS transistor P2 and PM
The gate of the OS transistor P3 is connected to the node D4. The drain of the PMOS transistor P3 and the PMOS
The gate of the transistor P2 is connected to the node D2. The sources of the NMOS transistors N2 and N3 are commonly connected to the ground node D11 and receive the ground voltage GND. The drains of the NMOS transistors N2 and N3 are nodes D4 and D2, respectively, and the PMOS transistor P
2 and the drains of P3, respectively.

The level converter 8 receives two signals which are logically complementary to each other and which swing between the power supply voltage VDD and the ground voltage GND, at the gates of the NMOS transistors N2 and N3, respectively. When a high level and a low level are given to the gates of the NMOS transistors N2 and N3 by the same operation as the level converter 6, the node D
The potentials of 4 and D2 become the levels of the ground voltage GND and the power supply voltage VDDH, respectively, and the NMOS transistors N2 and
When the low level and the high level are applied to the gate of N3, the potentials of the nodes D4 and D2 become the levels of the power supply voltage VDDH and the ground voltage GND, respectively.

As complementary signals supplied to the level converters, the gates of the NMOS transistors N0 and N1 are supplied with the logic circuit G0 and the output of the inverter IN1, respectively, and the gates of the NMOS transistors N2 and N3 are supplied with the logic circuit G1. The output of the inverter IN2 is given to each. Since the voltage VDD provided as a high level to the gates of the NMOS transistors N0 to N3 is higher than the threshold voltage Vthn of the NMOS transistors N0 to N3,
It is quite possible to turn on these NMOS transistors. Therefore, in the PMOS transistors P0 to P3,
The gate of the PMOS transistor connected to the drain of the turned-on NMOS transistor has the ground voltage GN.
Can drive up to D.

The driver unit 10 includes inverters IN3 to IN3.
It has N6, a PMOS transistor PD, and an NMOS transistor ND. The level converter 6 is provided to drive ON / OFF of the PMOS transistor PD, and the node D1 is connected to the gate of the PMOS transistor PD via the inverters IN3 and IN4 connected in series.
The level converter 8 is provided to drive ON / OFF of the NMOS transistor ND, and the node D2 is connected to the gate of the NMOS transistor ND via the inverters IN5 and IN5 connected in series. Inverter IN3
~ IN6 are all power supply voltage VDDH and ground voltage GND
Therefore, the high level of these outputs indicates the power supply voltage VDDH, and the low level thereof indicates the ground voltage GND.

The sources of the PMOS transistor PD and the NMOS transistor ND are connected to the power supply node D10 and the ground node D11, respectively, receive the power supply voltage VDDH and the ground voltage GND, and their drains are connected to each other at the node 23. The signal Vout is obtained from the node 23. When the node D1 is at high level, the PMOS transistor PD is turned off, and when it is at low level, it is turned on. When the node D2 is at low level, the NMOS transistor ND is turned off, and when it is at high level, it is turned on. The MOS transistors PD and ND are drive transistors for transmitting signals to other semiconductor chips, and have a larger current drive capability than the other transistors forming the interface section 4.

With the above configuration, when the enable signal EN is at the high level, the node D1 outputs the logic opposite to the signal Din, and the node D2 outputs the same logic as the signal Din. Therefore, when the signal Din is at high level, the PMOS
Since the transistor PD is turned on and the NMOS transistor is turned off, the signal Vout becomes the high level of the power supply voltage VDDH. On the other hand, when the signal Din is low level, P
Since the MOS transistor PD is turned off and the NMOS transistor ND is turned on, the signal Vout is the ground voltage GND.
Becomes the low level. When the enable signal EN is at low level, the nodes D1 and D2 are at high level and low level, respectively, regardless of the signal Din. Therefore PMOS
Both the transistor PD and the NMOS transistor ND are turned off.

The semiconductor integrated circuit device 100 further includes a PM
It includes OS transistors P10 and P11, NMOS transistors N10 and N11, and capacitors C0 and C1.
The PMOS transistor P10 is a capacitive element connected between the nodes D1 and D10 in order to set the node D1 to a high level when the interface section 4 is powered on. The gate of the PMOS transistor P10 is the node D1.
And the source and drain are connected to the power supply node D10.

The NMOS transistor N10 is a capacitive element connected between the nodes D3 and D11 to set the node D1 to a low level when the interface section 4 is powered on. The gate of the NMOS transistor N10 is connected to the node D3, and the source and drain of the NMOS transistor N10 are connected to the node D5.
Commonly connected to. The capacitor C0 is a capacitive element provided to reduce the capacitance between the node D3 and the ground node D11 in the normal operation after the interface unit 4 is powered on. One electrode of the capacitor C0 is connected to the source and drain of the NMOS transistor N10 at the node D5, and the other electrode is connected to the ground node D11.

The PMOS transistor P11 is a capacitive element connected between the nodes D4 and D10 to set the node D4 to a high level when the interface section 4 is powered on. The gate of the PMOS transistor P11 is connected to the node D4, and the source and drain are the power supply node D
10 are commonly connected.

The NMOS transistor N11 is a capacitive element connected between the nodes D2 and D11 to set the node D2 to a low level when the interface section 4 is powered on. The gate of the NMOS transistor N11 is connected to the node D2, and the source and drain thereof are the node D6.
Commonly connected to. The capacitor C1 is a capacitive element provided to reduce the capacitance between the node D2 and the ground node D11 in the normal operation after the interface section 4 is powered on. One electrode of the capacitor C1 is connected to the source and drain of the NMOS transistor N11 at the node D6, and the other electrode is connected to the ground node D11.

Each of the nodes D5 and D6 is a power supply node D
10 and the ground node D11,
It is in a so-called floating state. Moreover, although only a part thereof is illustrated, the NMOS transistors N0 to N3,
The back gates (substrates) of N10 and N11 are commonly connected to the ground node D11 and supplied with the ground voltage GND.
The back gates (substrates) of the MOS transistors P0 to P3, P10 and P11 are commonly connected to the power supply node D10 and supplied with the power supply voltage VDDH.

FIG. 2 shows that NM with respect to the potential of the node D3.
The relationship of the capacitance Cg between the nodes D3 and D11 obtained by the OS transistor N10 and the capacitor C0 is shown. The capacitance between the node D3 and the ground node is formed by the capacitance Ci between the gate and the substrate of the NMOS transistor N10 until the potential of the node D3 exceeds the threshold voltage Vthn (about 0.8V) of the NMOS transistor N10. To be done. The capacitance Ci decreases as the potential of the node D3 increases. This is because the depletion layer spreads on the substrate below the gate of the NMOS transistor N10.

When the potential of the node D3 exceeds the threshold value Vthn, a channel is formed under the gate of the NMOS transistor N10. Therefore, the capacitance Cg is equal to the capacitance Cd between the gate of the NMOS transistor N10 and the source / drain capacitance. It is formed by a capacitance (= Cd · C0 / (Cd + C0)) which is connected in series with the capacitance C0 of the capacitor C0. Since Cd >> C0 is set in this embodiment, the capacitance C
g can be regarded as approximately C0. NMOS for node D2
The relationship of the capacitance Cg between the node D2 obtained by the transistor N11 and the capacitor C1 and the ground node D11 is the same as that in FIG. 2, and detailed description thereof will be omitted.

Next, the NMOS transistors N10 and N11 and the PMOS transistors P10 and P when the power is turned on.
11 and the operation of the capacitors C0 and C1 will be described. Before both the core circuit unit 2 and the interface unit 4 are powered on, all the gates of the NMOS transistors N0 to N3 are at the ground voltage GND level, and the NMOS transistor N0.
The source and drain of each of N10 and N11 are also at the ground voltage G.
It is the ND level.

Consider a case where the interface section 4 is powered on earlier than the core circuit section 2. During the process in which the power supply node D10 rises to the power supply voltage VDDH in the level converter 6, the charges injected into the node D3 are used to charge the capacitance Cg between the node D3 and the ground node D11. It can be suppressed. On the other hand, PMOS
Depending on the capacity of the transistor P10, the power supply node D10
The potential of the node D1 also rises as the potential of V rises from 0V. Depending on the capacity of the transistors P10 and N10,
The potential of the node D3 becomes lower than that of the node D1. This potential difference acts to turn off the PMOS transistor P0 and turn on the PMOS transistor P1. This action further widens the potential difference between the nodes D1 and D3. As a result, the nodes D1 and D3 reach a high level equivalent to the power supply voltage VDDH and a low level equivalent to the ground voltage GND, respectively.

Since the capacitance Cg is set such that the potential of the node D3 at power-on does not exceed the threshold voltage Vthn of the NMOS transistor N10 through simulation or the like, the NMOS transistor N1 at power-on is set.
The capacitance Cd between the gate of 0 and the source and drain is small. Therefore, the capacitance Ci between the gate substrates of the NMOS transistor N10 contributes to the capacitance Cg when the power is turned on. The capacitance Ci can be set by adjusting the area of the gate of the NMOS transistor N10.

In the level converter 8, the power supply node D10
In the process of rising to the power supply voltage VDDH, the charges injected into the node D2 are used to charge the capacitance Cg between the node D2 and the ground node D11, so that the potential rise of the node D2 can be suppressed. On the other hand, the PMOS transistor P11
With the capacitance of, the potential of the node D4 rises as the potential of the power supply node D10 rises from 0V. The potential of the node D2 becomes lower than that of the node D4 due to the capacitance of the transistors P11 and N11. This potential difference acts to turn off the PMOS transistor P3 and turn on the PMOS transistor P2, further widening the potential difference between the nodes D1 and D3. As a result, the nodes D2 and D4 are connected to the ground voltage GND.
It reaches a corresponding low level and a high level corresponding to the power supply voltage VDDH, respectively.

Since the capacitance Cg is set so that the potential of the node D2 at power-on does not exceed the threshold voltage Vthn of the NMOS transistor N11 through simulation or the like, the NMOS transistor N1 at power-on is set.
The capacitance Cd between the 1 gate and the source and drain is small. Therefore, the capacitance Ci between the gate substrates of the NMOS transistor N11 mainly contributes to the capacitance Cg when the power is turned on.
Ci can be set by adjusting the area of the gate of the NMOS transistor N11.

Since the high level and the low level are set to the nodes D1 and D2, respectively, the MOS transistors PD and ND are turned off, and the MOS transistor P is turned off.
A large current passing through D and ND does not occur.

When the core circuit section 2 is powered on earlier than the interface section 4, the transistors PD,
Since a potential at which ND is not turned on at the same time is determined in the gates of the NMOS transistors N0 to N3, the transistor P
The problem of large current due to turning on D and ND at the same time does not occur.

Core circuit section 2 and interface section 4
At the time of normal operation after both are powered on, the gates of the NMOS transistors N0 and N1 in the level converter 6 are low level (GND) and high level (V) respectively.
DD) is applied, the node D3 is forcibly charged to a high level (VDDH) regardless of the added capacitance Cg, and the node D1 is forcibly charged to a low level (VDDH) regardless of the added capacitance of the PMOS transistor P10. It is discharged to GND). The high level (VDD) and the low level (G) are applied to the gates of the NMOS transistors N0 and N1, respectively.
When ND) is given, the nodes D3 and D1 are charged and discharged to the opposite low level (GND) and high level (VDDH), respectively.

When the signal Vin changes from the low level to the high level, the node D3 changes from 0V to VDDH, but as can be seen from FIG. 2, the threshold voltage Vthn to VDDH of the node D3 changes due to the presence of the capacitor C0. The capacity Cg is small. The dotted line shown in FIG. 2 represents the capacitance Cg when the capacitor C0 is deleted and the source and drain of the NMOS transistor N10 are connected to the ground node D11. When the potential of the node D3 is between 0 V and Vthn, the capacitance Cg is the same as when the capacitor C0 is present.
The capacitance Cd is between the gate and the source and drain of the transistor N10. The size of the capacitance Cd is about the same as the capacitance Ci when the potential of the node D3 is 0V. In the level converter 6 of FIG. 1, the capacitance Cg when the threshold voltage Vthn or more is applied to the gate of the NMOS transistor N10 is smaller than that when the capacitor C0 is not present. The amount of electric charge charged to the node D3 is small and the charging time to the node D3 is short. Therefore, the operation of the level converter 6 is speeded up.

FIG. 3 shows how the node D3 changes from low level (0 V) to high level (VDDH) with respect to time. In the case of the present embodiment in which the solid line includes the capacitor C0, the broken line omits the capacitor C0 and the source and drain of the NMOS transistor N10 are connected to the ground node D
11 shows the case of connecting to 11.

The potential starts to change at time t0, and the change in potential of node D3 is the same whether or not capacitor C0 is present until time t1 when threshold voltage Vthn is reached. However, when the capacitor C0 exists, the capacitance Cg sharply decreases at the threshold voltage Vth as compared with the case where the capacitor C0 does not exist. Therefore, when the potential of the node D3 exceeds the threshold voltage Vth, the potential changes rapidly. As shown in the figure, the time required for the potential of the node D3 to reach the voltage VDDH is shortened by the time Δt when the capacitor C0 is present as compared with the case where the capacitor C0 is not present, and the rising characteristic is improved.

Even when the signal Din changes from the high level to the low level and the potential of the node D3 changes from VDDH to 0V, the potential of the node D3 changes from VDDH to Vt.
The capacity Cg up to hn is small. The discharge time from the node D3 becomes shorter. Due to the presence of the capacitor C0, the node D3 reaches the low level quickly, and the falling characteristic is improved. Further, the capacitor C1 in the level converter 8 operates in the same manner as the capacitor C0, and thus detailed description of the operation is omitted. Since the capacitor C1 shortens the charging / discharging time to the node D2, the level converter 8 can be operated at high speed.

The capacitors C0 and C1 are composed of, for example, MOS transistors. FIG. 4A shows a circuit configuration example of the capacitor C0. The capacitor C0 is composed of an NMOS transistor N20, and its drain is an NMOS
It is connected to the source and drain of the transistor N20, and its source and gate are connected to the ground node D11 and receive the voltage GND.

The sectional structure is shown in FIG. P
An n-type semiconductor impurity diffusion layer 31, on an n-type semiconductor substrate 30,
32 and 33 are formed separately from each other. Diffusion layer 31,
A conductive layer 34 of polysilicon is formed on a p-type semiconductor portion sandwiched between 32 and joined to each other with a gate insulating film sandwiched therebetween, and a p-type sandwiched between diffusion layers 32 and 33 and joined to each other. A conductive layer 35 of polysilicon is formed on the semiconductor portion with a gate insulating film interposed therebetween. The conductive layer 34 is electrically connected to the node D3. The metal wiring layers 36 and 37 are formed on the substrate 2
0 is formed in the interlayer insulating layer, and the wiring layer 36 is the diffusion layer 3
1 and 32 are electrically connected. The metal wiring layer 37 electrically connects the conductive layer 35 and the diffusion layer 33. Wiring layer 3
Ground voltage GND is applied to 7 and the substrate 30.

The conductive layer 34 and the diffusion layer 31 serve as the gate and drain of the NMOS transistor N10,
The conductive layer 35 and the diffusion layer 33 are the NMOS transistor N2.
0 becomes the gate and the source, respectively. The diffusion layer 32 is N
The source of the MOS transistor N10 and the drain of the NMOS transistor N20 are common. The n-type inversion layer is not formed in the p-type semiconductor portion below the conductive layer 35 to which the ground voltage GND is applied, and the transistor N20 is always off.

When the parasitic capacitance between the gate and drain of the NMOS transistor N20 is Cgd and the parasitic capacitance between the substrate and drain is Cb, the sum (Cgd + Cb) of these is the capacitance value of the capacitor C0. The capacitor C1 is also composed of the NMOS transistor N20 of FIG.
The S transistor N11 has the same configuration as the NMOS transistor N10.

If necessary, one or both of the diffusion layer 31 and the wiring layer 36 may be deleted. For example, in FIG.
As shown in (a), the diffusion layer 32 is formed into the element isolation oxide film 3
The conductive layer 34 is formed on the surface of the semiconductor substrate 30 between 8 and 39, and the conductive layer 35 is formed on the p-type semiconductor portion between the isolation oxide film 38 and the diffusion layer 32 and the isolation oxide film 38. It is formed on the p-type semiconductor portion between isolation oxide film 39 and diffusion layer 32 and isolation oxide film 38. Conductive layer 34 and substrate 3
The capacitance between 0, the capacitance between the conductive layer 34 and the diffusion layer 32, the capacitance between the conductive layer 34 and the diffusion layer 32, and the capacitance between the diffusion layer 32 and the substrate 30 are respectively the above-mentioned capacitances Ci, Cd, and Cg.
d and Cb.

Capacitors C0 and C1 are shown in FIG.
As shown in, the wiring layer 36 connecting the diffusion layers 31 and 32 is formed.
Is formed in the interlayer insulating layer, and is arranged so as to face the wiring layer 36 with a part of the insulating portion interposed therebetween, and the ground voltage GN
It may be configured by another wiring layer 40 of a metal receiving D. The capacitance of the capacitors C0 and C1 is the capacitance between the wiring layer 36 and the wiring layer 40. The wiring layer 37 may be formed in a layer above the wiring layer 36 as shown in the drawing, or may be formed adjacent to the wiring layer 36 by a layer having the same height as the wiring layer 36, though not shown.

Further, the capacitors C0 and C1 are shown in FIG.
As shown in, the wiring layer 36 connecting the diffusion layers 31 and 32 is formed.
And a conductive layer 41 of polysilicon which is arranged to face the wiring layer 36 with an interlayer insulating film interposed therebetween and receives the ground voltage GND. Capacitors C0, C
The capacitance of 1 is the capacitance between the wiring layer 36 and the conductive layer 41.

The capacitors C0 and C1 are shown in FIG.
As shown in, the wiring layer 36 may be composed of a conductive layer 42 of polysilicon electrically connected to the diffusion layers 31 and 32, and the substrate 30. The capacitance of the capacitors C0 and C1 is the capacitance between the conductive layer 42 and the substrate 30.

As described above, according to the first embodiment, by connecting the capacitive element to the node where the converted potential amplitude appears in the level converter, the node is set to the logical level desired to be initialized when the power is turned on. Can be set. The logic level to be initialized is determined depending on whether the capacitive element is connected to the power supply node or the ground node. In this example, when the level converter is used to drive a driver that transmits a signal to another semiconductor device, by appropriately determining the logic level to be initialized, the driving force of the driver that configures the driver at power-on Prevents a large current from being unexpectedly generated in a large transistor.

Furthermore, by connecting the gate of the MOS transistor as a capacitive element to the node to be initialized and connecting another capacitive element to the source / drain (diffusion layer),
The capacity of the initialization node can be reduced during normal operation. Therefore, the operation speed of the level converter is improved, and further, the operation of the driver unit 10 is also speeded up.

Embodiment 2. FIG. 6 shows the second embodiment.
2 is a circuit configuration diagram of a semiconductor integrated circuit device 200 according to FIG.
1 is different from that of FIG. 1 in that the capacitors C0 and C1 are removed, and the source and drain of the NMOS transistor N10 and the source and drain of the NMOS transistor N11 are connected to the operating power supply (power supply voltage VDD ) Is commonly connected to the power supply node D12. Others are the same as in FIG.

Consider a case where the interface section 4 is powered on earlier than the core circuit section 2. In the level converter 6, the potential of the power supply node D12 remains 0V at the time when the potential of the power supply node D10 rises to the voltage VDDH. Therefore, the capacitance between the gate of the NMOS transistor N10 and the substrate is equal to that of the ground node D11 and the node D3.
And a potential between the node D3 and the node D3 are suppressed. The PMOS transistor P10 serves as a capacitance between the node D1 and the power supply node D10, and raises the potential of the node D1 as the power supply node D10 rises to the power supply voltage VDDH. This gives the node D the same as in FIG.
1 and D3 reach a high level equivalent to the power supply voltage VDDH and a low level equivalent to the ground voltage GND, respectively.

Since level converter 8 operates similarly to level converter 6, description thereof will not be repeated. Node D
While the potential rise of 2 is suppressed, the potential of the node D4 rises, so that the nodes D2 and D4 reach the low level equivalent to the ground voltage GND and the high level equivalent to the power supply voltage VDDH, respectively. Therefore, the node 23 is in a high impedance state based on the potential levels of the nodes D1 and D2.
When the core circuit unit 2 is powered on earlier than the interface unit 4, for the same reason as in the first embodiment,
The problem of a large current passing through the transistors PD and ND does not occur.

Regarding the normal operation after the power supply to the core circuit section 2 and the interface section 4 is turned on, the NM different from FIG.
Only the operation of the OS transistors N10 and N11 will be described. The rest of the configuration is the same as that of FIG. 1, and since the same operation is performed, its description is omitted.

The power supply voltage VDD is fixedly applied to the power supply node D12, and the sources and drains of the NMOS transistors N10 and N11 are higher than the voltage GND applied to the back gate (substrate) thereof. A so-called back bias effect occurs and the NMOS transistor N1
The threshold voltage Vthnx of 0 and N11 is the normal threshold voltage Vt when the source is applied to the ground voltage GND.
higher than hn.

FIG. 7 shows the NMO with respect to the potential of the node D3.
Nodes D3 and D1 obtained by the S transistor N10
The relationship of the capacitance Cg between the two is shown. NMOS transistor N
The condition for forming a channel in 10 is that the potential of the gate with respect to its source becomes higher than the threshold voltage Vthnx. That is, the potential of the node D3 is (VDD + Vt
hnx) or more, a channel is formed in the NMOS transistor N10, and the capacitance Cg becomes substantially equal to the capacitance Cd between the gate, the source, and the drain. On the other hand, when the potential of the node D3 is smaller than (VDD + Vthnx), no channel is formed and the capacitance Cg is the capacitance Ci between the gate and the substrate.
Is almost equal to. At this time, a reverse bias voltage is applied between the substrate and the source and drain, and the expansion of the depletion layer becomes more remarkable than when the ground voltage GND is applied to the source and drain. Therefore, the capacitance Ci is extremely small.

The broken line in FIG. 7 indicates the NMOS transistor N10.
It represents the capacitance Cg on the assumption that the ground voltage GND is applied to the source and drain of the. The potential of node D3 is 0
When V, the capacitance Cg is smaller in the present embodiment (solid line) than in the case of the wavy line. However, as the potential of the node D3 increases, the reduction rate of the capacitance Cg in this embodiment is significantly smaller than that of the wavy line. Even if the potential of the node D3 exceeds Vthn, the capacitance Cg still continues to decrease in the present embodiment, but in the case of the wavy line, the capacitance Cg rapidly increases and reaches Cd. Only when the potential of the node D3 exceeds VDD + Vthnx, in the present embodiment, the capacitance Cg rapidly increases and reaches Cd.

When the signal Din changes from the low level to the high level, the potential of the node D3 changes from 0V to VDDH. While the potential of the node D3 rises from 0V to (VDD + Vthnx), the capacitance Cg is remarkably small due to the NMOS transistor N10, and the node D3. Charging time is short. Node D
The change from low level to high level at 3 becomes faster. When the signal Din changes from the high level to the low level, the potential of the node D3 changes from VDDH to 0V, but the capacitance Cg is remarkably small while the potential is reduced to (VDD + Vthnx) or 0V, and the discharge time from the node D3 is short. . Therefore, the change from the high level to the low level at the node D3 also becomes faster. Since the NMOS transistor N11 of the level converter 8 also functions similarly to the NMOS transistor N10, detailed description thereof will be omitted.

Thus, in addition to the fact that the node of the level converter can be set to the logic level desired to be initialized by the capacitive element when the power supply of the interface unit 4 precedes that of the core circuit unit 2, Node D3
The level converters 6 and 8 after the power is turned on are improved in the rising characteristic and the falling characteristic of the node D2.
The normal operation of each becomes faster. Furthermore, the driver unit 1
The operation of 0 becomes faster. Further, in this embodiment, the capacitors C0 and C1 are deleted, so that
An integrated circuit device is configured with fewer elements than

Third Embodiment FIG. 8 shows the third embodiment.
3 is a circuit configuration diagram of a semiconductor integrated circuit device 300 according to FIG.
In the first and second embodiments, the operation of the level converter is speeded up by reducing the capacity added to the node that should be set to the low level as the initial value when the power is turned on during the normal operation.
In the present embodiment, conversely, the capacity added to the node to be set to the high level is reduced during the normal operation to speed up the operation of the level converter.

Therefore, this embodiment is different from that of FIG. 1 in that the capacitors C0 and C1 are removed, and the source and drain of the NMOS transistor N10 and the source and drain of the NMOS transistor N11 are connected to the ground node D11. Commonly connected to ground potential GN
Point receiving D, PMOS transistor P10 and node D
1 is newly provided with a PMOS transistor P4 which is a switching element which is connected between the PMOS transistor P11 and the node D4 and which is a switching element which is connected between the PMOS transistor P11 and the node D4.
This is the point where a MOS transistor P5 is newly provided. Others are the same as in FIG.

One of the source and drain of the PMOS transistor P4 is connected to the node D1 and the other is connected to the gate of the PMOS transistor P10. The gate is connected to the power supply node D12 to which the power supply voltage VDD is applied. It is connected to the node P10. Further, one of the source and drain of the PMOS transistor P5 is connected to the node D4, the other is connected to the gate of the PMOS transistor P11, the gate is connected to the power supply node D12, and the substrate (not shown) is connected to the power supply node P10.

When the interface section 4 is powered on earlier than the core circuit section 2, the power supply node D12 is at 0 V after the interface section 4 is powered on and before the core circuit section 2 is powered on. Therefore, the PMOS transistors P4 and P5 are both turned on when the interface section 4 is powered on. Therefore, the PMOS transistors P10 and P11 are electrically connected to the nodes D1 and D4, respectively. PMOS transistors P10 and P11
Is a capacitor connected between the nodes D1 and D4 and the power supply node D10, and the nodes D1 and D4 are set to a high level equivalent to the power supply voltage VDDH by the same operation as that of FIGS. 1 and 6.

On the other hand, NMOS transistors N10 and N11
Constitutes a capacitive element between the nodes D3 and D2 and the ground node, and the nodes D3 and D2 are set to a low level corresponding to the ground voltage GND. When the core circuit unit 2 is powered on earlier than the interface unit 4, the problem of large current passing through the transistors PD and ND does not occur for the same reason as in the first embodiment.

Regarding the normal operation after the power supply to the core circuit section 2 and the interface section 4 is turned on, an MO different from that shown in FIG.
S transistors N10, N11, P4, P5, P10,
Only the operation of P11 will be described. The rest of the configuration is the same as that of FIG. 1, and since the same operation is performed, its description is omitted.

Since the power source voltage VDD is applied to the gates of the PMOS transistors P4 and P5, the current supply capability of the PMOS transistors P4 and P5 is weaker than that when 0V is applied to the gates. The PMOS transistors P4 and P5 are connected to the node D1 and the PMOS transistor P.
10 and between the node D4 and the PMOS transistor P.
The function of the resistance elements respectively connected between 11 and 11 is achieved. The resistance of the resistance element apparently reduces the capacitance of the PMOS transistors P10 and P11 added to the nodes D1 and D4. As a result, the charge and discharge of the nodes D1 and D4 are quickly performed, and the operation speed of the level converters 6 and 8 is increased. Since the rising and falling characteristics of the nodes D1 and D2 to which the driver unit 10 in the subsequent stage is connected are improved, the operation of the driver unit 10 is accelerated.

In FIG. 8, the NMOS transistor N1
0, N11 source and drain are ground node D11
However, as in FIG. 1, the sources and drains of the NMOS transistors N10 and N11 may be connected to the ground node D11 via capacitors. As described in the first embodiment, the capacitance added to the nodes D3 and D2 can be reduced, and the level converters 6 and 8 can operate at higher speed.

Further, as in FIG. 6, in FIG.
The sources and drains of the OS transistors N10 and N11 may be connected to the power supply node D12 of the core circuit unit 2 instead of the ground node D11. The capacitance added to the nodes D3 and D2 can be reduced, and the level converters 6 and 8 can operate at higher speed.

Fourth Embodiment FIG. 9 shows the fourth embodiment.
2 is a circuit configuration diagram of a semiconductor integrated circuit device 400 according to FIG.
In this embodiment, a configuration for setting a desired logic level in the nodes D1 to D4 of the level converter when the interface unit 4 is powered on is realized with a small number of elements. Therefore, the present embodiment is different from that of FIG. 1 in that the capacitors C0 and C1 are deleted.
Source and drain of the OS transistor N10 and NM
The source and drain of the OS transistor N11 are commonly connected to the ground node D11, and the PMOS transistors P10 and P11 are removed. Other configurations are the same as those in FIG.

The NMOS transistors N10 and N11 form a capacitive element connected between the nodes D3 and D2 and the ground node D11, respectively. Before the power is turned on, the nodes D1 to D4 and D10 have a potential of 0V. Core circuit section 2
When the interface section 4 is powered on earlier, the potentials of the nodes D1 to D4 tend to rise from 0V as the potential of the power supply node D10 rises from 0V. However, the NMOS transistors N10 and N11 functioning as capacitance elements suppress the potential rise of the nodes D3 and D2.

The level converter 6 will be described as an example. Since the capacitance of the transistor N10 is charged, the potential of the node D3 is suppressed to the ground voltage GND.
The PMOS transistor P1 continues to be turned on even if the potential of the power supply node D10 rises. The PMOS transistor P1 which is turned on drives the node D1 to raise its potential.
Therefore, the capacitive element added between the node D1 and the power supply node D10 is not required. In addition, the PMOS transistor P0 is turned off due to the rise in the potential of the node D1.
No more charges are supplied to the node D3 via the transistor P0.

By the above operation, the node D3 is set to the low level corresponding to the ground voltage GND, and the node D1 is set to the high level corresponding to the power supply voltage VDDH. The level converter 8 also operates in the same manner as the node D2.
Is set to a low level corresponding to the ground voltage GND, and a high level corresponding to the power supply voltage VDDH is set to the node D4. When the core circuit unit 2 is powered on earlier than the interface unit 4, the problem of large current passing through the transistors PD and ND does not occur for the same reason as in the first embodiment.

A logic circuit for performing a predetermined logical operation operation based on the output of the level converter 6 is connected to the node D1.
Specifically, one or a plurality of Ms forming a logic circuit
The gates of the OS transistors are commonly connected to the node D1. Each MOS transistor is connected in series or indirectly between the power supply node D10 and the ground node D11 to form a current path between the nodes. For example, in FIG. 9, this circuit corresponds to the inverter IN3. Inverter IN3
Includes a PMOS transistor and an NMOS transistor connected in series between the power supply node D10 and the ground node D11, and the node D1 is connected to the gates of both MOS transistors.

In this embodiment, the elements connected to the node D1 are only the MOS transistors included in the level converter 6 and one or a plurality of MOS transistors forming the logic circuit in the subsequent stage. A power supply node D10 for the purpose of initializing the node D1 when the power is turned on.
It is not necessary to provide a capacitive element connected between the node and the node D1. Unlike the first to third embodiments, since the capacitance added to the node D1 is small, the rising and falling characteristics of the nodes D1 and D3 are improved and the high speed operation of the level converter 6 is improved in the normal operation after the power is turned on. To be achieved.

The node D4 is connected to the power supply node D10.
The element connected to is only the transistor included in the level converter 8. It is not necessary to provide a capacitive element connected between the power supply node D10 and the node D4 for the purpose of initializing the node D4 when the power is turned on. Node D4
Since the capacitance added to is small, in the normal operation after the power is turned on, the rising and falling characteristics of the nodes D4 and D2 are improved, and the high speed operation of the level converter 8 is achieved. Further, since there is no capacitive element added to the node to be initialized to a high level when the power is turned on, the semiconductor integrated circuit device 400
The number of elements can be reduced and the area can be reduced.

Further, as in FIG. 6, in FIG.
The source and drain of each of the S transistors N10 and N11 are not connected to the ground node D11 but to the power supply node of the core circuit unit 2 to which the power supply voltage VDD is applied, so that the high speed operation of the level converters 6 and 8 is further realized. It is possible.

Further, by applying the configurations of the NMOS transistor N10 and the capacitor C0 and the configurations of the NMOS transistor N11 and the capacitor C1 shown in FIG. 1 to the nodes D3 and D2 of FIG. 9, respectively, the level converter 6, 8 high speed operation may be realized.

Embodiment 5. FIG. 10 shows a circuit configuration diagram of a semiconductor integrated circuit device 500 according to the fifth embodiment. 9 differs from that of FIG. 9 in that the NMOS transistor N11 is connected to the node D, an inverter IN7 is further inserted between the node D2 and the inverter IN5, and the output of the logic circuit G1 is applied to the gate of the NMOS transistor N3. This is the point where the output of the applying inverter IN2 is applied to the gate of the NMOS transistor N2. Other configurations are the same as those in FIG.

In the fourth embodiment of FIG. 9, when the interface section 4 is powered on before the core circuit section 2, the node D whose low level should be set as an initial value is set.
Strictly speaking, the respective potentials V (D) of 3 and D2 are set as V (D) = VDDH · Cp / (Cp + Cg). Cg represents the capacitance between the nodes D3 and D2 and the ground node D11 by the NMOS transistors N10 and N11 as described above, and Cp represents the parasitic capacitance between the nodes D3 and D2 and the power supply node D10. The parasitic capacitance includes the capacitance between the gate and the source and the drain of each of the PMOS transistors P0 to P3, the wiring capacitance, and the like. Therefore, the potentials of the nodes D3 and D2 cannot be completely set to 0V and become higher than 0V depending on the capacitance Cp. When the potential becomes several hundred mV, the level converter 8
There may be problems on the side. In FIG. 8, the inverter IN5 of the next stage is driven by the potential of several hundred mV of the node D2,
The leakage current of IN6 increases. This is not preferable because it increases power consumption. Further, when some voltage noise is superimposed on the node D2 and the potential further rises to several hundred mV, the potential of the node D2 may exceed the logical threshold value of the inverter IN5 in the next stage, and the NMOS transistor ND may be turned on. On the other hand, at the nodes D1 and D4 where the high level is set as the initial value, the PMOS transistor P
1 and P2 can drive the nodes to the voltage VDDH, respectively.

In the fifth embodiment, the capacitive element (NMO
One electrode of the S transistor N11) is connected to the node N4 instead of the node D2. When the interface unit 4 is powered on before the core circuit unit 2, the low level is set to the node D4 and the high level is set to the node D2 by the capacity of the NMOS transistor N11. In particular, driven by the PMOS transistor P3, the node D2 is charged to the power supply voltage VDDH. With respect to the nodes D2 and D4, the setting of the logic level is opposite to that in the case of FIG. 9, so the inverter IN7 inverts the logic of the node D2 and supplies it to the inverter IN5. As a result, the logic level given to the inverter IN5 when the power is turned on becomes the same as in FIG.
The NMOS transistor ND is turned off.

As described above, by using the capacitive element (NMOS transistor N11) connected to the ground node to set the node of the level converter at which the signal for driving the driver MOS transistors PD and ND appears to a high level, The driver transistor can be turned off more stably. Further, when the core circuit unit 2 is powered on earlier than the interface unit 4, the problem of large current passing through the transistors PD and ND does not occur for the same reason as in the first embodiment.

Since the inverter IN7 is provided, the device 500 performs the same logical operation as that of the first to fourth embodiments in the normal operation after the core circuit section 2 and the interface section 4 are powered on. NMOS transistor N
The inputs to the gates of 2 and N3 are reversed from the case of FIG.

Similarly to FIG. 6, in FIG. 10, NM
The source and drain of each of the OS transistors N10 and N11 are not connected to the ground node D11 but to the power supply node of the core circuit section 2 to which the power supply voltage VDD is applied, and further high speed operation of the level converters 6 and 8 is realized. It is possible.

Further, by applying the configurations of the NMOS transistor N10 and the capacitor C0 and the configurations of the NMOS transistor N11 and the capacitor C1 shown in FIG. 1 to the nodes D3 and D4 of FIG. 10, respectively, the level converter 6, 8 high speed operation may be realized. Further, like the PMOS transistors P10 and P11 in FIG. 1, capacitance elements for initializing the nodes D1 and D2 to a high level may be added to the nodes D1 and D2, respectively. At that time, as shown in FIG. 8, a switch element may be provided between the capacitive element and the nodes D1 and D2 to be initialized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a semiconductor integrated circuit device 100 according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a characteristic of capacitance in a capacitance element connected to a node whose initial value is set when the power is turned on in the level converter of FIG. 1;

FIG. 3 is an explanatory diagram showing rising characteristics of a node to which a capacitive element is added.

FIG. 4 is a circuit diagram and a structural diagram showing a specific configuration of capacitors C0 and C1.

FIG. 5 is a structural diagram showing another specific configuration of capacitors C0 and C1.

FIG. 6 is a circuit configuration diagram showing a semiconductor integrated circuit device 200 according to a second embodiment of the present invention.

7 is an explanatory diagram showing a characteristic of capacitance in a capacitance element connected to a node to which an initial value is set when the power is turned on in the level converter of FIG. 6;

FIG. 8 is a circuit configuration diagram showing a semiconductor integrated circuit device 300 according to a third embodiment of the present invention.

FIG. 9 is a circuit configuration diagram showing a semiconductor integrated circuit device 400 according to a fourth embodiment of the present invention.

FIG. 10 is a circuit configuration diagram showing a semiconductor integrated circuit device 500 according to a fifth embodiment of the present invention.

FIG. 11 is a circuit configuration diagram showing a semiconductor integrated circuit device according to a conventional technique.

[Explanation of symbols]

2 ... Core part, 4 ... Interface part, 6, 8 ... Level converter, 10 ... Driver part, N10, N11 ... NMO
Capacitance element by S transistor, P10, P11 ... PM
Capacitance element by OS transistor, C0, C1 ... Capacitor (capacitance element), PD, ND ... MOS transistor for driving

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F038 AC03 AC05 BB02 BB08 DF07                       EZ20                 5J055 AX00 AX57 BX41 CX27 DX22                       DX56 DX72 DX83 EX07 EY10                       EZ07 EZ20 EZ25 FX19 FX27                       GX01 GX06 GX07                 5J056 AA11 BB00 CC00 CC21 DD13                       DD29 DD51 EE06 FF07 FF08                       KK02 KK03

Claims (16)

[Claims] 1. A level conversion which is connected to a power supply node receiving a power supply voltage and a ground node receiving a ground voltage, converts a signal into a signal having a voltage amplitude larger than the signal, and provides the converted signal to the first node. A conductive portion electrically connected to the first node, a first semiconductor portion sandwiching an insulating film between the conductive portion, and a conductive type different from that of the first semiconductor portion. A first capacitance element including a first semiconductor portion and a second semiconductor portion joined to the first semiconductor portion, and a second capacitance isolated from both the power supply node and the ground node. A semiconductor integrated circuit device including a second capacitive element connected in series to a second semiconductor portion of the element. 2. The first semiconductor portion is electrically connected to the ground node, and the second capacitive element is connected between the second node and the ground node.
The semiconductor integrated circuit device described. 3. The third capacitor has a third semiconductor portion electrically connected to the second semiconductor portion and a conductivity type different from that of the third semiconductor portion. A fourth semiconductor portion joined to the semiconductor portion, and a conductive portion sandwiching an insulating film between the fourth semiconductor portion and a voltage to which a voltage not forming an inversion layer is applied to the fourth semiconductor portion. The semiconductor integrated circuit device according to claim 1 or 2. 4. The first capacitance element is made of a metal first electrically connected to a second semiconductor portion of the first capacitance element.
3. The semiconductor integrated circuit device according to claim 1, further comprising: a wiring layer and a second conductive layer of metal, which is arranged to face the first wiring layer with an insulator interposed therebetween. 5. The second capacitance element is made of the same material as the metal wiring layer electrically connected to the second semiconductor portion of the first capacitance element and the conductive portion of the first capacitance element. 3. The semiconductor integrated circuit device according to claim 1 or 2, further comprising: a conductive layer which is arranged so as to face the wiring layer with an insulator interposed therebetween. 6. The second capacitance element includes a conductive layer that contains the same material as the conductive portion of the first capacitance element and is electrically connected to the second semiconductor portion, a metal wiring layer, and 3. The semiconductor integrated device according to claim 1, further comprising a conductive portion that has the same material as the conductive portion of the first capacitive element and that is arranged to face the first wiring layer with an insulator interposed therebetween. Circuit device. 7. A core circuit unit, which is connected to a ground node receiving a ground voltage and a first power node receiving a power supply voltage, and generates a first signal having a certain voltage amplitude, and a power supply different from the ground node. A level converter that is connected to a second power supply node that receives a voltage, receives the first signal, converts the second signal into a second signal having a voltage amplitude larger than that of the first signal, and provides the second signal to a predetermined node; And a conductive portion electrically connected to the predetermined node, a first semiconductor portion sandwiching an insulating film between the conductive portion, and a conductive type different from that of the first semiconductor portion. A semiconductor integrated circuit device including a capacitive element including a second semiconductor portion that is electrically connected to the first power supply node while being joined to the semiconductor portion. 8. The semiconductor integrated circuit device according to claim 7, wherein the first semiconductor portion is electrically connected to the ground node. 9. The method according to claim 1, wherein the second semiconductor portion has two regions that are separated by the first semiconductor portion and are electrically connected to each other by a wiring layer. 2. A semiconductor integrated circuit device according to claim 1. 10. A level converter which receives a signal and converts the signal into a signal having a voltage amplitude larger than the signal to provide to the first node, a first electrode to which a voltage is applied, and a second node A semiconductor integrated circuit device, comprising: a capacitor having a second electrode connected to the first node; and a switch element connected between the first node and the second node and controlling conduction between the first node and the second node. 11. A core circuit unit connected to a ground node for receiving a ground voltage and a power node for receiving a power supply voltage, the core circuit unit generating a signal to be applied to the level converter, wherein the switch element has the power supply at its gate terminal. 11. The semiconductor integrated circuit device according to claim 10, wherein the node includes a field effect transistor electrically connected to the node. 12. The level converter is connected to the ground node and another power supply node receiving a different power supply voltage,
The semiconductor integrated circuit device according to claim 10 or 11, wherein the first electrode of the capacitive element is electrically connected to the another power supply node. 13. A first node which receives a first voltage and a second node which receives a second voltage, receives two logically complementary input signals, and receives a voltage amplitude from the two signals. A level converter for converting into two logically complementary signals having a large value and providing them to the third and fourth nodes, respectively, a capacitive element connected between the first node and the third node, And each includes one or more field effect transistors electrically connected between the first and second nodes and having their gates electrically connected to the third or fourth nodes. A semiconductor integrated circuit device in which a capacitive element forming a capacitance is not provided between the second node and the fourth node. 14. The level converter of the first conductivity type, the drain of which is connected to the third node, the gate of which is connected to the fourth node, and the source of which is connected to the first node. Type first field effect transistor, the drain thereof is connected to the fourth node, the gate thereof is connected to the third node, and the source thereof is connected to the first node. A second conductivity type field effect transistor, a drain thereof is connected to the third node, a source thereof is connected to the first node, and a gate thereof is connected to the second node.
A third field effect transistor of the second conductivity type for receiving one of the two input signals, its drain connected to the fourth node, its source connected to the first node, and its gate connected to the second node
14. The semiconductor integrated circuit device according to claim 13, further comprising a fourth field effect transistor of the second conductivity type that receives the other of the two input signals. 15. Received two logically complementary first signals, converted into two logically complementary signals having a voltage amplitude larger than those two first signals, and respectively converted into first and second signals.
A first level converter provided to a node of the two, receives two logically complementary second signals, and converts them into two logically complementary signals having a voltage amplitude larger than the two second signals. A second level converter provided to the third and fourth nodes, respectively, a first capacitance element connected between a fifth node receiving a certain voltage and the first node, the fifth node A second capacitive element connected between the second node and the third node, a first field-effect transistor whose conduction is controlled according to a signal on the second node, and a first charge-effect transistor. A semiconductor integrated circuit device including a second field effect transistor which is connected and has a conductivity type different from that of the first field effect transistor whose conduction is controlled according to a signal on the fourth node. 16. The first level converter of the first conductivity type, the drain of which is connected to the first node, and the gate of which is connected to the second node.
A field effect transistor, the drain of which is connected to the second node, the gate of which is connected to the first node and the source of which is connected to the source of the first field effect transistor. A second conductivity type field effect transistor, the drain of which is connected to the first node, the gate of which receives one of the two first signals, and the source of which is connected to the fifth node. A third field effect transistor of a second conductivity type, the drain of which is connected to the second node, the gate of which receives the other of the two first signals, and the source of which is the fifth node; Fourth of said second conductivity type connected
A second field-effect transistor of the first conductivity type, the drain of which is connected to the third node and the gate of which is connected to the fourth node.
Field-effect transistor, the drain thereof is connected to the fourth node, the gate thereof is connected to the third node, and the source thereof is connected to the source of the fifth field-effect transistor. A sixth conductivity type field effect transistor, the drain of which is connected to the third node, the gate of which receives one of the two second signals, and the source of which is connected to the fifth node. The seventh of the second conductivity type
Field effect transistor of the second conductivity type, the drain of which is connected to the fourth node, the gate of which receives the other of the two second signals and the source of which is connected to the fifth node. Type 8
16. The semiconductor integrated circuit device according to claim 15, further comprising: