WO2007004294A1

WO2007004294A1 - Level converter circuit, control method thereof, and electronic circuit

Info

Publication number: WO2007004294A1
Application number: PCT/JP2005/012398
Authority: WO
Inventors: Sota Sakabayashi
Original assignee: Fujitsu Limited
Priority date: 2005-07-05
Filing date: 2005-07-05
Publication date: 2007-01-11

Abstract

A level converter circuit (2) level-converts a signal used in a circuit of a first power supply (internal power supply circuit (24) generating a voltage Vd1) to a signal used in a circuit of a second power supply generating a different voltage from the first power supply (external power supply circuit (26) generating a voltage Vd2), and outputs the converted signal. A pull-up circuit (18) is provided at an output terminal (16) for the level-converted signal, and pulls up the output terminal (16) to a high voltage (for example, the voltage Vd2) in synchronization with the power-on transient, thereby preventing the occurrence of an unstable output during the power-on period.

Description

Specification

Level converter circuit, control method thereof, and electronic circuit

Technical field

TECHNICAL FIELD [0001] The present invention relates to a level converter circuit that performs level conversion of a signal according to power supplies of different voltages, for example, level conversion of a signal on a low voltage power supply side to a signal on a high voltage power supply side. The present invention relates to a level converter circuit that suppresses the occurrence of indefinite output, a control method thereof, and an electronic circuit.

Background art

In general, for example, when a signal taken out from an LSI (Large Scale Integration) is transmitted to an external circuit as an electronic circuit, a voltage difference is generated between the power supply voltage on the LSI side and the power supply voltage on the external circuit side. If there is, the level must be converted to a signal corresponding to the voltage of the external circuit power supply. Therefore, a level converter circuit for converting to a level corresponding to a voltage is used for an input / output (IZO) circuit used for signal input / output.

[0003] By the way, in an LSI internal circuit, multiple power supplies are used to reduce power consumption. For example, a lower voltage internal power supply for an internal circuit is generated with respect to an external power supply supplied from the outside. By supplying this internal power supply to the internal circuit, the power consumption of the internal circuit can be reduced. However, when a low-voltage power-side signal is transmitted to a high-voltage power-side circuit, it is necessary to perform level conversion to a high-voltage power-side signal.

[0004] A level converter circuit used for such level conversion is provided with a forced pull-up circuit for forcibly pulling up a signal transmission node at a positive high potential, and a one-shot pulse synchronized with an edge at the time of transition of an input signal The signal transmission node is forcibly pulled up by a signal (for example, Patent Document 1), and includes an initialization circuit that conducts when the power is turned on and does not rise on the low-voltage power supply side. There is a type in which a node at a low level is lowered to the ground potential by the initialization circuit or raised to the potential on the high voltage power source side (for example, Patent Document 2).

Patent Document 1: JP 2000-269804 A Patent Document 2: Japanese Patent Laid-Open No. 2003-163590

Disclosure of the invention

Problems to be solved by the invention

[0005] By the way, the conventional power supply sequence of the level converter circuit (different power supply sequence), for example, the high voltage power supply side voltage (the output side voltage of the level converter circuit) rises quickly. If the rise of the voltage (voltage on the input side of the level converter circuit) is slow, the level converter output may become unstable, and the output side circuit that receives the output and the output side circuit, for example, C MOS There is a risk of overcurrent due to through current in the circuit.

[0006] The output indefinite state generated in the level converter circuit will be described with reference to the level converter circuit shown in FIG.

[0007] In the level converter circuit 2, the level of the signal on the first power supply side with the voltage Vdl is converted into the signal on the second power supply side with the voltage Vd2 (in this case, Vd2> Vdl). The level converting unit 4 includes a first transistor Trl, a second transistor Tr2, a third transistor Tr3, and a fourth transistor Tr4. The transistors Trl and Tr2 are P-channel transistors, and the transistors Tr3 and Tr4 are N It is composed of channel transistors. A voltage Vd2 is commonly applied to the sources of the transistors Trl and Tr2, the gate of the transistor Trl is connected to the drains of the transistors Tr2 and Tr4, and the gate of the transistor Tr2 is connected to the drains of the transistors Trl and Tr3. The sources of the transistors Tr3 and Tr4 are grounded and maintained at the ground (Gnd) potential.

[0008] An inverter unit 6 is installed on the gate side of the transistor Tr3, and a signal B (inverted signal ZA) obtained by inverting the signal A received at the input terminal 8 is applied. The inverter unit 6 that generates the inverted signal B includes a fifth transistor Tr5 and a sixth transistor Tr6. Transistor Tr 5 is a P-channel transistor, and transistor Tr 6 is an N-channel transistor. Each gate is shared and a common input terminal 8 is provided. The voltage Vdl is applied to the source of the transistor Tr5, and the source of the transistor Tr6 is grounded and maintained at the Gnd potential. The output of the inverter section 6 is also taken out of the common drain force of the transistors Tr5 and Tr6 and is stored in the gate of the transistor Tr3. [0009] In addition, an inverter unit 10 is installed on the gate side of the transistor Tr4, and an output of the inverter unit 6, that is, an inverted signal = A} of the signal C {(inverted signal ZA) obtained by inverting the signal B is added. . The inverter unit 10 includes a seventh transistor Tr7 and an eighth transistor Tr8. Transistor Tr7 is a P-channel transistor, and transistor Tr8 is an N-channel transistor. The output of inverter 6 is applied to the common gate. The voltage Vdl is applied to the source of the transistor Tr7, and the source of the transistor Tr8 is grounded and maintained at the Gnd potential. The output of the inverter unit 10 is taken out from the common drain of the transistors Tr7 and Tr8 and added to the gate of the transistor Tr4.

Then, the signal D extracted from the level converting unit 4 is inverted by the inverter unit 12 and extracted from the output terminal 14 as the signal E. In this case, the inverter unit 12 includes a ninth transistor Tr9 and a tenth transistor TrlO. The transistor Tr9 is a P-channel transistor, and the transistor TrlO is an N-channel transistor. The output of the level conversion unit 4 is applied to the common gate. A voltage Vd2 is applied to the source of the transistor Tr9, and the source of the transistor TrlO is grounded and maintained at the Gnd potential. The signal force inverted by the inverter 12 is taken out from the output terminal 14 provided at the drains of the transistors Tr9 and TrlO.

[0011] This level converter circuit 2 is used when level-converting a signal on the power supply side of the voltage Vdl to a signal on the power supply side of the voltage Vd2. For example, Vdl = l. V], Vd2 = l. 8 [V].

[0012] Therefore, in normal operation, when the signal A at the level of the voltage Vdl is supplied to the input terminal 8, it is added to the gate of the transistor Tr3 via the inverter 6 and via the inverters 6 and 10. Added to the gate of transistor Tr4. As a result, a level-shifted signal corresponding to the voltage Vd2 is obtained at the output point D of the level converting unit 4, and this signal is inverted by the inverter unit 12 and taken out from the output terminal 14 as the output signal E. If the transistors Tr9 and Tr10 do not conduct at the same time, no through current flows through the transistors Tr9 and TrlO.

[0013] However, when the power is turned on, if the voltage V d2 on the second power supply side rises before the power of the voltage Vdl on the first power supply side by the power-on sequence, the voltages Vdl and Vd2 , Vd2 = (External voltage) [V]

Vdl = 0 [V]

Will occur. In normal system operation, the transistors Tr3 and Tr4 are not turned on or off at the same time, but during this period, the operation of the inverter units 6 and 10 is stopped due to the voltage Vdl = 0 [V]. The gate voltages of transistors Tr3 and Tr4 are 0 [V], and both transistors Tr3 and Tr4 are turned off simultaneously. If such a condition occurs, the output extraction unit 16 (point D) of the level conversion unit 4 may become indeterminate, that is, may have an intermediate potential Vn. This intermediate potential Vn is an output state of an indeterminate level between the two different from the output H or output L of normal system operation.

[0014] When such an intermediate potential Vn is applied to the gates of the transistors Tr9 and TrlO of the inverter 12 on the rear stage side, the transistors Tr9 and TrlO are simultaneously turned on. When the transistors Tr9 and TrlO are turned on, an excessive through current flows through the transistors Tr9 and TrlO to the ground side. An LSI with a large number of level conversion units 4 and inverter units 12 is inconvenient because an excessive current flows when the power is turned on.

[0015] The output waveform of the level converter circuit 2 when the power is turned on will be described with reference to FIG. Fig. 2 is a diagram showing an operation simulation of the level converter circuit when the power is turned on, and shows the transition of the voltages Vdl and Vd2 and the potential change of the output extraction section 16 (point D).

[0016] The power is turned on at time tl (= 0. E + 00 [s]), and the voltage Vd2 passes Vd2 = at time t2 (= l. E-05 [s]) after a lapse of a predetermined time. l. Reach 8 [V]. After that, the voltage Vdl starts to rise at time t3 (= 3. E—05 [s]), and reaches Vdl = l. 2 [V] at time t4 (= 4. E—05 [s]). During the period from time tl to t3, the potential VD at force D where Vdl = 0 [V] rises following the voltage Vd2 and changes to a constant voltage (Vn ^ O. 42 [V]) at time t2. After that, it coincides with the voltage Vdl at time tx, rises to coincide with the voltage Vdl for a short period from time tx to time ty, and then rises to Vd2 (= 1.8 [V]) at time ty. The

[0017] With regard to such a change in the potential VD, the intermediate potential Vn is exhibited in the period from the time t2 to the time tx (intermediate potential period Tn). This intermediate potential Vn is an indefinite voltage value between the potential 0 [V] and the voltage Vd2 as described above. That is, the output extraction unit 16 is in an indeterminate output state. In this intermediate potential period Tn, the transistors Tr9 and TrlO of the inverter unit 12 are simultaneously As a result, the through current flows through the transistors Tr9 and TrlO. In addition, when such an intermediate potential Vn is transmitted to the subsequent circuit, it may cause an unexpected operation state (malfunction). Therefore, in order to prevent an excessive through current and malfunction caused by the power-on sequence, it is necessary to avoid output indefiniteness that occurs in the output extraction section 16.

[0018] With respect to such a problem, Patent Documents 1 and 2 do not disclose or suggest any means for solving the problem.

Accordingly, an object of the present invention relates to a level converter circuit that converts a level of a signal in accordance with a voltage of a power supply, and to prevent an indefinite output due to a power-on sequence.

[0020] To describe in detail such an object, the potential of the output extraction unit is controlled in response to power-on to avoid the occurrence of indefinite output.

Means for solving the problem

[0021] To achieve the above object, according to a first aspect of the present invention, a first power supply side signal is level-converted to a second power supply side signal having a voltage different from that of the first power supply. In the level converter circuit, a pull-up circuit is provided in the output extraction portion of the signal whose level has been converted, and the output extraction portion is pulled up to a high potential in synchronization with power-on by the pull-up circuit.

[0022] In such a configuration, when the second power supply rises before the first power supply, the output of the output extraction unit of the signal may become indefinite. In synchronism with power-on, the potential of the output extraction section is raised to a high potential, and output indefiniteness can be avoided. According to such a configuration, it is possible to suppress intermediate potential output. As a result, excessive current flow and malfunction can be prevented in the circuit on the subsequent stage of the level conversion output extraction section.

In this level converter circuit, the pull-up circuit raises the potential of the output extraction portion to a high potential in synchronization with the rise of the second power supply, and in response to the rise of the first power supply. The potential of the output extraction unit may be configured to depend on the level of the signal on the first power supply side. With such a configuration, the second power Instable output can be avoided because the potential of the output extraction section is raised to a high potential in synchronization with the rise of the output. In addition, since the potential of the output extraction section depends on the signal level of the first power supply due to the rise of the first power supply, it is possible to take out the level comparison output related to the pull-up when the power is turned on.

In this level converter circuit, the output extraction section is made conductive to the second power supply through the pull-up circuit in synchronization with the rise of the second power supply, thereby raising the voltage of the second power supply. It is good also as a structure. With such a configuration, the potential of the output extraction section can be raised to the voltage of the second power supply in synchronization with the rise of the second power supply.

[0025] In this level converter circuit, the pull-up circuit includes a transistor inserted between the output extraction section and the second power source, and the transistor is turned on when the second power source is turned on. It is good also as a structure made to conduct to. With such a configuration, the voltage of the second power supply can be applied to the output extraction section in synchronization with the rise of the second power supply, and the potential can be raised to the voltage of the second power supply.

In this level converter circuit, the pull-up circuit includes a transistor inserted between the output extraction unit and the second power supply, and the first power supply is connected to the gate of the transistor. It is good also as the structure which carried out. With such a configuration, the voltage of the second power supply can be stored in the output extraction section in synchronization with the rise of the second power supply, and the potential can be raised to the voltage of the second power supply. The current flowing in the transistor can be suppressed in response to the rise of the power supply.

In this level converter circuit, the pull-up circuit includes a series circuit of a transistor and a resistor between the output extraction unit and the second power supply, and the first gate is connected to the first gate of the transistor. The power supply voltage may be applied.

[0028] In this level converter circuit, the pull-up circuit includes a series circuit of a plurality of transistors between the output extraction unit and the second power source, and the gate of each transistor of the series circuit The first power supply voltage may be applied.

[0029] In this level converter circuit, the first power source is constituted by an internal power source of a semiconductor integrated circuit common to the level converter circuit, and the second power source is the semiconductor device. It may consist of an external power supply for the body integrated circuit!

In order to achieve the above object, according to a second aspect of the present invention, a signal on the first power supply side is level-converted to a signal on the second power supply side having a voltage different from that of the first power supply. A method for controlling a level converter circuit, wherein the potential of an output extraction unit for extracting the level-converted signal is raised to a high potential in synchronization with power-on.

[0031] In such a configuration, when the second power supply rises before the first power supply, the output of the signal output extraction unit may become indefinite. According to the configuration described above, the potential of the output extraction section is raised to a high potential in synchronization with the power-on. Such processing can avoid indefinite output. In other words, the intermediate potential output can be suppressed, and excessive current flow and malfunction can be prevented in the circuit at the rear stage of the output portion of the level conversion output.

[0032] In this level converter circuit control method, the potential of the output extraction section is raised to a high potential in synchronization with the rise of the second power supply, and the output extraction section according to the rise of the first power supply. This is a configuration in which the potential of the power source depends on the level of the signal on the first power supply side.

In order to achieve the above object, according to a third aspect of the present invention, a signal on the first power supply side is level-converted to a signal on the second power supply side having a voltage different from that of the first power supply. An electronic circuit comprising a level converter circuit, wherein a pull-up circuit is provided in the output extraction section for the level-converted signal, and the output extraction section is pulled up to a high potential in synchronization with power-on by the pull-up circuit. It is.

[0034] In this electronic circuit, the pull-up circuit raises the potential of the output extraction unit to a high potential in synchronization with the rise of the second power supply, and outputs the output according to the rise of the first power supply. Choose a configuration in which the potential of the extraction part depends on the level of the signal on the first power supply side.

[0035] In this electronic circuit, the output extraction section is made conductive to the second power supply through the pull-up circuit in synchronization with the rise of the second power supply, thereby raising the voltage of the second power supply. It is good also as a structure.

[0036] In this electronic circuit, the pull-up circuit includes the output extraction unit and the second power supply. A transistor may be provided between the power source and the transistor, and the transistor may be turned on when the second power source is turned on.

[0037] In this electronic circuit, the pull-up circuit includes a transistor inserted between the output extraction unit and the second power source, and the first power source is connected to a gate of the transistor. As a configuration.

[0038] In this electronic circuit, the first power source is constituted by an internal power source of a semiconductor integrated circuit common to the level converter circuit, and the second power source is constituted by an external power source of the semiconductor integrated circuit. May be.

The invention's effect

[0039] According to the present invention, the following effects can be obtained.

[0040] (1) It is possible to avoid indefinite output caused by the power-on sequence.

[0041] (2) Since output instability caused by the power-on sequence can be avoided, it is possible to prevent malfunction such as overcurrent flow in the circuit on the rear stage side.

[0042] Other objects, features, and advantages of the present invention will become clearer with reference to the accompanying drawings and each embodiment.

Brief Description of Drawings

FIG. 1 is a circuit diagram showing a level converter circuit related to the present invention.

FIG. 2 is a diagram showing an output waveform of a level converter circuit when power is turned on.

FIG. 3 is a circuit diagram showing a level converter circuit according to the first embodiment of the present invention.

FIG. 4 is a flow chart showing an operation sequence as an example of a control method of the level converter circuit.

FIG. 5 is a diagram showing an output waveform of the level converter circuit when power is turned on.

FIG. 6 is a diagram showing an output waveform of the level converter circuit when power is turned on.

FIG. 7 is a diagram showing a current flowing through a pull-up circuit.

FIG. 8 is a diagram showing a level converter output.

FIG. 9 is a circuit diagram showing a level converter circuit according to a second embodiment of the present invention.

FIG. 10 is a circuit diagram showing a level converter circuit according to a third embodiment of the present invention. [11] A circuit diagram showing a level converter circuit according to a fourth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a level converter circuit according to a fifth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a level converter circuit according to another embodiment of the present invention. Explanation of symbols

[0044] Two-level converter circuit

4 Level conversion section

12 Inverter section

16 Output extraction part

18 Pull-up circuit

Vdl voltage (first power supply)

Vd2 voltage (second power supply)

Trl l Pull-up transistor

Trl2 pull-up transistor

20 Pull-up resistor

22 Semiconductor integrated circuit (electronic circuit)

24 Internal power supply circuit (first power supply)

26 External power supply circuit (second power supply)

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment]

A first embodiment of the present invention will be described with reference to FIG. FIG. 3 is a circuit diagram showing the level converter circuit according to the first embodiment. In FIG. 3, the same parts as those of the level converter circuit shown in FIG. This level comparator circuit is configured using the level converter circuit shown in FIG. 1. This is an example, and the protection scope of the present invention is limited to the level converter circuit of this embodiment. is not.

In this level converter circuit 2, voltage examples of the first and second power supplies as different power supplies For example, the level of the signal on the voltage Vdl (first power supply) side is converted to the signal on the voltage Vd2 (second power supply) side. Therefore, the level converter circuit 2 is provided with a level converting unit 4, and the output extracting unit 16 has a pull-up (PuU) that raises the potential of the output extracting unit 16 to a high potential in synchronization with power-on. -up) Circuit 18 is provided.

[0048] In this case, the pull-up circuit 18 is configured to forcibly raise the potential of the output extraction unit 16 that extracts the level-converted output to the voltage Vd2 of the second power supply in synchronization with power-on. In this embodiment, the pull-up circuit 18 is provided with a P-channel transistor Trl 1 as a pull-up transistor! A voltage Vd2 is applied to the source of the transistor Trl 1 from the same power source as the level converting unit 4, and a voltage Vdl is applied to the gate of the transistor Trl 1 from the same power source as the inverter units 6 and 10. It has been added. In other words, the source and gate of the transistor Trl are governed by different power supply voltages.

According to such a configuration, when the voltage Vdl applied to the gate of the transistor Trl l is Vdl = 0, the transistor Trl l is turned on (ON). During this conduction, the drain side potential of the transistor Trl is raised to the same potential as the source side voltage Vd2. As a result, the potential of the output extraction portion 16 on the drain side of the transistors Tr2 and Tr4 is raised to the voltage Vd2.

[0050] When the voltage Vdl applied to the gate of the transistor Trl l is Vdl> 0, the current flowing in the transistor Trl l decreases according to the level of the voltage Vdl, and the potential of the output extraction unit 16 is level. It depends on the output level of the conversion unit 4.

[0051] Therefore, when the power supply on the voltage Vd2 side rises earlier than the power supply on the voltage Vdl side by the voltage input sequence,

Vd2 = (External voltage) [V]

Vdl = 0 [V]

It becomes. In this case, the gate-source voltage Vgs of the transistor Trl l of the pull-up circuit 18 is

Vgs = Vdl -Vd2 = -Vd2

It becomes. For example, if Vdl = 0 [V] and Vd2 = l. 8 [], it becomes ¥ ₈ 5 = — ¥ (12 = —1.8 [V], and the gate of the transistor Trl l is in the most open state. Therefore, the output extraction part 16 ( The potential VD at point D) is VD = Vd2. That is, during the period before the voltage Vdl rises (Vdl = 0), the potential of the output extraction unit 16 (point D) is raised to the voltage Vd2 of the power source that controls the level conversion unit 4 and fixed.

[0052] In this case, when the potential of the output extraction unit 16 is raised to the voltage Vd2, the transistor Tr9 of the inverter unit 12 constituting the output circuit is cut off (OFF), the transistor TrlO is turned on (ON), and the output terminal The signal E obtained at 14 is L (low) output. That is, the simultaneous conduction of the transistors Tr9, 10 is avoided, and the flow of the through current is prevented.

[0053] Further, in the normal operation of the system including the level converter circuit 2 when the voltage Vdl rises, when Vd2 = (external voltage) [V] and Vdl = (internal voltage) [V], the transistor T rl 1 Gate-source voltage Vgs

Vgs = Vdl-Vd2>-Vd2 '' (2)

It becomes. Here, the system including the level converter circuit 2 is an electronic circuit such as a semiconductor integrated circuit incorporating the level converter circuit 2 or an electronic device including the electronic circuit. In this case, if Vd2 = l. 8 [V] and Vdl = l. 2 [V], then Vgs = -0.6 [V], and the absolute value of the voltage applied to the gate of the transistor Trl l is Compared with Vdl = 0 [V], the current flowing through the transistor Tr11 is reduced. The potential of the output extraction unit 16 depends on the output level of the level conversion unit 4. That is, Vd2 [V] is output when a high (H) level output is generated from the output extraction unit 16, and 0 [V] when a low (L) level output is generated from the output extraction unit 16. ] Is output.

[0054] Due to such a power-on sequence in which the voltage Vdl rises after the rise of the voltage Vd2, the potential of the output extraction part 16 (point D) is also maintained during the period of Vdl = 0 [V] (Td: Fig. 5). The intermediate potential Vn (Fig. 2) does not become the same or the same potential as the voltage Vd2, so the gate voltages of the transistors Tr9 and TrlO are also fixed to this voltage Vd2. Therefore, through current flow from the power supply side to the Gnd side when the power is turned on is avoided.

A method for controlling the level converter circuit 2 will be described with reference to FIG. FIG. 4 is a flowchart showing potential control of the output extraction unit corresponding to the power-on sequence. This flowchart is an example of a control method for the level converter circuit 2. When the power is turned on and the voltage Vd2 rises and the rise of the voltage Vdl is delayed, the period of Vdl = 0 and Vgs = —Vd2 is established as described above (step Sl). During this period, the transistor Tr11 conducts (step S2), and the potential VD of the output extraction section 16 becomes VD = Vd2 [V]. Such processing is continuously executed until the voltage Vdl rises. That is, the operations in steps S1 to S3 are repeated. As a result, the potential VD of the output extraction unit 16 is maintained at the voltage Vd2 that controls the level conversion unit 4, and the above-described intermediate potential Vn (FIG. 2) does not occur.

[0057] When the voltage Vdl rises (Vdl> 0), the process proceeds from step S1 to step S4, and the above-described equation (2) is established. In this case, depending on the output level (L or H) of the level converting unit 4 (step S5), normal operation is performed. That is, when the output level of the level converting unit 4 is H, VD = Vd2 [V] (step S6), and when L, VD = 0 [V] (step S7), and the process returns to step S1. That is, after the voltage Vdl rises, the operations of steps Sl, S4 to S6, and S7 are repeated.

In the level converter circuit 2 having such a pull-up circuit 18, first, when the power is turned on, the output of the level converting unit 4 that does not depend on the power-on sequence is set to a constant level, for example, the voltage Second, when the gate of the transistor Trl l is connected to another power supply, for example, the power supply on the voltage Vdl side, the voltage Vdl rises and shifts to normal operation. Can reduce the steady-state current flowing through the transistor Trl. That is, the amount of steady current can be greatly reduced compared to the current value when the gate of the transistor Trl is fixed to 0 [V].

The simulation results of the operation waveform and operation current of the level converter circuit 2 will be described with reference to FIGS. 5, 6, 7, and 8. FIG. Figure 5 shows the rise of the power supply voltage and the potential change at the output extraction section (in the case of H output) .Figure 6 shows the rise of the power supply voltage and the potential change at the output extraction section (in the case of L output). Fig. 7 is a diagram showing changes in the current flowing through the transistor Trl l of the pull-up circuit, and Fig. 8 is a diagram showing the level converter output.

[0060] As shown in FIG. 5, after the power-on sequence, the voltage Vd2 starts to rise at the time point tl, and after reaching the predetermined voltage Vd2 = l.8 [V] at the time point t2, the voltage Vdl is changed from the time point tl. Time Td Rise starts at time t3 delayed by a certain amount, and reaches the predetermined voltage Vdl = 1.2 [V] at time t4. That is, Vdl = 0 [V] in the period of time Td.

As described above, at this time Td, the transistor Tr 11 becomes conductive, and the potential VD of the output extraction unit 16 (point D) follows the voltage Vd 2 and becomes the same level. In the example shown in Fig. 5, the level conversion unit 4 generates H output, so the potential VD of the output extraction unit 16 (point D) remains VD = Vd2 even after the time t4 when the voltage Vdl rises. Yes.

[0062] Further, as shown in FIG. 6, the voltage Vd2 starts rising at time tl and reaches the predetermined voltage Vd2 = l.8 [V] at time t2 by the power-on sequence. Rise starts at time t3 delayed by time Td from tl, and reaches a predetermined voltage Vdl = 1.2 [V] at time t4. That is, Vdl = 0 [V] in the period of time Td. At time Td, the transistor Tr11 becomes conductive, and the potential VD of the output extraction section 16 (point D) follows the voltage Vd2 and becomes the same level. These are the same as in FIG.

However, in the operation shown in FIG. 6, since the level converting unit 4 generates the L output, the potential VD of the output extraction unit 16 (D point) is increased when the voltage Vdl rises. As described above, since it depends on the output of the level conversion unit 4, VD = 0 [V] is transferred between time t3 and time t4, and the L output of the level conversion unit 4 is taken out.

[0064] As shown in a of FIG. 7, the current Ipu flowing through the transistor Trl l during system operation

In [A], the steady-state current value is suppressed by the voltage Vdl applied to the gate, and the power consumption is reduced.

[0065] By the way, to avoid the occurrence of the intermediate potential Vn when the power is turned on, the gate of the transistor Trl l can be grounded to the Gnd potential. However, the gate is maintained and fixed at such a potential. If this is done, the steady-state current value will increase as shown in Fig. 7b, and power consumption cannot be reduced.

[0066] When the voltage Vdl is stored at the gate of the transistor Trl l, the potential of the output extraction section 16 (point D) is as shown in FIG. 8 a and the gate of the transistor Tr3 (B The potential changes in line with the potential at point). On the other hand, when the gate of the transistor Trl is grounded and pulled down to the Gnd potential, the potential of the output extraction portion 16 changes corresponding to the gate potential of the transistor Tr3 as shown in FIG. However, when the gate potential of transistor Tr3 is 0 level Even if the output voltage shifts, the output voltage shifts by a small voltage Vr. Therefore, when voltage Vdl is applied to the gate of transistor Trl 1, the direct current (DC) path generated when the voltage at output extraction section 16 (point D) is low (Low) = voltage Vd2-transistor Trl 1—Transistor Tr4—The output voltage shift through the Gnd path is reduced. As a result, it can be seen that resistance to noise can be improved.

[Second Embodiment]

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 9 is a circuit diagram showing a level converter circuit according to the second embodiment. In FIG. 9, the same parts as those of the level converter circuit 2 shown in FIG.

In the level converter circuit 2 of this embodiment, the pull-up circuit 18 is configured by a series circuit of P-channel transistors Trl 1 and Trl 2 as a plurality of pull-up transistors. A common voltage Vdl is supplied to the gates of these transistors Trl 1 and Trl 2.

[0070] According to such a configuration, the voltage Vd2 rises before the voltage Vdl by the power-on sequence, and the transistors Trl1 and Trl2 are both turned on during the time Td (Fig. 5) when Vdl = 0. The potential of the output extraction unit 16 is raised to the voltage Vd2 and maintained at that potential. Therefore, the occurrence of the intermediate potential Vn is avoided. Such a configuration also provides the same function as the level converter circuit 2 shown in FIG.

[Third Embodiment]

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 10 is a circuit diagram showing a level converter circuit according to the third embodiment. In FIG. 10, the same parts as those of the level converter circuit 2 shown in FIG. 3 or FIG. 9 are denoted by the same reference numerals.

In the level converter circuit 2 of this embodiment, the pull-up circuit 18 is configured by a parallel circuit of transistors Trl 1 and Trl 2 as a plurality of pull-up transistors. A common voltage Vdl is fed to the gates of these transistors Trl 1 and Trl2.

[0074] Even with such a configuration, the voltage Vd2 rises before the voltage Vdl by the power-on sequence, and the transistors Trl1 and Trl2 are both guided during the time Td (Fig. 5) when Vdl = 0. Then, the potential of the output extraction unit 16 is raised to the voltage Vd2 and maintained at that potential. Therefore, the occurrence of the intermediate potential Vn is avoided. Even with such a configuration, the same function as the level converter circuit 2 shown in FIG. 3 can be obtained.

[Fourth Embodiment]

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 11 is a circuit diagram showing a level converter circuit according to the fourth embodiment. In FIG. 11, the same parts as those of the level converter circuit 2 shown in FIG.

In the level converter circuit 2 of this embodiment, the pull-up circuit 18 is configured as a series circuit including a transistor Trl 1 and a resistor 20 as a pull-up transistor. The voltage Vdl is supplied to the gate of the transistor Trl l.

[0078] According to such a configuration, the voltage Vd2 rises before the voltage Vdl by the power-on sequence, and the transistor Trl l becomes conductive during the period of time Td (Fig. 5) when Vdl = 0. The potential of the extraction unit 16 is raised to a voltage close to the voltage Vd2 and maintained at that potential. Therefore, also in this case, occurrence of the intermediate potential Vn is avoided. Even with such a configuration, a function similar to that of the level converter circuit 2 shown in FIG. 3 can be obtained.

[Fifth embodiment]

Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 12 is a circuit diagram showing a semiconductor integrated circuit according to the fifth embodiment. In FIG. 12, the same parts as those of the level converter circuit 2 shown in FIG.

[0081] The semiconductor integrated circuit 22 is an example of an electronic circuit, and is configured by installing a number of circuits and elements such as the internal power supply circuit 24 as a first power supply together with the level converter circuit 2 described above. Yes. The internal power supply circuit 24 is supplied with the voltage Vd2 from the external power supply circuit 26 installed outside the semiconductor integrated circuit 22 in order to reduce the power consumption inside the semiconductor integrated circuit 22, and the voltage Vdl lower than the voltage Vd2 And supplying this voltage Vdl to the internal circuit of the semiconductor integrated circuit 22 reduces the power consumption of the internal circuit.

In the level converter circuit 2, the voltage of the transistor Trl l of the level conversion unit 4, the inverter unit 12, and the pull-up circuit 18 is supplied from the external power supply circuit 26. 6, 10 and the gate of transistor Trl l are internal Power circuit 24 power Voltage Vdl is applied.

According to such a semiconductor integrated circuit 22, the function as described above can be obtained, and the potential of the output extraction unit 16 of the level conversion unit 4 is synchronized with the power-on sequence. Bow I is raised to voltage Vd2 and maintained. Since this potential is applied to the inverter section 12, no through current flows.

Then, as the voltage Vdl rises, the potential of the output extraction unit 16 changes according to the level conversion output potential, and the level conversion output is applied to the inverter unit 12 during system operation. Other functions are as described above.

[Other embodiments, etc.]

(1) In the above embodiment, the case of Vd2> Vdl has been described for the voltages Vdl and Vd2. However, the pull-up circuit 18 according to the present invention can also be used when Vdl> Vd2. In that case, a voltage converter 28 added with a broken line may be installed in the semiconductor integrated circuit 22 shown in FIG. 12, and the voltage VdO may be set to be lower than Vd2 and applied to the gate of the transistor Trl1.

(2) In the above embodiment, the force described on the assumption that the configuration of the level converter circuit 2 shown in FIG. 1 is used. The present invention relates to the output extraction unit 16 of the level conversion unit 4 of the level converter circuit 2. One characteristic is that the potential of the level converter 4 is raised to the voltage of the second power source when the power is turned on. Therefore, the level converting unit 4 is limited to the configurations shown in FIGS. 3, 9, 10, and 11. is not.

[0088] (3) In the above embodiment, it is described that the through current is prevented by avoiding output indefiniteness. However, the level converter circuit, the control method thereof, or the electronic circuit according to the present invention is The output can be arbitrarily fixed (specified: HZL), and has the following technical advantages. As shown in Fig. 13, the level converter circuit 2 (Fig. 3, 9, 10, or 11) is provided, and the inverter T28 is also equipped with transistors Trl3 and Trl4 in the previous stage, and the transistors Trl5 and Trl6 in the subsequent stage. In the circuit 32 where the inverter 30 is installed, when the level converter circuit 2 is Vdl = 0 and Vd2 = l, and the output E = 'L', the input / output relationship of the inverter 28 is A ', A, and the inverter If the input / output relationship of 30 is E, E ', the output of inverter 30 is E, =' H ', so input A of input terminal 8 of level converter circuit 2 The logic of output E of output terminal 14 and the logic of input A 'of input terminal 34 and output E' of output terminal 36 can be the same, and outputs E and E 'are arbitrarily fixed (HZL). . Therefore, for example, when the output of the level converter circuit 2 is finally connected to the external output pin of the LSI, it is assumed that the external output pin is connected to the external input pin of another LSI, and the receiving LSI When there is a DC path to the ground (GND) side with respect to the external input pin, when Vd 1 = 0 and output H occurs in the sending LSI, a DC current flows. In other words, DC current flows through the route of the sending side Vd2—board wiring receiving side GND. This can be avoided by setting the output to L. Therefore, in the level converter circuit 2 according to the present invention, since the output can be fixed, this DC current can be avoided.

[0089] As described above, the most preferred embodiment of the present invention has been described. However, the present invention is not limited to the above description but is described in the claims or disclosed in the specification. It goes without saying that various modifications and changes can be made by those skilled in the art based on the gist of the present invention, and such modifications and changes are included in the scope of the present invention.

Industrial applicability

The present invention relates to a level converter circuit that converts a level of a first power supply side signal into a second power supply side signal having a voltage different from that of the first power supply, and relates to a voltage rise in a power-on sequence. This is useful because it can avoid indefinite output due to irregularities and can prevent through currents and malfunctions that occur on the output side.

Claims

The scope of the claims

[1] A level converter circuit for level-converting a signal on the first power supply side into a signal on the second power supply side having a voltage different from that of the first power supply,

A level converter circuit comprising: a pull-up circuit in an output extraction unit for the level-converted signal, and the pull-up circuit pulling up the output extraction unit to a high potential in synchronization with power-on.

[2] In the level converter circuit according to claim 1,

The pull-up circuit raises the potential of the output extraction section to a high potential in synchronization with the rise of the second power supply, and raises the potential of the output extraction section in response to the rise of the first power supply. A level converter circuit characterized in that it is configured to depend on the signal level of the power supply side.

[3] In the level converter circuit according to claim 1,

Synchronously with the rise of the second power supply, the output extraction section is connected to the second power supply through the pull-up circuit to raise the voltage of the second power supply. Level converter circuit.

[4] In the level converter circuit according to claim 1,

The pull-up circuit includes a transistor inserted between the output extraction unit and the second power supply, and is configured to make the transistor conductive when the second power supply is turned on. Level converter circuit.

[5] In the level converter circuit according to claim 1,

The level converter circuit, wherein the pull-up circuit includes a transistor inserted between the output extraction unit and the second power source, and the first power source is connected to a gate of the transistor.

[6] In the level converter circuit according to claim 1,

The pull-up circuit includes a series circuit of a transistor and a resistor between the output extraction unit and the second power supply, and is configured to apply the voltage of the first power supply to the gate of the transistor. A characteristic level converter circuit.

[7] In the level converter circuit according to claim 1, The pull-up circuit includes a series circuit of a plurality of transistors between the output extraction unit and the second power source, and the voltage of the first power source is applied to the gate of each transistor of the series circuit. A level converter circuit characterized by having a structure that can be ordered.

[8] In the level converter circuit according to claim 1,

The level converter is characterized in that the first power source is constituted by an internal power source of a semiconductor integrated circuit common to the level converter circuit, and the second power source is constituted by an external power source of the semiconductor integrated circuit. circuit.

[9] A level converter circuit control method for level-converting a signal on the first power supply side to a signal on the second power supply side having a voltage different from that of the first power supply,

A method for controlling a level converter circuit, wherein the potential of an output extraction unit for extracting the level-converted signal is raised to a high potential in synchronization with power-on.

[10] In the method for controlling a level converter circuit according to claim 9,

The potential of the output extraction unit is raised to a high potential in synchronization with the rise of the second power supply, and the potential of the output extraction unit is set to a signal on the first power supply side in response to the rise of the first power supply. A method for controlling a level converter circuit, characterized in that the level converter circuit depends on the level of

[11] An electronic circuit comprising a level converter circuit for level-converting a signal on the first power supply side into a signal on the second power supply side having a voltage different from that of the first power supply,

An electronic circuit comprising a pull-up circuit in an output extraction unit for the signal whose level has been converted, and the pull-up circuit pulls up the output extraction unit to a high potential in synchronization with power-on.

[12] In the electronic circuit according to claim 11,

The pull-up circuit raises the potential of the output extraction unit to a high potential in synchronization with the rise of the second power supply, and increases the potential of the output extraction unit in response to the rise of the first power supply. An electronic circuit characterized in that it is configured to depend on the level of the signal on the power supply side.

[13] In the electronic circuit according to claim 11,

A configuration in which the output extraction section is made to conduct to the second power supply through the pull-up circuit in synchronization with the rise of the second power supply, thereby raising the voltage of the second power supply. An electronic circuit characterized by that.

[14] In the electronic circuit according to claim 11,

The pull-up circuit includes a transistor inserted between the output extraction unit and the second power supply, and is configured to make the transistor conductive when the second power supply is turned on. Electronic circuit to do.

[15] In the electronic circuit according to claim 11,

The electronic circuit according to claim 1, wherein the pull-up circuit includes a transistor inserted between the output extraction unit and the second power supply, and the first power supply is connected to a gate of the transistor.

[16] In the electronic circuit according to claim 11,

The first power source is constituted by an internal power source of a semiconductor integrated circuit common to the level converter circuit, and the second power source is constituted by an external power source of the semiconductor integrated circuit. .