JPH10336007A - Level converter, output circuit, and input-output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a level converter used for a semiconductor device which operates with a plurality of power supply voltages to stably operate even when a time lag exists between the delivering timing of the power supply voltages. SOLUTION: A level converter is provided with an input buffer circuit 100 and a level converting section 101 equipped with an output holding circuit 102. The buffer circuit 100 outputs a pair of buffer signals X1 and X2 to the level converting section 101 on the basis of a binary input signal A having an amplitude based on a low-voltage power source. The section 101 outputs the binary input signal A after converting the signal A into a binary output signal Y having the amplitude based on a high-voltage power source on the basis of the buffer signals X1 and X2. The output holding circuit 102 outputs the binary output signal Y based on the potential difference between the buffer signals X1 and X2 when the states of the signals X1 and X2 become unstable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level converter used for a semiconductor device operating at a plurality of power supply voltages.

2. Description of the Related Art In recent years, there has been a semiconductor device having a configuration in which circuits operating at different power supply voltages are provided to reduce power consumption, and a power supply voltage is supplied to each circuit as needed. A level converter is used as an interface between circuits having different power supply voltages, and its operation requires high reliability.

[0003]

2. Description of the Related Art FIG. 10 shows an output section of a semiconductor device operating at two kinds of power supply voltages. The signal A output from the internal circuit 50 operating with the power supply voltage of 3V is input to the level converter 51, and is also inverted by the inverter 52 and input to the level converter 51 as a signal A bar. Therefore, one of the signals A and A bar is the ground GN.
D, the other signal is 3v.

When the signal A and the inverted signal A bar are input to the level converter 51, the signal A is converted into a signal B whose amplitude becomes 5 V from the ground level and output. This signal B is supplied to a CMOS inverter 53 composed of a P-channel MOS transistor Tr1 and an N-channel MOS transistor Tr2 and operating at a power supply voltage of 5V.
And output from the output terminal 54.

FIG. 11 shows a conventional level converter 51. A power supply voltage of 5 V is supplied to the sources of the P-channel MOS transistors Tr3 and Tr5. Transistor Tr3
Is connected to the drain of an N-channel MOS transistor Tr4, and the drain of the transistor Tr5 is connected to the drain of an N-channel MOS transistor Tr6. The sources of the transistors Tr4 and Tr6 are connected to the ground GND.

The drains of the transistors Tr3 and Tr4,
That is, the node N1 is connected to the gate of the transistor Tr5, and the drains of the transistors Tr5 and Tr6, that is, the node N2 is connected to the gate of the transistor Tr3. Further, the node N2 is connected to the gate of a CMOS inverter 55 composed of a P-channel MOS transistor Tr7 and an N-channel MOS transistor Tr8 and operating at a power supply voltage of 5V.

The signal A is input to the gate of the transistor Tr6, and the signal A is input to the gate of the transistor Tr4. Then, the signal B is output from the drain of the CMOS inverter 55. The transistors Tr4 and Tr6 are connected to the transistors Tr3 and T3, respectively.
It has a current drive capability greater than r5.

[0008] The level converter 5 thus configured
In 1, when the signal A goes high (3v) and the signal A bar goes low (ground level), the transistor Tr6 is turned on and the transistor Tr4 is turned off.
Then, the transistor Tr3 is turned on and the transistor Tr5 is turned off. At this time, the node N2 is at L
Level (ground level), and the CMOS inverter 55 outputs an H level (5v) signal B.

When signal A goes low (ground level) and signal A goes high (3v), transistor T
While r6 is turned off, the transistor Tr4 is turned on. Then, while the transistor Tr5 is turned on,
The transistor Tr3 is turned off. At this time, the node N2
Is at H level (5v), and the CMOS inverter 55 outputs a signal B at L level (ground level).

Accordingly, the level converter 51 converts the signals A and A having an amplitude of 3 V from the ground level into a signal B having an amplitude of 5 V from the ground level, and outputs the signal B.

[0011]

In a semiconductor device operating at a plurality of power supply voltages, when a power supply voltage having a plurality of voltage values is supplied to the inside of a circuit, the power supply device generally operates from a high voltage to a low voltage. In order to generate the power supply, a power supply voltage having a high voltage value is first supplied to the inside of the circuit.

When a power supply voltage of 3V and a power supply voltage of 5V are supplied to the inside of the circuit, for example, as shown in FIG.
After supplying the power supply voltage of 5V, the power supply voltage of 3V is supplied several μS (microseconds) later. During a period of several μS in which the 5V power supply voltage is supplied and the 3V power supply voltage is not supplied, it can be considered that all signals in the circuit operating with the 3V power supply voltage are at the L level. it can.

Even when the signal A and the signal A, which are signals from a circuit operating at a power supply voltage of 3V, are both at L level, a state occurs in which a power supply voltage of 5V is supplied to the level converter 51.

Then, a power supply voltage of 5 V is supplied to the drains of the transistors Tr3 and Tr5 in a state where the transistors Tr4 and Tr6 are both turned off.
N2 may be an intermediate potential.

Therefore, there is a problem that the input of the CMOS inverter 55 has an intermediate potential, the transistors Tr7 and Tr8 are both turned on, and a through current flows from the power supply to the ground GND.

The output signal B of the level converter 51 also has the intermediate potential, the transistors Tr1 and Tr2 are both turned on, and a through current flows from the power supply to the ground GND. As the transistors Tr1 and Tr2, transistors having a large load driving capability are used. Therefore, the through current flowing through the transistors Tr1 and Tr2 has a considerably large current value of several tens to several hundreds of milliamps. Therefore, there is a problem that power consumption increases. Also, it may cause a malfunction due to latch-up.

An object of the present invention is to provide a level converter used in a semiconductor device which operates at a plurality of power supply voltages, and which operates stably even when there is a time difference between the application timings of the plurality of power supply voltages. It is in.

[0018]

FIG. 1 is a diagram for explaining the principle of the first aspect of the present invention. That is, the level converter includes the input buffer circuit 100 and the level conversion unit 101 including the output holding circuit 102. The input buffer circuit 100 outputs a pair of buffer signals X1 and X2 to the level converter 101 based on a binary input signal A having an amplitude based on a low-voltage power supply. The level converter 101 converts the binary input signal A into a binary output signal Y having an amplitude based on a high-voltage power supply based on the buffer signals X1 and X2, and outputs the converted signal. The output holding circuit 102 outputs a binary output signal Y based on the potential difference between the buffer signals X1 and X2 when the buffer signals X1 and X2 are in an undefined state.

According to a second aspect, in the level converter according to the first aspect, the output holding circuit and the level conversion unit are configured such that an input terminal and an output terminal of the first and second CMOS inverters operated by a high voltage power supply are mutually connected. Connected and configured.

The input buffer circuit includes the first CM.
The first between the output terminal of the OS inverter and the low potential side power supply
Are connected in series, and a second input transistor is connected in series between the output terminal of the second CMOS inverter and the low-potential-side power supply, based on the binary input signal. By turning on one of the first and second input transistors, the buffer signal is output.

According to a third aspect of the present invention, the output holding circuit includes an initial value setting circuit for setting an initial value of the binary output signal when a high voltage power supply is turned on. According to a fourth aspect, in the initial value setting circuit, one of the output terminals of the first and second CMOS inverters is connected to one of a high-potential-side power supply and a low-potential-side power supply via a capacitor.

According to a fifth aspect of the present invention, the initial value setting circuit is interposed between one of the output terminals of the first and second CMOS inverters and one of a high potential power supply and a low potential power supply. It comprises an initial value setting transistor, and a reset signal output circuit for turning on the initial value setting transistor for a predetermined time based on turning on a high voltage power supply.

According to the present invention, the initial value setting circuit is configured such that threshold voltages of the first and second CMOS inverters are different values. According to a seventh aspect, the initial value setting circuit includes the capacitance and the first and second CMOS inverters having different threshold voltages.

According to an eighth aspect, there is provided an output circuit in which an output buffer circuit is driven based on a binary output signal of the level converter according to any one of the first to seventh aspects.

According to a ninth aspect, based on the binary output signal of the level converter according to any one of the third to seventh aspects, the pull-up control transistor connected to the high-potential-side power supply via a resistor is provided. The gist is an output circuit that is opened and closed.

According to a tenth aspect, an output mode for outputting an output signal from an output buffer circuit based on the binary output signal of the level converter according to any one of the third to seventh aspects, and an output mode of the output buffer circuit. The gist of the present invention is an input / output circuit capable of switching between an input mode in which a signal is in an undefined state.

(Operation) According to the first aspect of the present invention,
The output holding circuit 102 outputs a binary output signal Y based on the potential difference between the buffer signals X1 and X2 when the buffer signals X1 and X2 are in an undefined state. Therefore, even if the buffer signals X1 and X2 are in an undefined state, the circuit operates normally.

According to the second aspect of the present invention, when one of the first and second input transistors is turned on based on a binary input signal, the first and second CMOS inverters are turned off. The binary output signal is output. The first and second CMOS inverters operate so as to enlarge the potential difference if there is a slight potential difference at their output terminals. Therefore, when the buffer signal becomes indefinite, one of the output terminals is used. Is at H level and the other is at L level. Therefore, a binary output signal is reliably output.

According to the third aspect of the present invention, the initial value setting circuit sets an initial value of the binary output signal when a high voltage power supply is turned on. Therefore, when the high voltage power is turned on,
The output holding circuit outputs a binary output signal having the set initial value.

According to the fourth aspect of the present invention, when the high voltage power supply is turned on, the capacitance connected to the high potential side power supply is
It works to raise the potential of the connected output terminal.
Further, the capacitor connected to the low-potential-side power supply works to lower the potential of the connected output terminal when the high-voltage power supply is turned on. Therefore, the initial value of the binary output signal that is output when the high voltage power is turned on while the buffer signal is in an undefined state is determined to be one of the binary output signals.

According to the fifth aspect of the present invention, the reset signal output circuit outputs a reset signal for a predetermined time when the high voltage power is turned on. When the high-voltage power supply is turned on, the initial value setting transistor connected to the high-potential-side power supply
It is turned on based on the reset signal and works to raise the potential of the output terminal of the CMOS inverter. or,
When the high-voltage power supply is turned on, the initial value setting transistor connected to the low-potential-side power supply is turned on based on the reset signal, and serves to lower the potential of the output terminal of the CMOS inverter. Therefore, the initial value of the binary output signal that is output when the high voltage power is turned on while the buffer signal is in an undefined state is determined to be one of the binary output signals.

According to the sixth aspect of the present invention, when a high voltage power supply is applied to a CMOS inverter having a low threshold voltage and a CMOS inverter having a high threshold voltage, the CMOS inverter having a low threshold voltage has an H level first. Is output, the initial value of the binary output signal to be output when the high voltage power supply is turned on while the buffer signal is in an undefined state is determined to be one of the binary output signals.

According to the seventh aspect of the present invention, when a high voltage power supply is applied to a CMOS inverter having a low threshold voltage and a CMOS inverter having a high threshold voltage, the CMOS inverter having a low threshold voltage has an H level first. Is output, the initial value is reliably determined in addition to the function of the capacitor.

[0034] According to the invention of claim 8, according to claim 1,
The output buffer circuit is driven based on the binary output signal of the level converter according to any one of the above items 7 to 7,
Output circuit operates normally.

According to the ninth aspect of the present invention, a third aspect is provided.
7. The pull-up control transistor connected to the high-potential-side power supply via the resistor opens and closes based on the binary output signal of the level converter according to any one of 7 to 7,
A pull-up initial state when the high-voltage power is turned on with the buffer signal in an undefined state is set.

According to the tenth aspect of the present invention, the level converter according to any one of the third to seventh aspects,
The output mode is switched between an output mode in which the output signal is output from the output buffer circuit and an input mode in which the output signal of the output buffer circuit is in an indefinite state based on the value output signal. The initial state is set.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 2 shows a first embodiment of a level converter embodying the present invention.

P-channel MOS transistors Tr11 and N
A first MOS transistor including a channel MOS transistor Tr12;
The output terminal of the CMOS inverter 2 is a P-channel MO
It is connected to the input terminal of a second CMOS inverter 3 composed of an S transistor Tr13 and an N channel MOS transistor Tr14. The output terminal of the second CMOS inverter 3 is connected to the input terminal of the first CMOS inverter 2. In the present embodiment, the first and second
CMOS inverters 2 and 3 constitute an output holding circuit and a level converter.

The output terminal of the first CMOS inverter 2 is connected to the drain of a first input transistor Tr15 composed of an N-channel MOS transistor, and the output terminal of the second CMOS inverter 3 is connected to an N-channel MOS transistor.
A second input transistor Tr1 composed of a transistor
6 is connected to the drain. The sources of the first and second input transistors Tr15 and Tr16 are connected to ground GN.
D. In the present embodiment, the first and second
The input transistors Tr15 and Tr16 form an input buffer circuit.

The output terminal of the second CMOS inverter 3, that is, the node N3, is connected to the input terminal of the third CMOS inverter 4 composed of a P-channel MOS transistor Tr17 and an N-channel MOS transistor Tr18. In this embodiment, the first to third CMOs
The S inverters 2, 3, and 4 are supplied with a high-voltage power supply of 5 V. The transistors Tr15 and T15
The current driving capability of r16 depends on the transistors Tr11 and Tr13.
Is set so as to be larger than the current driving capability.

The gate of the transistor Tr16 has two gates.
An input signal A is input as a value input signal, and an inverted signal A of the input signal A is input to the gate of the transistor Tr15.
A bar is entered. The input signals A and A are output from an internal circuit that operates on a 3V power supply that is a low-voltage power supply,
Its amplitude ranges from ground level to 3v.

The level converter 1 configured as described above
When the input signal A goes high (3v) and the input signal A goes low (ground level), the transistor Tr16 is turned on and the transistor Tr15 is turned off. Then, the transistor Tr11 is turned on, the transistor Tr12 is turned off, and the transistor Tr1 is turned off.
4 is turned on, and the transistor Tr13 is turned off. At this time, the node N3 is at L level (ground level),
L as a binary output signal is supplied to the third CMOS inverter 4.
Level (ground level) is input, and the third CMOS
Inverter 4 outputs an H-level (5v) output signal B.

When the input signal A goes low (ground level) and the input signal A goes high (3v), the transistor Tr16 is turned off and the transistor Tr15 is turned on. Then, the transistor Tr13 is turned on and the transistor Tr14 is turned off, and the transistor Tr12 is turned on and the transistor Tr11 is turned off. At this time, the node N3 is at the H level (5v),
The third CMOS inverter 4 outputs H as a binary output signal.
The level (5v) is input, and an L-level (ground level) output signal B is output from the third CMOS inverter 4.

Therefore, in the level converter 1, the input signals A and A whose amplitudes become 3 V from the ground level are obtained.
The bar is converted into an output signal B having an amplitude of 5 V from the ground level.

When power is supplied to the semiconductor device having the level converter 1 and 5V power is supplied prior to 3V power supply, the input signals A and A are both at L level. 1 is supplied with 5 V power.

Then, although the transistors Tr15 and Tr16 are both turned off, the first and second CMOS inverters 2 and 3 have a slight output terminal voltage based on the power supply of 5 V to the level converter 1. If there is a potential difference, the operation is performed so as to enlarge the potential difference, so that one of the output terminal voltages is at H level and the other is at L level.
Therefore, the node N3 is at L level (ground level),
The third CMOS inverter 4 outputs an output signal B of H level (5v) or L level (ground level).

Next, the characteristic operation and effect of the first embodiment as described above will be described below. (1) In the level converter 1 of the present embodiment, when the power supply voltage of 5 V is turned on when both the input signals A and A are at L level, the first and second CMOS inverters 2
The node N3 is set to either the L level (ground level) or the H level (5v) by the output holding circuit composed of N.3. Therefore, no through current flows from the power supply to the ground GND in the level converter 1, and the output signal B does not become the intermediate potential. As a result, normal operation of the circuit is guaranteed while reducing the power consumption of the semiconductor device.

(Second Embodiment) FIG. 3 shows a second embodiment. The level converter 10 according to the second embodiment is obtained by adding first and second capacitors C1 and C2 to the level converter 1 according to the first embodiment.
The same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

The output terminal of the first CMOS inverter 2, that is, the node N4, is connected to a 5V power supply via the first capacitor C1. The node N3 has a second capacitance C
2 is connected to the ground GND. In the present embodiment, the first and second capacitors C connected in this manner
1 and C2 constitute an initial value setting circuit.

The level converter 1 configured as described above
At 0, the input signal A whose amplitude is 3v from the ground level is converted into an output signal B whose amplitude is 5v from the ground level in the same operation as the level converter 1 of the first embodiment.

When power is supplied to the semiconductor device provided with the level converter 10 and 5V power is supplied prior to 3V power supply, the input signals A and A are both at L level.
Regarding the level, the power of 5 V is supplied to the level converter 10.

When a power supply voltage of 5 V is applied to the level converter 10 when both the transistors Tr15 and Tr16 are turned off, the first and second capacitors C1 and C2 cause a coupling phenomenon. This coupling phenomenon works to raise the level of the node N4 toward the H level and to lower the level of the node N3 toward the L level.

In this state, when the first and second CMOS inverters 2 and 3 operate, the node N3 becomes L level (ground level), and the third CMOS inverter 4 outputs H level (5V). The signal B is output. That is, when the power is turned on, the transistors Tr15, T15
level converter 10 when both r16 are off
Has an initial value of 1.

The characteristic effects of the second embodiment as described above will be described below. (1) In the level converter 10 of the present embodiment, when the power supply voltage of 5 V is turned on when both the input signals A and A are at the L level, in addition to the same operation as the first embodiment, Due to the coupling phenomenon caused by the first and second capacitors C1 and C2, the signal held in the holding circuit becomes a constant value, and the output signal B becomes H level (5v). Therefore,
In addition to the effects of the first embodiment, the transistors Tr15, Tr15,
Level converter 1 when both Tr16 are off
The initial value of 0 can be set to 1. As a result, the operation of the next stage circuit can be reliably controlled.

The second embodiment may be modified as follows. ○ As shown in FIG. 4, the node N4
May be connected to ground GND via a first capacitor C1, and the node N3 may be connected to a 5V power supply via a second capacitor C2.

The level converter 15 connected as described above
Then, as in the level converter 10 of the second embodiment, the signal held in the holding circuit becomes a constant value, and the output signal B becomes L level (ground level). Therefore, in addition to the effects of the first embodiment, the initial value of the level converter 15 at power-on can be set to 0. As a result, the operation of the next stage circuit can be reliably controlled.

(Third Embodiment) FIG. 5 shows a third embodiment. In the level converter 20 of the third embodiment, an initial value setting transistor Tr20 composed of an N-channel MOS transistor and a reset signal output circuit 21 are added to the level converter 1 of the first embodiment. The same components as those of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

The output terminal of the first CMOS inverter 2, that is, the node N4 is connected to the drain of the N-channel MOS transistor Tr20. The source of the transistor Tr20 is connected to the ground GND.
The gate of the transistor Tr20 is connected to the reset signal output circuit 21. In this embodiment, the transistor Tr20 and the reset signal output circuit 21 connected in this way constitute an initial value setting circuit.

The reset signal output circuit 21 is a circuit which operates at a power supply voltage of 5 V and outputs a pulse signal which becomes H level for a predetermined time when the power is turned on as a reset signal. The pulse width of the reset signal is set to a time sufficient to ensure that the potential of the node N4 is lower than that of the node N3 based on the ON operation of the transistor Tr20 after the power is turned on.

The level converter 2 configured as described above
At 0, the input signal A whose amplitude is 3v from the ground level is converted into an output signal B whose amplitude is 5v from the ground level in the same operation as the level converter 1 of the first embodiment.

When power is supplied to the semiconductor device having the level converter 20 and 5V power is supplied prior to 3V power supply, the input signals A and A are both at L level.
Regarding the level, the power of 5 V is supplied to the level converter 20.

When the transistors Tr15 and Tr16 are both turned off and a power supply voltage of 5 V is applied to the level converter 20, a reset signal is output from the reset signal output circuit 21 and the transistor Tr20 is turned on. Then, the potential of the node N4 becomes lower than that of the node N3.

In this state, when the first and second CMOS inverters 2 and 3 operate, the node N4 is at L level (ground level) and the node N3 is at H level (5v).
Thus, an L-level (ground level) output signal B is output from the third CMOS inverter 4. That is,
When the power is turned on and the transistors Tr15 and Tr16 are both turned off, the initial value of the level converter 20 becomes 0.

The characteristic effects of the third embodiment as described above will be described below. (1) In the level converter 20 of this embodiment, when the power supply voltage of 5 V is turned on when both the input signals A and A are at the L level, the transistor Tr20 is turned on and the node N4 is pulled down from the node N3. Therefore, the operation of the holding circuit causes the node N4 to go low (ground level), the node N3 to go high (5v), and the output signal B to go low (ground level).

Therefore, in addition to the effects of the first embodiment,
The initial value of the level converter 20 when both the transistors Tr15 and Tr16 are off can be set to 0. As a result, the operation of the next stage circuit can be reliably controlled.

(2) Level converter 2 of the present embodiment
0, the first and second capacitors C of the second embodiment
1 and C2 are not required, and an initial value can be set by a configuration including the transistor Tr20 and the reset signal output circuit 21. Since a general semiconductor device often includes a power-on reset circuit, the reset signal output circuit 21 does not need to be provided. Therefore, the area occupied by the level converter 20 in the layout area of the semiconductor device can be reduced.

The third embodiment may be modified and implemented as follows. As shown in FIG. 6, the drain of the transistor Tr20 may be connected to the node N3.

The level converter 25 connected as described above
Then, in the same operation as the level converter 20 of the third embodiment, the transistor Tr20 is turned on and the node N3 is turned on.
Is pulled down from the node N4, the output signal B becomes H
Level (5v). Therefore, in addition to the effect of the first embodiment, the initial value of the level converter 25 at power-on can be set to 1. As a result, the operation of the next stage circuit can be reliably controlled. Further, the same effect as the effect (2) of the second embodiment can be obtained.

(Fourth Embodiment) FIG. 7 shows a fourth embodiment in which the present invention is embodied in an output circuit for pull-up resistance control. Since the output circuit of the pull-up resistance control uses the level converter 10 of the second embodiment, the description of the operation of the level converter 10 is omitted.

The control signal P from the internal circuit 50 operating at the power supply voltage of 3V is input to the level converter 10 and is also inverted by the inverter 31 operating at the power supply voltage of 3V, and is inverted to the level converter 10 as a signal P bar. Is entered.

In the level converter 10, the signals P and P whose amplitude is 3v from the ground level are converted into a signal Q whose amplitude is 5v from the ground level. Signal Q output from level converter 10 is input to the gate of pull-up control transistor Tr30 formed of a P-channel MOS transistor. Transistor T
The source of r30 is connected to a 5V power supply via a resistor R,
The drain of the transistor Tr30 is connected to the external terminal 32. In this embodiment, the level converter 1
An output circuit for pull-up resistance control is constituted by 0, the resistor R, and the transistor Tr30.

In the pull-up resistor control output circuit thus configured, if the control signal P goes low (ground level) and the signal P bar goes high (3v), the signal Q
Becomes L level (ground level), and the transistor T
When r30 is turned on, the output voltage output from the external terminal 32 becomes 5V.

When the control signal P goes high (3v) and the signal P bar goes low (ground level), the signal Q goes high (5v), the transistor Tr30 is turned off, and the external terminal 32 goes high. It becomes an impedance state.

As described above, the level converter 1
0 when the power is turned on, the initial value of the signal Q is H level (5
v). Therefore, the initial state when the power of the external terminal 32 is turned on is a high impedance state.

The characteristic operation and effect of the fourth embodiment as described above will be described below. (1) In the output circuit of the pull-up resistance control according to the present embodiment, when the power supply voltage of 5 V is turned on when the input signals P and P bar are both at the L level, the level converter 10
Output a high-level (5v) signal Q at the external terminal 3
2 is in a high impedance state.

Therefore, the amplitude is 3 from the ground level.
The normal operation of the pull-up resistance control output circuit is assured while the pull-up resistance control output circuit can be controlled by the control signal P which becomes v, that is, while reducing power consumption. Further, the initial operation state of the output circuit of the pull-up resistance control when the signals P and P are both at the L level can be set to the high impedance state.

(Fifth Embodiment) FIG. 8 shows a fifth embodiment in which the present invention is embodied in an input / output circuit 40.
The input / output circuit 40 uses the level converter 10 (initial value 1) of the second embodiment and the level converter 15 (initial value 0) of another example. The description of is omitted.

Input / output control signal C output from internal circuit
Is a signal which becomes H level when the terminal 41 is used as an output terminal. The data D output from the internal circuit
Is output from the terminal 41 when the terminal 41 is used as an output terminal. The amplitude of the signals C and D is 3 V from the ground level.

In the input / output circuit 40, the input / output control signal C is input to the NAND circuit 42 and also to the NOR circuit 44 via the inverter 43. Data D
Is input to the NAND circuit 42 and the NOR circuit 44
Is input to

The output signal E of the NAND circuit 42 is input to the level converter 10 and the inverter 4
Level converter 1 which is inverted at 5 and becomes signal E bar
Input to 0.

The output signal F of the NOR circuit 44 is input to the level converter 15 and inverted by the inverter 46 and input to the level converter 15 as a signal F bar. Each of the logic circuits 42 to 46 operates with a 3V power supply.

Signal G output from level converter 10 is input to the gate of first input / output transistor Tr40 formed of a P-channel MOS transistor. The source of the transistor Tr40 is connected to a 5V power supply. Signal H output from level converter 15 is input to the gate of second input / output transistor Tr41 formed of an N-channel MOS transistor. The source of the transistor Tr41 is connected to the ground GND.

The drains of the transistors Tr40 and Tr41 are connected to each other to form a node N5. The node N5 is connected to the terminal 41 and the input buffer 4
7 is connected to the internal circuit of the semiconductor device.

In the input / output circuit 40 configured as described above, when the input / output control signal C goes low (ground level), the signal E is fixed at the high level (3v), and the signal F is fixed.
Are fixed at the L level (ground level).

Then, as described above, signals E and F whose amplitudes are 3V from the ground level are converted into signals G and H whose amplitudes are 5V from the ground level by the level converters 10 and 15, respectively. Therefore, the transistor Tr4
0 and Tr41 are both turned off to enter the input mode. In this state, when a signal is input to the terminal 41, the signal becomes the input signal In via the input buffer 47 and is supplied to the internal circuit.

When the input / output control signal C becomes H level (3v), the signals E and F become inverted signals of the data D. Then, as described above, the level converters 10 and 15 generate signals E and F whose amplitudes become 3 V from the ground level, respectively.
The signals are converted into signals G and H having an amplitude of 5 V from the ground level. Therefore, when the data D becomes H level (3v), the transistor Tr40 is turned on and the transistor Tr41 is turned off. If data D is L
Level (ground level), the transistor Tr40 is turned off, and the transistor Tr41 is turned off.
Is turned on. That is, the output mode is such that one of the transistors Tr40 and Tr41 is turned on based on the data D. Then, data D whose amplitude is 5 V from the ground level is output from the terminal 41.

When power is supplied to the semiconductor device having the level converters 10 and 15 and 5V power is supplied prior to 3V power supply, the signals E, E, F, and
All F bars are at L level, but the level converter 1
0 and 15 are supplied with 5 V power.

As described above, the level converter 1
The initial value of the signal G at power-on at 0 is H level (5
v). The initial value of the signal H when the power is turned on in the level converter 15 is L level (ground level).

Therefore, the transistors Tr40 and Tr41 are turned off. As a result, the initial state of the input / output circuit 40 when the power is turned on is the input mode. The characteristic operation and effect of the fifth embodiment as described above will be described below.

(1) In the input / output circuit 40 of the present embodiment, when the signals E, E, F, and F input to the level converters 10 and 15 at the time of power-on are all at L level, 5 V Even when the power supply voltage is turned on, the level converter 10 outputs an H level (5v) signal G, and the level converter 15 outputs an L level (ground level) signal H. Therefore, the transistors Tr40, T40
Since r41 is reliably turned off, no unnecessary current flows from the terminal 41 to the outside, and no through current flows from the power supply to the ground GND. Further, there is no possibility that an external current flows to the ground GND.

The fifth embodiment may be modified as follows. As shown in FIG. 9, the level converters 10 and 15 are different from the level converter 25 (initial value 1) of the third embodiment and the level converter 2 of the third embodiment.
It may be changed to 0 (initial value 0). At this time, it is necessary to connect the reset signal output circuit 21 to the level converters 25 and 20.

In such an input / output circuit 48, in addition to the effect similar to the effect of the fifth embodiment, the same effect as the effect (2) of the third embodiment can be obtained. or,
Each of the above embodiments may be modified and implemented as follows.

In the first embodiment, the threshold voltages of the first and second CMOS inverters 2 and 3 have been described as being the same. For example, the threshold voltage of the first CMOS inverter 2 is set to the second value. The threshold voltage of the CMOS inverter 3 may be set to a value higher than the threshold voltage. In this alternative example, the first and second CMOS inverters 2 and 3 constitute an initial value setting circuit.

In this way, when the power supply voltage of 5 V is turned on when both the input signals A and A are at the L level,
The second CMOS inverter 3 outputs the H level first, and that state is maintained. Therefore, the node N3 becomes H level (5v), and the third CMOS inverter 4 outputs an output signal B of L level (ground level). That is, the initial value is 0. Also, the second CMOS
The threshold voltage of inverter 3 may be set to a value higher than the threshold voltage of first CMOS inverter 2. In this case, when the power supply voltage of 5 V is applied when both the input signals A and A are at the L level, the node N3 goes to the L level (ground level) and the third C
MOS inverter 4 outputs an output signal B of H level (5v). That is, the initial value is 1.

Therefore, the initial value can be set without increasing the number of transistors. In the level converter 10 of the second embodiment, the threshold voltage of the second CMOS inverter 3 may be set to a value higher than the threshold voltage of the first CMOS inverter 2. Further, in the level converter 15 of another example, the threshold voltage of the first CMOS inverter 2 may be set to a value higher than the threshold voltage of the second CMOS inverter 3. In this alternative example, first and second CMOS inverters 2 and 3 and a first
And the second capacitors C1 and C2 constitute an initial value setting circuit.

Thus, the first and second capacitors C
The effect of the coupling phenomenon of C1 and C2 is compensated, and the initial value can be set reliably. In the level converter 10 of the second embodiment, one of the first and second capacitors C1 and C2 may be omitted. For example, even when the first capacitor C1 is omitted, the second capacitor C2 sets the level of the node N3 to L.
Node N to work down to the level
3 is held at the L level. Also, for example, the second capacitor C
2 is omitted, the first capacitor C1 is connected to the node N
The node N3 is held at the L level because the node N3 works to raise the level of the node N4 toward the H level. Therefore, this initial value is 1. As a result, the initial value “1” can be set by reducing the number of capacitors. In the level converter 15 of another example, the first and second capacitors C
Either one of C1 and C2 may be omitted. By doing so, the initial value “0” can be set by reducing the number of capacitors.

The level converters 1, 10, 15, 20, and 25 of the above-described embodiments and other examples may be connected instead of the level converter 51 of FIG. By doing so, the level converters 1, 10, 15, 20, 25,
Output buffer circuit 53 composed of CMOS inverter
When the power supply voltage of 3 V is not supplied to the internal circuit 50, that is, when the input signals A,
When the power supply voltage of 5 V is turned on when both the A bars are at the L level, the level converters 1, 10, 15, 20, 25
The output signal B output from the controller becomes either an L level (ground level) or an H level (5v). Therefore,
Both the transistors Tr1 and Tr2 of the output buffer circuit 53 are not turned on, and no through current flows from the power supply to the ground GND. As a result, normal operation of the output circuit is guaranteed while reducing power consumption of the semiconductor device. The level converter 1 in which the initial value is set
When 0, 15, 20, and 25 are used, the initial value of the output circuit is also determined, so that the operation of the circuit connected to the output terminal 54 can be reliably controlled.

Although the level converter 10 is used in the fourth embodiment, a level converter 25 may be used instead of the level converter 10. Even in this case, the same effect as the effect of the fourth embodiment can be obtained. Further, the area occupied by the level converter 25 in the layout area of the semiconductor device can be reduced.

Also, level converters 15 and 20 may be used in place of level converter 10. With this configuration, when the power supply voltage of 5 V is turned on when both the input signals P and P are at the L level, the external terminal 32 enters a high impedance state. Therefore, the operation of the next stage circuit can be reliably controlled.

[0100] 3v and 5 in the above embodiments and other examples
The power supply of v may be implemented as a power supply of another voltage value. -Level converter 2 of the third embodiment and another example
At 0 and 25, the source of the transistor Tr20 is connected to the ground GND, but may be connected to a power supply of 5V. By doing so, the initial value is inverted.

[0101]

As described above in detail, according to the first aspect of the present invention, the circuit operates normally even when the buffer signal is in an undefined state.

According to the second aspect of the present invention, a binary output signal is reliably output. According to the third aspect of the present invention, when the high voltage power supply is turned on, the output holding circuit outputs a binary output signal having a set initial value.

According to the present invention, the initial value of the binary output signal outputted when the high voltage power supply is turned on while the buffer signal is in an undefined state is one of the binary output signals. Is determined.

According to the present invention, the output circuit operates normally. According to the ninth aspect of the present invention, the initial state of the pull-up when the high voltage power is turned on with the buffer signal in an indefinite state is set.

According to the tenth aspect, the initial state of the mode when the high voltage power supply is turned on with the buffer signal in an indefinite state is set.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a level converter according to the first embodiment;

FIG. 3 is a circuit diagram showing a level converter (initial value 1) according to a second embodiment;

FIG. 4 is a circuit diagram showing a level converter (initial value 0) according to another example of the second embodiment;

FIG. 5 is a circuit diagram showing a level converter (initial value: 0) according to a third embodiment;

FIG. 6 is a circuit diagram showing a level converter (initial value 1) according to another example of the third embodiment;

FIG. 7 is a circuit diagram showing an output circuit for pull-up resistance control according to a fourth embodiment;

FIG. 8 is a circuit diagram showing an input / output circuit according to a fifth embodiment.

FIG. 9 is a circuit diagram showing another example of the input / output circuit of the fifth embodiment.

FIG. 10 is a circuit diagram showing an output unit.

FIG. 11 is a circuit diagram showing a conventional level converter.

FIG. 12 is a waveform chart showing a difference in a supply time of a power supply voltage.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 100 Input buffer circuit 101 Level conversion part 102 Output holding circuit A Binary input signal X1, X2 Buffer signal Y Binary output signal

Claims (10)

[Claims] 1. An input buffer circuit to which a binary input signal having an amplitude based on a low-voltage power supply is input, and a high-level binary input signal based on a pair of buffer signals output from the input buffer circuit. A level converter for converting the signal into a binary output signal having an amplitude based on a voltage power supply and outputting the binary signal. The level converter includes a buffer signal when the buffer signal is in an undefined state. 2 based on the potential difference of
A level converter comprising an output holding circuit for outputting a value output signal. 2. An output holding circuit and a level converter, wherein input terminals and output terminals of first and second CMOS inverters operating on a high voltage power supply are connected to each other. A first input transistor is connected in series between an output terminal of a first CMOS inverter and a low-potential-side power supply, and the second CMOS
A second input transistor is connected in series between an output terminal of the inverter and a low potential side power supply, and one of the first and second input transistors is turned on based on the binary input signal. The level converter according to claim 1, wherein the buffer signal is output by performing the above operation. 3. The output holding circuit according to claim 1, further comprising an initial value setting circuit for setting an initial value of the binary output signal when a high voltage power supply is turned on. Level converter. 4. The initialization value setting circuit according to claim 1, wherein one of the output terminals of the first and second CMOS inverters is connected to one of a high-potential power supply and a low-potential power supply via a capacitor. The level converter according to claim 3, characterized in that: 5. An initial value setting circuit interposed between an output terminal of one of the first and second CMOS inverters and one of a high potential side power supply and a low potential side power supply. 4. The level converter according to claim 3, further comprising a transistor for resetting, and a reset signal output circuit for turning on the transistor for initial value setting for a predetermined time based on turning on a high voltage power supply. 6. The level converter according to claim 3, wherein said initial value setting circuit configures threshold voltages of said first and second CMOS inverters as different values. 7. The first and second CMs having different values of the capacitance and a threshold voltage.
5. The level converter according to claim 4, comprising an OS inverter. 8. An output circuit for driving an output buffer circuit based on a binary output signal of the level converter according to claim 1. Description: 9. A transistor for pull-up control, which is connected to a high-potential-side power supply via a resistor, based on the binary output signal of the level converter according to claim 3. An output circuit characterized by the above. 10. An output mode for outputting an output signal from an output buffer circuit based on the binary output signal of the level converter according to claim 3, and an output signal of the output buffer circuit is undefined. An input / output circuit characterized by switching between an input mode for setting a state and an input mode.