JP2000124792A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent increase of the scale in a level shift circuit by connecting a 1st inverter means to a 2nd input part, connecting an output part to the input part of the 1st inverter means and pulling up the outputs of the 1st and 2nd inverter means. SOLUTION: The output part of a 1st inverter 1 is connected to the input part of a 2nd inverter 2 and then to a 2nd output terminal 8 and the drain of a P-channel MOS transistor TR 4. The source and the gate of the TR 4 are connected to a power supply VDD and a 2nd input terminal 7, respectively. The output part of the inverter 2 is connected to the input part of the inverter 1 and then to a 2nd output terminal 6 and the drain of a 3rd P-channel MOS TR 3. The source and the gate of the TR 3 are connected to the power supply VDD and a 1st input terminal 5, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a level shift circuit.

[0002]

2. Description of the Related Art In a circuit having two power supply systems, a level shift circuit is a circuit for converting an output signal level from one power supply system into an input signal level to the other power supply system.

FIG. 4 shows an example of a conventional level shift circuit. Hereinafter, a conventional level shift circuit will be described with reference to FIG. In the configuration of the figure, reference numeral 21 denotes a first p-channel MOS transistor 21A and a first n-channel MOS transistor 21A.
A first inverter including a channel MOS transistor 21B, and a second inverter 22 include a second p-channel MOS transistor 2B.
2A and a second inverter 23A composed of a second n-channel MOS transistor 22B, and a third inverter 23A
An OS transistor, 23B a third n-channel MOS transistor, 24A a fourth p-channel MOS transistor, 24B a fourth n-channel MOS transistor,
25 is a fifth n-channel MOS transistor, 26 is a sixth n-channel MOS transistor, 27 is an input terminal,
28 is a first output terminal, 29 is a second output terminal, and 30 is a connection terminal to the power supply VSS2.

It is assumed that a signal from a circuit driven by a power supply VSS1 (not shown) is input to the input terminal 27.

[0005] Regarding the operation of the level shift circuit configured as described above, when the signal I input to the input terminal 27 is a low level voltage (hereinafter referred to as "L") (1) and when the signal I is a high level voltage (Hereinafter “H”) (2)
Will be described.

(1) When the signal I input to the input terminal 27 is L. When the signal I is L, the first p-channel MOS transistor 21A and the first n-channel MOS transistor 2
The output of the first inverter 21 composed of 1B becomes H (point A).

When the voltage level at the point A becomes H,
The input of the second inverter including the second p-channel MOS transistor 22A and the second n-channel MOS transistor 22B becomes H, and the output of the second inverter 22 becomes L (point B). When the point B becomes L, the fourth p-channel MOS transistor 24A is turned on, and the fourth n-channel MOS transistor 24A is turned on.
B turns off. For this reason, the voltage level of the second output terminal 29 becomes H. On the other hand, since the point A is at H, the third p-channel MOS transistor 23A is turned off, the third n-channel MOS transistor 23B is turned on, and the second output terminal 29 is at H as described above. For this reason, the fifth n-channel MOS transistor 25 is turned on, and the first output terminal 28 is set to L.

(2) When the input signal I input to the input terminal 27 is H. When the signal I is H, the first p-channel MOS transistor 21A and the first n-channel MOS transistor 2
The output of the first inverter 21 composed of 1B becomes L (point A). When the voltage level at the point A becomes L, the second p-channel MOS transistor 22A and the second n
The output of the second inverter 22 including the channel MOS transistor 22B becomes H (point B). As mentioned above, A
Since the point is L, the third p-channel MOS transistor 23A is turned on, the third n-channel MOS transistor 23B is turned off, and the output of the first output terminal 28 becomes H. Further, as described above, since the point B is H, the fourth p-channel MOS transistor 24A is turned off, and the fourth n-channel MOS transistor 24A is turned off.
Since B is turned on and the first output terminal 28 is H, the sixth n-channel MOS transistor 26 is turned on, and the output of the second output terminal 29 is L. The above operations are summarized in the following table, and the level shift operation is performed.

[0009]

[Table 1]

[0010]

However, in the case where the level shift circuit has the above configuration, the level shift circuit is connected to the output terminals 28 and 29 rather than the power supply system VSS1 of the signal I input to the input terminal 27. When the voltage of the power supply system VSS2 of the output signal to be output is low, the third n-channel MOS transistor 23B and the fourth n-channel
Since neither of the S transistors 24B is completely turned off, a through current flows when a signal changes. In addition, power supply V
As the voltage difference between SS1 and power supply VSS2 increases, this through current increases, which causes a problem that the response of the level shift circuit becomes slow.

Further, depending on the size of each transistor, the operation as a level shift circuit may not be performed for the following reasons, and there is a problem that it is difficult to adjust the size of the transistor. That is, in the figure, the fourth p-channel MOS transistor 24A,
Three transistors, a fourth n-channel MOS transistor 24B and a sixth n-channel MOS transistor 26, are connected in series.

When VSS1 is substantially equal to VSS2, the circuit operation is performed in correspondence with the H level and L level of these transistors, respectively.
In the case of VSS2, the H level and the L level do not correspond to each other, and the fourth n-channel MOS transistor 24B does not turn off. As a result, the through current increases and the circuit operation slows down. In the case where VSS1 and VSS2 are almost equal, when high-speed operation is important, it is necessary to increase the gate width in order to reduce the on-resistance of the fourth n-channel MOS transistor 24B. Also, V
To ensure a reliable circuit operation when SS1 >> VSS2, the fourth p-channel MOS transistor 24
It is necessary to set the ON resistance of A to the ON resistance of the fourth n-channel MOS transistor 24B. As described above, it is necessary to design a transistor in consideration of various conditions. Further, when data is transferred from one logic system to another logic system and data is held by a latch circuit, the level shift circuit and the latch circuit are provided separately, so that the circuit scale is increased. There was a problem of being connected.

[0013]

Means for Solving the Problems In order to solve the above problems, the present invention has been made as follows. In the first invention, the first inverter means and the second inverter means having an output portion connected to the input portion of the first inverter means and an output portion connected to the input portion of the first inverter means. And means for pulling up the output of the first inverter means and means for pulling up the output of the second inverter means.

In the second invention, a first input terminal and a second input terminal, a first output terminal and a second output terminal, and an input portion of the first input terminal and the second output terminal serve as a first output terminal. A first inverter having an output connected to the second output terminal, a second inverter having an input connected to the second output terminal, and an output connected to the first output terminal; A first p-channel MOS transistor having a drain connected to the first output terminal and a gate connected to the first input terminal to pull up an output of the second inverter; A second p-channel MOSFET whose drain is connected to the second output terminal and whose gate is connected to the second input terminal to pull up the output of the inverter.
And a level shift circuit composed of an S transistor.

According to a third aspect of the present invention, the output section of the decoder circuit is connected to each input section of the pull-up means.

[0016]

By configuring the level shift circuit in this manner, if the on-resistance of the first p-channel MOS transistor is sufficiently low with respect to the output of the first inverter, 2
It operates reliably irrespective of the voltages of the two power supply systems, and the response speed does not become extremely slow. Further, the size of the transistor can be easily adjusted. Further, the drain is connected to the first output terminal to pull up the first inverter,
Also, the first p-gate whose gate is connected to the first input terminal
In order to pull up the channel MOS transistor and the second inverter, the drain thereof is connected to the second output terminal.
Also, the second gate whose gate is connected to the second input terminal
By setting both input terminals of the channel MOS transistor to H, signals output to the first output terminal and the second output terminal can be latched.

[0017]

FIG. 1 shows a first embodiment of the present invention. Hereinafter, the operation of the embodiment of FIG. 1 will be described. In the configuration of FIG. 1, reference numeral 1 denotes a first p-channel MOS transistor 1A and a first n-channel MOS transistor 1A.
B, a first inverter 2 and a second p-channel M
A second inverter 3 including an OS transistor 2A and a second n-channel MOS transistor 2B is a third p-channel M for pulling up the second inverter 2.
The OS transistor 4 is a fourth p-channel MOS transistor for pulling up the first inverter 1,
Is a first input terminal, 6 is a first output terminal, 7 is a second input terminal, and 8 is a second output terminal.

The output of the first inverter 1 is connected to the input of the second inverter 2 and to the second output terminal 8 and the drain of the fourth p-channel MOS transistor 4. The source of the fourth p-channel MOS transistor 4 is connected to the power supply VDD, and its gate is connected to the second power supply VDD.
Are respectively connected to the input terminals 7. On the other hand, the output of the second inverter 2 is connected to the input of the first inverter 1, and is also connected to the second output terminal 6 and the drain of the third p-channel MOS transistor 3. Further, the source of the third p-channel MOS transistor 3 is connected to the power supply VDD, and its gate is connected to the first input terminal 5.
It is connected to the.

Next, the operation of the level shift circuit shown in FIG. The signal IX to the first input terminal 5 in FIG.
Next, consider the case where the signal I to the second input terminal 7 is set to H. Since the voltage level L of the first input terminal 5 (IX) is applied to the gate of the third p-channel MOS transistor 3, the transistor of the third p-channel MOS transistor 3 is turned on, and as a result, 1 output terminal 6 becomes H. The voltage level H of the second input terminal 7 is the fourth level.
Is applied to the gate of the p-channel MOS transistor 4, the fourth p-channel MOS transistor 4 is turned off, but the first p-channel MOS transistor 1A and the first n-channel MOS transistor 1B The above-described H of the first output terminal 6 is input to the inverter, and the output of the inverter is L, so that the second output terminal 8 is L. Further, the second p-channel MOS transistor 2A and the second n-channel MOS transistor 2A
Since the input of the second inverter made of B is L, the output of the second inverter becomes H, outputs H to the first output terminal 6, and enters a steady state.

Next, the signal IX applied to the first input terminal 5 is set to H, and the signal I applied to the second input terminal 7 is set to L.
Consider the case. Since the second input terminal 7 (I) becomes L, the fourth p-channel MOS transistor 4 is turned on. A second p-channel MOS is connected to the second output terminal 8.
The output H of the transistor 4 and the previous output L of the first inverter including the first p-channel MOS transistor 1A and the first n-channel MOS transistor 1B collide with each other and a through current flows. MOS
Since the ON resistance of the fourth p-channel MOS transistor 4 is made lower than the ON resistance of the transistor 1B, the second output terminal 8 becomes H. This signal change is
Second p-channel MOS transistor 2A and second n-channel MOS transistor 2A
The first output terminal 6 is changed to L through the second inverter 2 including the channel MOS transistor 2B.
Since the first input terminal 5 (IX) is at H, the third p-channel MOS transistor 3 is turned off, and no through current flows here. Further, since the first output terminal 6 has become L, the output of the first inverter 1 including the first p-channel MOS transistor 1A and the first n-channel MOS transistor 1B changes to H, and the second The collision of the signal at the output terminal 8 is resolved, and a steady state is set.

Further, the signal IX applied to the first input terminal 5 is set to L, and the signal I applied to the second input terminal 7 is set to H
Consider the case. Since the first input terminal 5 (IX) becomes L, the third p-channel MOS transistor 3 is turned on. The first output terminal 6 has a third p-channel M
The output H of the OS transistor 3 and the second p-channel MO
The previous output L of the second inverter 2 comprising the S transistor 2A and the second n-channel MOS transistor 2B
And the through current flows, but the second p-channel MOS transistor 3 has an on-resistance lower than the on-resistance of the second n-channel MOS transistor 2B. H. This signal change causes the second output terminal 8 to change to L through the first inverter 1 including the first p-channel MOS transistor 1A and the first n-channel MOS transistor 1B. Since the second input terminal 7 (I) is at H level, the fourth p
The channel MOS transistor 4 is turned off, and no through current flows here. Further, when the second output terminal 8 becomes L, the output of the second inverter 2 including the second p-channel MOS transistor 2A and the second n-channel MOS transistor 2B changes to H and the first The collision of signals at the output terminal 6 is resolved, and a steady state is set.

Further, a case is considered where both the signal IX applied to the first input terminal 5 and the signal I applied to the second input terminal 7 are set to H. Since both the first input terminal 5 (IX) and the second input terminal 7 (I) become H, the third p-channel MOS transistor 3 and the fourth p-channel MOS transistor 4 are both turned off. . Since the H of the first output terminal 6 and the L of the second output terminal 8 do not change, the outputs of the first inverter 1 and the second inverter 2 are fixed without any change. This is because the signal I to the second input terminal is low and the signal IX to the first input terminal is high, and the signal I to the second input terminal and the signal IX to the first input terminal are low. Similarly, when both are changed to H, the first output terminal 6 is set to L and the second output terminal
Is fixed at H. That is, by setting both the inputs of the first input terminal 5 and the second input terminal 7 to H, the outputs of the first and second output terminals are latched.

FIG. 2 shows a second embodiment of the present invention, which is a circuit example in which a decoder circuit is added to the level shift circuit of FIG.

In FIG. 2, only those added to FIG. 1 will be described. 9 is a third inverter and 10 is a first N
An AND gate circuit, 11 is a second NAND gate circuit,
12 is a third input terminal, and 13 is a fourth input terminal.
The third input terminal 12 is input to the third inverter 9 and becomes one input of the second NAND gate circuit 11, and the output of the third inverter 9 is connected to one input of the first NAND gate circuit 10. Become. Also, the fourth input terminal 13
Is the other input of each of the first NAND gate circuit 10 and the second NAND gate circuit 11, and the third inverter 9, the first NAND gate circuit 10, and the second NAND gate circuit 11 control the decoder circuit 14. Make up. In FIG. 2, the output of the second NAND gate circuit 11 forming the decoder circuit 14 is connected to the gate input of the third p-channel MOS transistor 3, so that the first input terminal 5 And the gate input of the fourth p-channel MOS transistor 4 is connected to the first NA of the decoder circuit 14.
The connection of the output of the ND gate circuit 10 eliminates the second input terminal 7. The operation of the level shift circuit to which the decoder circuit of FIG. 2 is added is as follows.

(1) The input signal of the fourth input terminal 13 is set to H
And if. When the input signal I is L, the first NAND gate circuit 10
Is L, the output of the second NAND gate circuit 11 is H, and when the input signal I is H, the first NA
The output of the ND gate circuit 10 becomes H, and the second NAND
The output of the gate circuit 11 becomes L.

(2) The input signal of the fourth input terminal 13 is set to L
And if. When the input signal I is L, the first NAND gate circuit 10
Is H, the output of the second NAND gate circuit 11 is also H, and when the input signal I is H, the first NA
The output of the ND gate circuit 10 becomes H, and the second NAND
The output of the gate circuit 11 also becomes H.

That is, when the input of the fourth input terminal 13 is set to H, the input of the third input terminal 12 is switched to H or L, so that the level shift operation as described in FIG. By setting the input terminal 13 of L to L, a function of latching the output regardless of whether the signal I is H or L is provided.

FIG. 3 shows that in the embodiment of FIG. 1, each transistor is a p-channel MOS transistor and an n-channel MOS transistor.
5 shows a circuit in which each OS transistor is replaced. The operation is the same as in FIG. 1, and the description is omitted.

[0029]

As described above, the use of the level shift circuit having the configuration according to the present invention does not cause a reduction in the operation speed and facilitates the design of the transistor. Further, in addition to the function of the level shift circuit as described above, the circuit can have a function as a latch circuit, so that the circuit scale can be reduced as compared with a case where a latch circuit is separately provided for the level shift circuit. It can be significantly reduced.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention.

FIG. 2 shows a second embodiment of the present invention.

FIG. 3 shows a third embodiment of the present invention.

FIG. 4 shows a conventional level shift circuit.

[Explanation of symbols]

1 First p-channel MOS transistor 1A and first p-channel MOS transistor 1A
First inverter composed of n-channel MOS transistor 1B, second p-channel MOS transistor 2A and second inverter
3rd p-channel MOS transistor 4 4th p-channel MOS transistor 5 1st input terminal 6 1st output terminal 7 2nd input terminal 8 2nd Output terminal 9 Third inverter 10 First NAND circuit 11 Second NAND circuit 12 Third input terminal 13 Fourth input terminal 21 From first p-channel MOS transistor 21A and first n-channel MOS transistor 21B A first inverter 22 A second inverter 23A including a second p-channel MOS transistor 22A and a second n-channel MOS transistor 22B 23A A third p-channel MOS transistor 23B A third n-channel MOS transistor 24A A fourth p Channel MOS transistor 24B Four n-channel MOS transistors 25 Fifth n-channel MOS transistor 26 Sixth n-channel MOS transistor 27 Third input terminal 28 Third output terminal 29 Fourth output terminal 30 Power supply terminal

Claims (3)

[Claims] A first input terminal and a second input terminal;
A first inverter having a first output terminal and a second output terminal, an input portion connected to the first output terminal, an output portion connected to the second output terminal, The output of the first inverter is connected to the input thereof, the output of the second inverter is connected to the input of the first inverter, and the control amount applied to the first input terminal is controlled by the second inverter. Means for pulling up the output of the first inverter means accordingly, and means for pulling up the output of the second inverter means according to a control amount applied to the second input terminal. A level shift circuit. 2. A first input terminal and a second input terminal,
A first inverter having a first output terminal and a second output terminal, an input portion thereof connected to the first output terminal, an output portion thereof connected to the second output terminal, and an input portion thereof; Is connected to the second output terminal, the output of the second inverter is connected to the first output terminal, and the drain of the second inverter is connected to the first inverter to pull up the output of the second inverter. A first p-channel MOS transistor having a gate connected to the first input terminal and a drain connected to the second inverter for pulling up the output of the first inverter. And a second p-channel MOS transistor having a gate connected to the second input terminal. 3. A level shift circuit according to claim 1, wherein an output of a decoder circuit is connected to each input of said pull-up means.