JPH0983343A - Signal level conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal level conversion circuit consisting of an inverter circuit and a level conversion circuit which can increase the signal level conversion speed and also can reduce the power consumption by eliminating a long time when the potential of an output signal line shifts after the potential of an input signal line shifts and also eliminating occurrence of a through current. SOLUTION: An inverter circuit (transistors TR P1 and N1) outputs the potential level of a 2nd power line 102 when the input signal of an input signal line 105 is equal to the potential of a 3rd power line 103 and then outputs the potential level of a 1st internal power line 107 when the input signal of the line 105 is equal to the potential of the line 103 respectively. Then a switch circuit (TR P2, P3, P4 and N5) outputs the potential of the line 103 to the line 107 when the input signal of the line 105 is equal to the potential of the power line 103 and then outputs the potential of a 1st power line 101 to the line 107 when the input signal of the line 105 is equal to the potential of the line 102 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal level conversion circuit composed of a semiconductor device, and more particularly to a high speed signal level conversion circuit with reduced power consumption.

[0002]

2. Description of the Related Art An example of a conventional level conversion circuit of this type is shown in FIG. The first power supply 101 includes a first power supply line 101 having a high potential, a second power supply line 102 having a low potential, and a third power supply line 103 having a potential slightly lower than the potential of the first power supply line 101. Between the line 101 and the second power supply line 102, cross-connected pMOS transistors P11 and P12, and nMOs cascade-connected to the drains of these transistors.
The S transistors N11 and N12 are connected. Also,
PM between the third power line 103 and the second power line 103
OS transistor P13 and nMOS transistor N13
The inverter circuit composed of is connected. The input signal line 105 is connected to the gates of the transistors P13 and N13, and the transistors P12 and N13 are connected to each other.
The output signal line 106 is connected to the 12 connection points.

In this configuration, the input signal line 10 is now
When the potential level of 3 is the same as the potential of the second power supply line 102, that is, at the low level, the potential of the gate terminal of the nMOS transistor N11 becomes the same as the potential of the third power supply line 103, and the gate terminal of the nMOS transistor N12. Is the same as the potential of the second power supply line 102. Therefore, the nMOS transistor N11 is turned on, the nMOS transistor N12 is turned off, and p
The drain terminal of the MOS transistor P11 becomes equal to the potential level of the second power supply line 102. Therefore, pM
The OS transistor N12 is turned on, and the potential of its drain terminal becomes the same as the potential of the first power supply line 101. That is, when the potential of the input signal line 105 is the same as the potential of the second power supply line 102, the potential of the output signal line 106 is the same as the potential of the first power supply line 101, which is a high level.

On the other hand, when the potential level of the input signal line 105 is the same as the potential of the third power supply line 105, that is, at the high level, the potential of the gate terminal of the nMOS transistor N11 is the same as the potential of the second power supply line 102. And nMO
The potential of the gate terminal of the S transistor N12 becomes the same as the potential of the third power supply line 103. Therefore, the nMOS transistor N12 is turned on, the nMOS transistor N11 is turned off, and the pMOS transistor P1 is turned on.
The drain terminal of 1 becomes equal to the potential level of the second power supply line 102. Therefore, the pMOS transistor P11
Is turned on, and the potential of its drain terminal becomes the same as the potential of the first power supply line 101. That is, when the potential of the input signal line 105 is the same as the potential of the third power supply line 105,
The potential of the output signal line 106 becomes the same as the potential of the second power supply line, and becomes low level.

[0005]

In this conventional signal level conversion circuit, the input signal line 105 is the second power supply line 102.
Of the first power supply line 101 after the transition from the potential level of the first power supply line 103 to the potential level of the third power supply line 103.
The nMOS transistor N12 is turned on when a transition is made between the potential level of PMOS and the potential level of the second power supply line 102, but the transistors P13 and N of the pMOS and nMOS are turned on.
After the delay time of the inverter circuit composed of 13 nMOS
The transistor N11 is turned off. On the other hand, the input signal line 1
05 transits between the potential level of the third power supply line 103 and the potential level of the second power supply line 102, and then the output signal line 1
If 06 transits between the potential level of the second power supply line 102 and the potential level of the first power supply line 101, nMO
S-transistor N12 turns off, but pMOS, nM
The nMOS transistor N11 is turned on after the delay time of the inverter circuit including the transistors P13 and N13 of the OS.

The nMOS transistor N12 is turned on, N1
When 1 is off, the drain terminal of the pMOS transistor P11 and the gate terminal of P12 are at the potential level of the first power supply line 101, and the gate terminal of P11 and the drain terminal of P12 are at the potential level of the second power supply line 102. ing. On the other hand, when the nMOS transistor N12 is off and N11 is on, the drain terminal of the pMOS transistor P11 and the gate terminal of P12 are at the potential level of the second power supply line 102, and the gate terminal of P11 and the drain terminal of P12 are the first.
Of the power supply line 101.

Since the pMOS transistors P11 and P12 have a structure in which the gate terminal and the drain terminal are cross-connected to each other, there is a feedback loop, and the drain terminal of the pMOS transistor P11 and the gate terminal of P12 are the first power source. Since the potential level of the line 101, the gate terminal of P11 and the drain terminal of P12 are the second power supply line 10
From the time of transition to the potential level of 2 and when the drain terminal of P11 and the gate terminal of P12 are at the potential level of the second power supply line 102, the gate terminal of P11 and the drain terminal of P12 are connected to the first power supply line 101. It takes a long time to transit to the potential level.

Therefore, the conventional signal level conversion circuit has a problem that it takes a long time from the transition of the potential of the input signal line 105 to the transition of the potential of the output signal line 106. Further, as the potential of the third power supply line 103 becomes lower than that of the first power supply line 101, it becomes necessary to increase the on-currents of the nMOS transistors N11 and N12 as compared with the on-currents of the pMOS transistors P11 and P12. The drive current of the output signal line 106 is reduced. Further, since the time for which the potential of the output signal line 106 changes depends on the direction in which the potential of the input signal line 105 changes, even if a signal with a duty ratio of 50% is input to the input signal line 105, Duty ratio 50%
There is a problem that the signal of cannot be obtained. SUMMARY OF THE INVENTION An object of the present invention is to solve the conventional problems as described above and to provide a high-speed signal level conversion circuit with low power consumption.

[0009]

A signal level conversion circuit according to the present invention includes a first power source having a high potential, a second power source having a low potential, and a third power source having a potential lower than the first power source. And the first
The internal power supply line of the second power supply is output when the input signal is equal to the potential of the third power supply, and the first internal power supply is output when the input signal is equal to the potential of the third power supply. When the input signal is equal to the potential of the third power supply, the potential of the third power supply is output to the first internal power supply line and the input signal of the second power supply is output. A high-speed signal utilizing the fact that a first switch circuit that outputs the potential of the first power supply to the first internal power supply line when it is equal to the potential is used, and the delay time between the input and output of the inverter circuit is short. The level conversion is enabled, and the potential of the first internal power supply line is set to the potential of the first or third power supply line, whereby the transistor of the inverter circuit is completely turned off, the through current is eliminated, and the power consumption is reduced.

Also, the signal level conversion circuit of the present invention comprises a first power source having a high potential, a second power source having a low potential, and the second power source.
And a second internal power supply line having a potential higher than that of the second power supply, the potential level of the second internal power supply line is output when the input signal is equal to the potential of the first power supply, An inverter circuit that outputs the potential level of the first power supply line when the signal is equal to the potential of the fourth power supply, and a fourth internal line to the second internal power supply line when the input signal is equal to the potential of the fourth power supply. And a second switch circuit that outputs the potential of the second power source to the second internal power source line when the potential of the power source is output and the input signal is equal to the potential of the first power source. The short delay time between input and output in the circuit enables high-speed signal level conversion, and the use of the second internal power supply line eliminates shoot-through current and reduces power consumption.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. In the figure, a first power supply line 101 having a high potential, a second power supply line 102 having a low potential, and the first power supply line 102
Third power supply line 103 having a potential slightly lower than the power supply line 101 of
And a first internal power supply line 107. further,
When the input signal input to the input signal line 105 is equal to the potential of the third power supply line 103, the potential level of the second power supply line 102 is output, and when the input signal is equal to the potential of the third power supply line 103. To the inverter circuit for outputting the potential level of the first internal power supply line 107, and when the input signal is equal to the potential of the third power supply line 103.
The potential of the third power supply line 103 is output to the first power supply line 103, and the potential of the first power supply line 101 is output to the first internal power supply line 107 when the input signal is equal to the potential of the second power supply line 102.
And a switch circuit. Signal level conversion circuit.

In the inverter circuit, the source and drain of the first pMOS transistor P1 and the first nMOS transistor N1 are connected in cascade, the connection point is connected to the output signal line 106, and the gates are connected to each other to input the input signal. Line 105
Connected to

In the first switch circuit, the source is connected to the first power supply line 101, the drain is connected to the first internal power supply line 107, and the gate is connected to the first internal signal line 108. PMOS transistor P2, the source thereof is connected to the first power supply line 101, the drain thereof is connected to the first internal signal line 108, and the gate thereof is connected to the first internal power supply line 107, and the source thereof. Is the first internal signal line 108, and the drain is the input signal line 1
05, a fifth nMOS transistor N5 having a gate connected to the third power supply line 103, a source for the input signal line 105, and a drain for the first internal power supply line 107.
And a fourth pMOS transistor P4 whose gate is connected to the second power supply line 102, respectively.

According to this configuration, when the input signal line 105 is at a high level, that is, the potential of the third power supply line 103 which is lower than the potential of the first power supply line 101, the first pMOS transistor P1 and the nMOS transistor N1 are connected. In the inverter circuit, the nMOS transistor N1 is turned on and pM
Since the OS transistor P1 is turned off, the output signal line 1
A low level signal, that is, a signal of the potential of the second power supply line 102 is output to 06. At this time, the input signal line 1
Since 05 is at a high level, the fourth pMOS transistor P4 is turned on and the fifth nMOS transistor N5 is turned off, so that the potential of the first internal power supply line 107 becomes the input signal line 1
This is equal to the potential of the third power supply line 103, which is the potential of 05. Therefore, the third pMOS transistor P3 is turned on and the second pMOS transistor P2 is turned off,
Furthermore, the first pMOS transistor P1 is completely turned off, there is no through current that constantly flows between the first power supply line 101 and the second power supply line 102, and low power consumption is achieved.

When the input signal line 105 becomes low level,
The fourth pMOS transistor P4 is turned off and the fifth nMO
Since the S transistor N5 is turned on and the second pMOS transistor P2 is turned on, the third pMOS transistor P3 is turned off and the potential of the first internal power supply line 107 becomes equal to that of the first power supply line 101. In addition, the first nMOS transistor N1 of the inverter circuit is off, and the first pM
Since the OS transistor P1 is on, the output signal line 1
A high level, that is, the potential of the first power supply line 101 is output to 06. At this time, the first nMOS transistor N
Since 1 is off, there is no through current that constantly flows between the first power supply line 101 and the second power supply line 102, and it is possible to reduce power consumption.

When the input signal line 105 changes from the high level to the low level, or when the input signal line 105 changes from the low level to the high level, the potential of the output signal line 106 has no signal feedback unlike the conventional circuit. 1 pMOS,
Since it changes immediately through the nMOS transistors P1 and N1, high-speed signal level conversion is possible.

That is, in this first embodiment, pM
By utilizing the fact that the replacement time between the input and output of the inverter circuit composed of the OS transistor P1 and the nMOS transistor N1 is short, high-speed signal level conversion is possible. Further, the potential of the third power supply line 103, which is lower than the potential of the first power supply line 101, is used, but this does not completely turn off one of the transistors forming the inverter circuit. However, by setting the potential of the first internal power supply line 107 to the potential of the first or second power supply line, the transistor is completely turned off, a through current is eliminated, and power consumption is reduced.

FIG. 2 is a circuit diagram of the second embodiment of the present invention. In the figure, a high-potential first power supply line 101,
The second power supply line 102 of low potential and the second power supply line 10
It has a fourth power supply line 104 having a potential slightly higher than the second potential and a second internal power supply line 109. Further, the input signal input to the input signal line 105 is the first power line 101.
An inverter circuit that outputs the potential level of the second internal power supply line 109 when the input signal is equal to the potential of the first power supply line 104 and outputs the potential level of the first power supply line 101 when the input signal is equal to the potential of the fourth power supply line 104. And the input signal is the fourth power line 10
When the potential of the second internal power supply line 109 is equal to
Of the second internal power supply line 10 when the potential of the power supply line 104 is output and the input signal is equal to the potential of the first power supply line 101.
9 is provided with a second switch circuit for outputting the potential of the second power supply line 102.

The inverter circuit has the same structure as that of the first embodiment. In the second switch circuit, the source is connected to the second power supply line 102, the drain is connected to the second internal power supply line 109, and the gate is connected to the second internal signal line 110. N2, a third nMOS transistor N3 having a source connected to the second power supply line 102, a drain connected to the second internal signal line 110, and a gate connected to the second internal power supply line 109, and a source input signal. The drain is input to the line 105, the drain is input to the second internal signal line 110, the gate is connected to the fourth power supply line 104, and the fifth pMOS transistor N5 is connected to the source; and the source is input to the second internal power supply line 109. Signal line 105
And a fourth nMOS transistor N4 whose gate is connected to the first power supply line 101, respectively.

According to this structure, when the input signal line 105 is at the high level, that is, the potential of the first power supply line 101,
Since the first pMOS transistor P1 of the inverter circuit is turned off and the first nMOS transistor N1 is turned on, a low level signal, that is, a potential signal of the second power supply line 102 is output to the output signal line 106. At this time, the fourth nMOS transistor N4 is turned off, the fifth pMOS transistor P5 is turned on, and the second and third pMOS transistors P5 and P5 are turned on.
Since the MOS transistors P2 and P3 are turned on, the potential of the second internal power supply line 109 becomes equal to the potential of the second power supply line 102. Further, the first pMOS transistor P1 is completely turned off, there is no through current that constantly flows between the first power supply line 101 and the second power supply line 102, and low power consumption is achieved.

On the other hand, when the input signal line 105 is at the low level, that is, the potential of the fourth power supply line 104 which is higher than the potential of the second power supply line 102, the first pMOS transistor P1.
Is turned on and the first nMOS transistor N1 is turned off, so that a high level signal of the potential of the first power supply line 101 is output to the output signal line 106. That is, at this time, since the fourth nMOS transistor N4 is turned on and the fifth pMOS transistor P5 is turned off, the second internal power supply line 108 is connected to the fourth power supply line 104 which is the potential level of the input signal line 105. It becomes equal to the electric potential.
At this time, the second and third pMOS transistors P2,
P3 is turned off. Further, the first nMOS transistor N1 is completely turned off, and the first power line 101 to the second
There is no through current that constantly flows between the power lines 102 of
Low power consumption can be achieved.

When the potential of the input signal line 105 changes from the high level to the low level or from the low level to the high level, the potential of the output signal line 106 does not have a signal feedback unlike the conventional circuit. Therefore, each of the first pMOS and nMOS transistors P of the inverter circuit
Since it changes immediately through 1 and N1, high-speed signal level conversion is possible.

That is, also in the second embodiment, high-speed signal level conversion can be performed by utilizing the fact that the replacement time between the input and output of the inverter circuit composed of the pMOS transistor P1 and the nMOS transistor N1 is short. It will be possible. Further, although the potential of the fourth power supply line 104, which is higher than the potential of the second power supply line 102, is used,
This causes a state in which one of the transistors forming the inverter circuit is not completely turned off. However, by setting the potential of the second internal power supply line 109 to the potential of the first or second power supply line, The transistor is completely turned off to eliminate the through current and reduce the power consumption.

FIG. 3 is a circuit diagram of a third embodiment of the present invention in which the first and second embodiments are integrated. That is, the high-potential first power line 1
01, a second power supply line 102 having a low potential, and a third power supply line 10 having a potential slightly lower than the potentials of the first power supply line 101.
3, the fourth power supply line 104 having a potential slightly higher than the potential of the second power supply line 102, and each of the first and second internal power supply lines 10
7,109. Further, the input signal line 105
When the potential of the input signal input to is equal to the potential of the third power supply line 103, the potential level of the second internal power supply line 109 is output, and when the input signal is equal to the potential of the fourth power supply line 104. An inverter circuit is provided which outputs the potential level of the first internal power supply line 107.

When the input signal is equal to the potential of the third power supply line 103, the potential of the third power supply line 103 is output to the first internal power supply line 107, and the input signal is the fourth power supply line 1.
When the input signal is equal to the potential of the fourth power supply line 104, the first switch circuit which outputs the potential of the first power supply line 101 to the first internal power supply line 107 when the potential of the input signal is equal to the potential of 04. The potential of the fourth power supply line 104 is output to the second internal power supply line 109, and when the input signal is equal to the potential of the third power supply line 103, the second power supply line 1 is connected to the second internal power supply line 109.
And a second switch circuit that outputs the potential of 02.

Here, the inverter circuit is the same as that of the first and second embodiments. Further, the first switch circuit has the same configuration as that of the first embodiment, and the second switch circuit has the same configuration as that of the second embodiment.

According to this structure, when the input signal line 105 is at the high level, that is, the potential of the third power supply line 103 which is lower than the potential of the first power supply line 101, the output signal line 106 is set to the low level by the inverter circuit. That is, the signal of the potential of the second power supply line 102 is output. At this time, the fifth
Since the nMOS transistor N5 and the fourth nMOS transistor N4 are off and the fourth pMOS transistor P4 and the fifth pMOS transistor P5 are on,
The potential of the internal power supply line 107 becomes equal to the potential of the third power supply line 105, and the potential of the second internal power supply line 109 becomes equal to the potential of the second power supply line 102. And the first nM
Since the OS transistor N1 is on, the potential of the second power supply line 102 is output to the output signal line 106, and the first pMO
The S transistor P1 is completely turned off, and there is no through current that constantly flows between the first power supply line 101 and the second power supply line 102.

On the other hand, when the input signal line 105 is at the low level, that is, the potential of the fourth power supply line 104 which is higher than the potential of the second power supply line 102, the inverter circuit causes the output signal line 106 to be at the high level, that is, the first potential. The signal of the potential of the power supply line 101 is output. At this time, the fifth nMOS transistor N5 and the fourth nMOS transistor N4 are turned on, the fourth pMOS transistor P4 and the fifth pMOS transistor N4 are turned on.
Since the transistor P5 is off, the potential of the first internal power supply line 107 becomes equal to the potential of the first power supply line 101,
The potential of the internal power supply line 109 becomes equal to the potential of the fourth power supply line 104. At this time, the first nMOS transistor N1 is completely turned off, and the first power line 101 to the second
There is no through current that constantly flows between the power lines 102 of
Low power consumption can be achieved.

When the input signal line 103 changes from the high level to the low level or from the low level to the high level, the potential of the output signal line 104 has no signal feedback unlike the conventional circuit, so that P10, N11. Since it changes immediately through, high speed signal level conversion is possible.

That is, also in the third embodiment, high-speed signal level conversion can be performed by utilizing the short replacement time between the input and output of the inverter circuit composed of the pMOS transistor P1 and the nMOS transistor N1. What is possible is similar to each of the above-described embodiments. Further, the potential of the third power supply line 103, which is lower than the potential of the first power supply line 101, and the potential of the fourth power supply line 104, which is higher than the potential of the second power supply line 102, are used. But
This causes a state in which one of the transistors forming the inverter circuit is not completely turned off, but the potential of the first and second internal power supply lines 107 and 109 is set to the potential of the first or second power supply line. By doing so, the transistor is completely turned off, a through current is eliminated, and power consumption is reduced.

[0031]

As described above, according to the present invention, basically, the signal level conversion is performed by using the inverter circuit. Therefore, the fact that the delay time between the input and the output of the inverter circuit is short is used to realize the high speed operation. Signal level conversion can be realized. In addition, the first and second internal power supply lines are provided in the circuit, and the potential of the internal power supply line is set to the first or the second depending on the potential of the input signal.
By controlling to the potential of the power supply line, it is possible to completely turn off the transistor forming the inverter circuit, eliminate the through current, and reduce the power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of a signal level conversion circuit of the present invention.

FIG. 2 is a circuit diagram according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a third embodiment of the present invention.

FIG. 4 is a circuit diagram of an example of a conventional signal level conversion circuit.

[Explanation of symbols]

 P1 to P5 p-type MOS transistor N1 to N5 n-type MOS transistor 101 to 104 power supply line 105 input signal line 106 output signal line 107 first internal power supply line 108 first internal signal line 109 second internal power supply line 110 2 internal signal lines

Claims (7)

[Claims] 1. A high-potential first power source, a low-potential second power source, and a lower-potential third power source than the first power source,
A first internal power supply line, the potential level of the second power supply is output when the input signal is equal to the potential of the third power supply,
An inverter circuit that outputs the potential level of the first internal power supply line when the input signal is equal to the potential of the third power supply, and a first internal power supply line when the input signal is equal to the potential of the third power supply. A first switch circuit that outputs the potential of the third power supply and outputs the potential of the first power supply to the first internal power supply line when the input signal is equal to the potential of the second power supply. Characteristic signal level conversion circuit. 2. A high-potential first power source, a low-potential second power source, and a fourth power source having a higher potential than the second power source.
A second internal power supply line, the potential level of the second internal power supply line is output when the input signal is equal to the potential of the first power supply, and the second internal power supply line is output when the input signal is equal to the potential of the fourth power supply. 1
An inverter circuit that outputs the potential level of the power supply line of
When the input signal is equal to the potential of the fourth power supply, the potential of the fourth power supply is output to the second internal power supply line, and the input signal is the first potential.
And a second switch circuit that outputs the potential of the second power supply to the second internal power supply line when the potential of the power supply is equal to the potential of the power supply. 3. A high-potential first power source, a low-potential second power source, and a third power source having a lower potential than the first power source,
A fourth power source having a higher potential than the second power source, and the first and second power sources.
And an internal power supply line, the potential level of the second internal power supply line is output when the input signal is equal to the potential of the third power supply, and the first power supply line is output when the input signal is equal to the potential of the fourth power supply. When the input signal is equal to the potential of the third power supply, the potential of the third power supply is output to the first internal power supply line, and the input signal of the inverter circuit outputs the potential level of the internal power supply line. A first switch circuit that outputs the potential of the first power supply to the first internal power supply line when it is equal to the potential of the power supply; and a second internal power supply line when the input signal is equal to the potential of the fourth power supply. And a second switch circuit that outputs the potential of the second power supply to the second internal power supply line when the potential of the fourth power supply is output to the second internal power supply line and the input signal is equal to the potential of the third power supply. A signal level conversion circuit characterized by. 4. An inverter circuit, wherein the source and drain of a first pMOS transistor and a first nMOS transistor are cascade-connected, the connection point is connected to an output signal line, and each gate is connected to an input signal line. The signal level conversion circuit according to any one of claims 1 to 3, 5. The first switch circuit has a source for the first power supply, a drain for the first internal power supply line, and a gate for the first power supply.
And a second pMOS transistor connected to the internal signal line of the third source, a source connected to the first power supply, a drain connected to the first internal signal line, and a third gate connected to the first internal power supply line for the gate. pMOS transistor and source is first
A fifth nMOS transistor having a drain connected to the input signal line, a gate connected to the third power supply line, a source connected to the input signal line, a drain connected to the first internal power supply line, and a gate And a fourth pMOS transistor connected to the second power supply, respectively.
A signal level conversion circuit according to any one of 3 and 4. 6. The second switch circuit has a source for the second power supply, a drain for the second internal power supply line, and a gate for the second power supply line.
And a second nMOS transistor connected to the internal signal line of the third source, a source connected to the second power supply, a drain connected to the second internal signal line, and a third gate connected to the second internal power supply line for the gate. An nMOS transistor, a source is connected to the input signal line, a drain is connected to the second internal signal line, a gate is connected to the fourth power supply, and a fifth pMOS transistor is connected to the source and the second internal power supply line is connected to the drain. 5. The signal level conversion circuit according to any one of claims 2 to 4, wherein the signal level conversion circuit comprises an input signal line and a fourth nMOS transistor having a gate connected to the first power supply. 7. The first switch circuit has a source for the first power supply, a drain for the first internal power supply line, and a gate for the first power supply line.
And a second pMOS transistor connected to the internal signal line of the third source, a source connected to the first power supply, a drain connected to the first internal signal line, and a third gate connected to the first internal power supply line for the gate. pMOS transistor and source is first
A fifth nMOS transistor whose drain is connected to the input signal line, whose gate is connected to the third power supply line, and whose source is the input signal line, whose drain is the first internal power supply, and whose gate is The second switch circuit has a source for the second power supply, a drain for the second internal power supply line, and a gate for the second internal power supply circuit. A second nMOS transistor respectively connected to the signal line, a source for the second power supply, a drain for the second internal signal line, and a gate for the second
A third nMOS transistor connected to the internal power supply line, a source connected to the input signal line, a drain connected to the second internal signal line, and a gate connected to the fourth power supply for a fifth pMOS transistor. 5. The signal level conversion circuit according to claim 3, wherein the source is a second internal power supply line, the drain is an input signal line, and the gate is a fourth nMOS transistor connected to the first power supply.