JPH04306725A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a through current from flowing to a digital signal input circuit part in accordance with an analog signal inputted to the input circuit part of the digital signal by preventing signal input to the digital signal input circuit part at the time. analog signal input made is selected. CONSTITUTION:In the input/output circuit P of a system, an input pad part 1 is connected to the input of a comparator 2 constituting the input circuit part of the analog signal and the input of an invertor 3. The comparator 2 compares the analog signal with reference voltage and the result is transmitted to CPU 7 through a data bus 6. An N-channel MOS transistor 11 constituting an input prevention means is connected to the C-MOS invertor 3 in series and the output of a flip flop 10 constituting a selection information output means is connected to the gate of the transistor 11. The output node of the C-MOS invertor 3 is connected to the invertor 4 of the next stage and to a high potential power source VDD through a transistor 12.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor device, and more specifically, an input/output circuit in which an analog signal input or output circuit section and a digital signal input circuit section are connected to a common port. The present invention relates to a semiconductor device having:

Some microcomputer systems employ analog/digital input/output circuits that can selectively input (or output) either analog or digital signals in order to increase the versatility of the system. This selection is usually determined by the specifications of the equipment controlled by the microcomputer system.

0003

2. Description of the Related Art The input/output circuit of the above type in a conventional semiconductor device will be explained with reference to FIG. The figure is an example of a circuit diagram of a microcomputer system. In the semiconductor device shown in the figure, in the input/output circuit P, the I/O
The analog signal or digital signal input from the pad section 1 connected to the O pin is passed through a comparator 2 which receives the analog signal input and detects that this signal is above a reference value and outputs this fact, and a digital signal input. C-, which forms an input buffer that receives the signal and outputs it to the inverter 4 at the next stage.
It is input to both of the MOS inverters 3. The outputs of both input circuit units are transmitted to the data bus 6 via the gate 5 which is turned on via a selection signal and an address (not shown).
Furthermore, it is given to the CPU 7 via the data bus 6. The comparator 2 and the C-MOS inverter 3 each receive an input of an analog signal or a digital signal and are in an operating state defined by the input signal level.

0004

[Problems to be Solved by the Invention] In the case of a conventional semiconductor device having an input/output circuit for both analog and digital signals, when an analog signal is input, the C-MOS inverter which is the input circuit for the digital signal is 3 is in the operating state defined by this analog signal. By the way, this analog signal is, for example, 0-5V C
- When the signal level of each of the P-channel and N-channel MOS transistors 3A and 3B constituting the MOS inverter 3 is near the threshold value, for example, around 2V, both MOS transistors 3A and 3B may be conductive in some cases. A through current flows through these, which may result in wasteful power consumption. However, there have been no examples of semiconductor devices having this type of input/output circuit having this problem in the past.

In view of the above-mentioned problems of the conventional semiconductor device, the present invention provides a method for selectively inputting an analog signal or a digital signal (
In a semiconductor device having an input/output circuit for inputting or outputting an analog signal, improvements are made so that power is not wasted in the digital signal input circuit when an analog signal is input or output, thereby achieving input/output with low power consumption. An object of the present invention is to provide a semiconductor device having a circuit.

[0006]

[Means for Accomplishing the Object] FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a pad part forming a port, 2 is an analog signal input circuit part,
3 is a digital signal input circuit section, 10 is selection information output means, and 11 is input blocking means.

In order to achieve the above object, the semiconductor device of the present invention has a semiconductor device in which an analog signal input or output circuit section (2) and a digital signal input circuit section (3) are connected to a common circuit, as illustrated in FIG. selectively one of the analog signal or digital signal is connected to the port (1) of said one port (1)
In a semiconductor device having an input/output circuit in a format in which the selection is an analog signal or a digital signal, the selection information output means (10) outputs information as to whether the selection is an analog signal or a digital signal; The present invention is characterized in that an input blocking means (11) is provided for blocking the input of the digital signal to the input circuit section (3) when indicating the selection of the digital signal.

[0008]

[Operation] The selection information output means outputs information regarding which of the analog signal or digital signal is selected,
In response to this information, the input blocking means blocks the analog signal input from the port from being input to the digital signal input circuit section when the input selection is an analog signal, and as a result, the input blocking means blocks the analog signal input from the port from being input to the digital signal input circuit section. This prevents wasted power consumption that may occur depending on the voltage level of an analog signal.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be further explained with reference to the drawings. Figure 1
In the input/output circuit P of the microcomputer system,
One input of a chopper type comparator 2 which constitutes an analog signal input circuit section and the input of an inverter 3 which constitutes a digital signal input circuit section are connected to the pad section 1 which constitutes an input port. In the comparator 2, the analog signal is compared with the reference voltage which is the other input, and if the input analog signal is equal to or higher than the reference voltage, the output is "1", and if it is less than the reference voltage, the output is "0" to the data bus 6. , and is further transmitted to the CPU 7 via this data bus 6.

An N-channel MOS transistor 11, which serves as input blocking means, is connected in series to the C-MOS inverter 3, and the output of a flip-flop 10, which serves as selection information output means, is connected to the gate of the N-channel MOS transistor 11. There is. The output node n1 of the C-MOS inverter 3 is connected to the input of the second inverter 4 in the next stage, and is connected to the source of the P-channel MOS transistor 12.
It is connected to a high potential power supply VDD via a drain path. The gate of P-channel MOS transistor 12 is commonly connected to the gate of N-channel MOS transistor 11 forming input blocking means. The output of the second inverter 4 is given to the CPU 7 via the gate 5 and data bus 6, which are rendered conductive via address selection and digital signal selection information. Note that the second inverter 4 is also configured as a C-MOS transistor.

The flip-flop 10 is configured as a D flip-flop, and receives a selection information signal together with a latch signal (address) from the CPU 7 via the data bus 6, for example, at the time of its initialization. When a digital signal is selected as an input signal, "1" is input to the D terminal as a selection information signal, and when an analog signal is selected, "0" is similarly input. As a result, the output Q of the flip-flop 10 becomes H level when the input selection is a digital signal, and becomes L level when the input selection is an analog signal.
level.

With the above configuration, when the input selection is an analog signal, N-channel MOS transistor 11 is turned off and P-channel MOS transistor 12 is turned on. As a result, in the C-MOS inverter 3, the current flowing through the source-drain path is blocked regardless of its input.
, and its output node n1 is connected to high potential power supply VDD by P channel MOS transistor 12 and maintained at H level. P-channel MOS transistor 12 prevents node n1 from going to a floating level, thereby preventing the input of inverter 4 at the next stage from floating, thereby preventing a through current that may occur in this inverter.

When the input selection is a digital signal, the N-channel MOS transistor 11 is turned on, and the P-channel MOS transistor 11 is turned on.
The S transistor 12 is turned off, the C-MOS inverter 3 receives the digital signal, operates normally, and transmits the digital signal via the second inverter 4 at the next stage.

As a modification of the embodiment shown in FIG. 1, a P-channel MOS transistor forming the input blocking means is provided in series with the current path of the C-MOS inverter 3 on the high potential power supply VDD side, and an N-channel MOS transistor is provided on the high potential power supply VDD side. A configuration in which the source/drain path is provided between the node n1 and the low potential power supply GND can also be adopted. In addition,
In this case, the selection information is output as an H level when an analog signal is selected, contrary to the above case.

FIG. 2 is a circuit diagram of the second embodiment. In this embodiment, a P-channel MOS transistor 11A and an N-channel MOS transistor 11B connected in series are provided as input blocking means connected in series with the C-MOS inverter 3, and their series connection point is connected to the output node. n2, and further a P channel MOS transistor 11A.
By disposing a third inverter 13 that controls the gate of the MOS transistors 11A and 11B, both MOS transistors 11A and 11B are turned off when an analog signal is selected. Further, a fourth inverter 14 is provided antiparallel to the second inverter 4. The fourth inverter 14 is composed of a MOS transistor with a large on-resistance, and functions as a latch circuit together with the second inverter 4.

When the input circuit is used under the selection of digital signal input, the output node n of the second inverter 4
For example, when node n3 is at H level and the digital signal becomes logic "L", the H level of node n3 turns on the N-channel MOS transistor of the fourth inverter, and this MOS transistor and the digital signal input A series circuit is formed with the P-channel MOS transistor 3A, which is turned on based on the logic of The voltage level is determined by the voltage division ratio.

[0017] The above voltage level is
Because of the high on-resistance of the N-channel MOS transistor of
becomes L level due to the action of the second inverter 4,
Further, due to the action of the fourth inverter, the node n2 becomes a normal H level. Note that when the logic level of the digital signal and the level of node n3 are at voltage levels different from the above, the P-channel MOS of the fourth inverter
Transistor and N-channel MOS transistor 3B, 1
1B, it is latched to a normal signal level in the same way as above.

Furthermore, even if the MOS transistors 11A and 11B constituting the input blocking means are turned off when selecting an analog signal, the nodes n2 and n3 remain at H level or L level through the positive feedback action of both inverters 4 and 14. For example, the voltage level of the node n2 floats near the threshold value of the second inverter 4 to prevent a through current from flowing through the inverter 4.

The above embodiments are shown for the purpose of illustration; for example, the selection information output means is not limited to a flip-flop, and may be used in place of other storage means or simply means for outputting a selection information signal. Enough. Similarly, the input blocking means can be replaced with other well-known circuits. Furthermore, in each of the embodiments, the analog signal input circuit section and the digital signal input circuit section are connected to a common port, but the analog signal output circuit section and the digital signal input circuit section are connected to a common port. A semiconductor device having an input/output circuit connected to a common port with a circuit section is also included in the semiconductor device of the present invention.

[0020]

As explained above, according to the semiconductor device of the present invention, when analog signal input is selected, signal input to the digital signal input circuit section is blocked, so that analog signals are not input to the digital signal input circuit section. Since it is possible to prevent the risk of wasteful power consumption due to a through current flowing through the digital signal input circuit section depending on the signal voltage level, a remarkable effect is achieved in that the power consumption of the semiconductor device can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

FIG. 3 is a conventional circuit diagram.

[Explanation of symbols]

1 Pad part 2 Comparator 3, 4, 13, 14 Inverter 6 Data bus 7 CPU

Claims (1)

[Claims] [Claim 1] Analog signal input or output circuit section (2)
and a digital signal input circuit section (3) are connected to a common port (1), and one of an analog signal or a digital signal is selectively input or output to said one port (1). In a semiconductor device having an input/output circuit, selection information output means (10) outputs information as to whether the selection is an analog signal or a digital signal; 1. A semiconductor device comprising input blocking means (11) for blocking signal input to the input circuit section (3).