JP2601223B2 - Simultaneous bidirectional I / O buffer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to an input / output circuit thereof.

[0002]

2. Description of the Related Art In an input / output circuit of a semiconductor device, a bidirectional buffer for both input and output may be used. These are effective in reducing the number of wirings required for signal transmission between semiconductor devices.

Conventionally, as a bidirectional buffer for both input and output of a semiconductor device, generally, a tri-state buffer type circuit which uses input / output in a time-division manner or an ECL / G
There is a buffer using a connection logic by wired connection, which is used in a TL interface or the like. Note that G
TL (Gunning Tranceiver Logic) is a high-speed low-amplitude interface between CMOS.

[0004] Among these buffers, the response speed is relatively slow due to control of signal switching in a tri-state buffer or the like, and it is difficult to operate at high speed.

In a bidirectional buffer using a wired connection, received data can be defined only as an "OR" or "AND" signal with both output data.

For this reason, the output data from one bidirectional buffer can be received by the other bidirectional buffer only when its own output data is at a high level (A
ND type) or low level (OR type). In other states, the output of the other side cannot be received, and it is impossible to perform data transfer in a state where inputs and outputs are mutually independent.

Conventionally, a simultaneous type bidirectional input / output buffer has been proposed as an interface type capable of transferring completely independent data at high speed with respect to such a bidirectional buffer.

This provides a bidirectional buffer of the form of FIG.
As shown in FIG. 4, a single wiring is connected between two semiconductor devices a and b, and a high level = V
dd, low level = 0, and intermediate level = (Vdd / 2)
This is realized by taking the three values of

More specifically, referring to FIG. 3, in a simultaneous bidirectional buffer IOBUF, a CMOS inverter including a pMOS transistor P1 and an nMOS transistor N1 outputs an output signal from an internal circuit of a semiconductor device (not shown). An output-side circuit that receives an input through the terminal OUT and outputs the drive to the input / output terminal IO is configured. The input side circuit of the simultaneous bidirectional buffer IOBUF has two comparators C, one of which is connected to the input / output terminal IO and the other of which is connected to the input of the selector SEL.
1 and C2 and an input terminal IN for transmitting the output of the selector SEL to an internal circuit of a semiconductor device (not shown). The reference voltages (logic determination levels) of the two comparators C1 and C2
VR1 and VR2 are, for example, 1/4 of the power supply voltage VDD, respectively.
The comparators C1 and C2 determine the signal level of the input / output terminal IO and the logical determination levels VR1 and VR.
2 and outputs the result of comparison.

That is, referring to FIG. 3, in the input side circuit of the simultaneous type bidirectional buffer IOBUF, if the signal input from input / output terminal IO is 1/4 VDD or less, both comparators C1 and C2 output logical signals. When the value “0” is output and the signal input from the IO terminal is equal to or more than ／ VDD, the logical values “1” are both output from the comparators C1 and C2.
Is output, and regardless of the logical value of the output signal OUT input as a selection signal to the selector SEL, the selector SEL
Outputs the signal level of the input / output terminal IO.

The signal level of the input / output terminal IO is 1 /
When it is in the range of 4VDD to 3 / 4VDD, the logical values "1" and "0" are output from the comparators C1 and C2,
One of the comparators C1 and C2 is selectively output from the selector SEL depending on the logical value of the output signal OUT, and the logic of the output of the other party is selected according to the logical value of the output signal OUT of the buffer itself and the level of the input signal. It operates to detect a value.

That is, referring to FIG. 4, when the signal levels of the transmission signals of the two buffers a and b are different, the potential level of the signal line becomes an intermediate level, and the reception signals of the two buffers a and b The logic threshold for the level is switched according to the own transmission signal, and the content of the transmission signal of the other party is determined.

Such a simultaneous type bidirectional input / output buffer does not require a waiting time required for synchronization for switching between transmission and reception as in the case of using a tri-state buffer or the like. High-speed operation becomes possible, and, unlike general wired connection, complete separation of input / output signals is possible.

[0014]

However, it is known that it is difficult to guarantee an intermediate level when a plurality of semiconductor devices are connected in such a circuit.

This will be described with reference to FIG. Here, between the two semiconductor devices a and b, the level (potential) of the signal line when the pMOS transistor P1 is on on the a side and the nMOS transistor N1 is on on the b side
Is determined by the on-resistance of these transistors. When the on-resistance of the a-side pMOS transistor P1 is higher than that of the b-side nMOS transistor N1, the current I flowing between the semiconductor devices a and b is The signal level is substantially determined by the on-resistance of the pMOS transistor P1, and the signal level is Vdd /
Determined to be lower than 2. In the opposite case, that is, p on the a side
When the ON resistance of the MOS transistor P1 is lower than that of the nMOS transistor N1 on the b side, the signal level is determined to be higher than Vdd / 2. This is the a-side nMOS
The same applies to the relationship between the transistor N1 and the p-side pMOS transistor P1.

In general, the performance of a transistor of a semiconductor device is determined by using different conductivity type M transistors such as a p-channel transistor and an n-channel transistor.
It is extremely difficult from the viewpoint of manufacturing control to match the OS transistors while suppressing their variations, and to guarantee the matching of performance and characteristics between different semiconductor devices.

For this reason, when a simultaneous bidirectional input / output buffer as shown in FIG.
The variation of the ON resistance of the MOS transistor is 50 to 7
This is about 0%, and the output intermediate level has a disadvantage of about 20 to 30% variation with respect to Vdd / 2 which is the design center.

In some cases, a resistor is connected in series to the output buffer section for stabilization at an intermediate level. However, in this case, there is a problem that the burden of manufacturing control of the resistor increases.

Accordingly, an object of the present invention is to provide a semiconductor device which solves the above-mentioned problems and stabilizes an intermediate output level in such a simultaneous bidirectional buffer.

[0020]

In order to achieve the above object, the present invention provides a CMOS type output buffer for outputting an output signal of a semiconductor device to an input / output terminal; An input buffer circuit for outputting a ternary value to the semiconductor device in accordance with a signal level of the input / output terminal, wherein the simultaneous type bidirectional input / output buffer further controls a current flowing through the CMOS output buffer. Means for controlling the intermediate value level to be set at an intermediate value of the power supply voltage.

Further, the present invention preferably provides a bidirectional buffer for simultaneously performing input / output via one terminal of a semiconductor device, wherein the logic level of the terminal is ternary, and In a simultaneous bidirectional input / output buffer, wherein a logic decision level is made variable in accordance with the logical output content of the bidirectional buffer, an output circuit of the bidirectional buffer comprises a CMOS logic circuit,
A first current limiting means is inserted between the CMOS logic circuit and a second current limiting means.
Wherein the current limiting means is inserted.

In the simultaneous bidirectional input / output buffer of the present invention, preferably, the first current limiting means is a pMO.
Forming a first current mirror circuit with S transistors;
The second current limiting means constitutes a second current mirror circuit using an nMOS transistor.

In the simultaneous type bidirectional input / output buffer according to the present invention, preferably, a current which determines an operation state of the first and second current mirror circuits is supplied from outside through respective terminals of the semiconductor device. It is characterized by having such a configuration.

[0024]

According to the present invention, the output buffer is controlled by controlling the current of the transistor in the on state of the output buffer to properly control the intermediate value level when the bidirectional buffers are interconnected to the intermediate value of the power supply voltage. Is achieved by avoiding fluctuations in the intermediate value level due to variations in characteristics between transistors of different conductivity types.

In the present invention, by adding a current limiting circuit comprising a current mirror circuit to the simultaneous type bidirectional input / output buffer, the intermediate potential level can be stabilized even when the manufacturing variation of the semiconductor device is large. It is.

Further, according to the present invention, when two semiconductor devices are interconnected via a wiring, one conductive type MOS transistor of a CMOS logic circuit of one side bidirectional buffer and one side of a bidirectional buffer CMOS logic circuit are connected. The currents flowing through the other conductivity type MOS transistors of the buffer are equal, the intermediate level is kept exactly at ２ of the power supply voltage, and the intermediate level does not depend on chip-to-chip variations in device characteristics.

The present invention makes it possible to variably set the capacity / impedance of a buffer from an external terminal of a semiconductor device.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

[0029]

Embodiment 1 A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a semiconductor device including a simultaneous bidirectional input / output buffer according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram in which this is connected between two semiconductor devices a and b.

Referring to FIG. 1, a semiconductor device according to a first embodiment of the present invention includes a plurality of simultaneous type bidirectional buffers IOBU.
F and level generating circuits VBPG and VBNG for applying the operation bias potentials VBP and VBN.

The simultaneous type bidirectional buffer IOBUF has an output terminal OUT and an input terminal I connected to the inside of the semiconductor device.
N, an input / output terminal IO for interfacing with the outside of the semiconductor device. The output side circuit includes four pMOS and nMOS transistors P1, P2, whose sources and drains are connected in series between the power supply Vdd and the ground potential.
The gates of the MOS transistors P1 and N1 are commonly connected to an output terminal OUT, and the drains are connected to an input / output terminal IO and an input determination unit IBUF.

The operating bias potentials VBP and VBN are applied to the gates of the MOS transistors P2 and N2 from the level generating circuits VBPG and VBNG, respectively.

The input determination unit IBUF has two logic determination levels VR in the same manner as the conventional example described with reference to FIG.
1, VR2 is compared with the potential of the input / output terminal IO. 2
The comparators C1 and C2 are connected to a selector circuit selected by an output terminal OUT, and the output is connected from an input terminal IN to an internal circuit of the semiconductor device.

Referring to FIG. 1, level generation circuit VBPG
Is a circuit for generating an operating bias VBP applied to the simultaneous bidirectional buffer IOBUF. The pMOS transistors P3 and P4, whose sources and drains are connected in series between the power supply Vdd and the reference current input terminal IREF1, and the reference potential VR0. And a comparator C3 for comparing the potential with the reference current input terminal IREF1.
It is connected to the gate of MOS transistor P4.

Similarly, the level generating circuit VBNG has an operation bias VB applied to the simultaneous bidirectional buffer IOBUF.
N, NMOS transistors N3 and N4 whose sources and drains are connected in series between a ground potential and a reference current input terminal IREF2, and a reference potential V
R0, a reference current input terminal IREF2, and a comparator C4 for comparing potentials. The output VBN is connected to the gate of the nMOS transistor N4.

In this embodiment, it is assumed that the reference potential VR0 gives the output intermediate level = Vdd × 1/2, and the logical decision levels VR1 and VR2 are VDD ・ 3/4, Vdd
・ A potential of 1/4 shall be applied.

The reference current input terminals IREF1, IREF
It is assumed that REF2 is maintained such that predetermined equal currents (constant currents) flow in or out from the outside of the semiconductor device. Further, MOS transistors P1, P
2 is equal to P3 and P4, and the sizes of N1 and N2 are equal to N3 and N4.

Next, the operation of this embodiment will be described.

As shown in FIG. 2, a, b between two semiconductor devices
The simultaneous type bidirectional buffer according to this embodiment is connected, the output terminal OUT on the a side is at the “H” level, the output terminal OUT on the b side is at the “L” level, and the The case where the wiring is at an intermediate level will be described.

The nMOS transistor N1 on the a side and the pMOS transistor P1 on the b side are turned on, and the current flowing therethrough is nM of the level generation circuit VBNG on the a side.
It is limited by the nMOS transistor N2 mirror-connected to the OS transistor N4, and on the b side, it is limited by the pMOS transistor P2 mirror-connected to the pMOS transistor P4 of the level generation circuit VBPG.

In the level generation circuit VBNG, the gate potential of the nMOS transistors N2 and N4 is determined by the comparator C4 so that the potential of the reference current input terminal IREF2 is maintained at the same potential as the reference potential VR0.

For this reason, the nMOS transistors N1, N
2, the drain potential of the nMOS transistor N2 is V
In the case of dd / 2, the same current as the current given to the terminal IREF2 flows. This is the same for the level generation circuit VBPG.

Reference current input terminals IREF1, IREF2
Since the same current flows on both sides a and b, n
The currents flowing through the pMOS transistors P1, P2 on the MOS transistors N1, N2, b side are equal to this reference current, the intermediate level is accurately maintained at Vdd / 2, and depends on the transistor manufacturing variation between the two semiconductor devices. do not do.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments but includes various embodiments according to the principle of the present invention.

[0045]

As described above, according to the present invention (claim 1), the intermediate value level when the bidirectional buffers are interconnected is controlled by controlling the transistor current flowing through the CMOS output buffer. Correctly set the intermediate value of the power supply voltage (1 /
2), the effect of stabilizing the intermediate value level without depending on the variation in the characteristics such as the on-resistance between transistors of different conductivity types constituting the output buffer and the variation in the characteristics between the chips. Having.

According to the present invention (claims 2 and 3),
By adding a current limiting circuit, which is preferably a current mirror circuit, to the simultaneous bidirectional input / output buffer, it is possible to stabilize the intermediate potential level even when the manufacturing variability of the semiconductor device is large.

According to the present invention (claims 2 and 3),
When two semiconductor devices are connected to each other via a wiring by a simple circuit configuration, a CMOS of a bidirectional buffer on one side is used.
The currents flowing through the MOS transistor of one conductivity type of the logic circuit and the MOS transistor of the bidirectional buffer on the other side are equal, and the intermediate level is exactly maintained at 電源 of the power supply voltage. It does not depend on the variation between chips.

Further, according to the present invention (claim 4), there is an effect that the capacity / impedance of the buffer can be varied from outside the semiconductor chip.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor device including a simultaneous type bidirectional input / output buffer according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a state where two semiconductor devices of FIG. 1 are connected;

FIG. 3 is a circuit diagram of a conventional semiconductor device including a simultaneous type bidirectional input / output buffer.

FIG. 4 is a diagram showing a state in which two semiconductor devices of FIG. 3 are connected;

[Explanation of symbols]

 IOBUF bidirectional buffer IBUF input determination unit VGNB, VBPG bias generation circuit C1, C2, C3, C4 voltage comparator IO, OUT, IN signal terminal IREF1, IREF2 reference current input terminal VR0, VR1, VR2 reference potential terminal N1, N2, N3 , N4 nMOS transistors P1, P2, P3, P4 pMOS transistors

Claims (4)

(57) [Claims] A CMOS output buffer for outputting an output signal of a semiconductor device to an input / output terminal; A simultaneous type bidirectional input / output buffer having an input buffer circuit for outputting to the semiconductor device; and a means for controlling a current flowing through the CMOS type output buffer, wherein the intermediate value level is set to an intermediate value of the power supply voltage. A simultaneous bidirectional input / output buffer characterized by being controlled to be set. 2. A bidirectional buffer for simultaneously inputting and outputting data via one terminal of a semiconductor device, wherein the logic level of the terminal is ternary, and the input logic determination level of the bidirectional buffer is the bidirectional buffer. In the simultaneous type bidirectional input / output buffer, which is variable according to the logical output content of the buffer, the output circuit of the bidirectional buffer is formed of a CMOS logic circuit, and a CMOS logic circuit is provided between a high-potential-side power supply and the CMOS logic circuit. 1 current limiting means, and the low-potential-side power supply and the CM
A simultaneous bidirectional input / output buffer, wherein a second current limiting means is inserted between the buffer and the OS logic circuit. 3. The first current limiting means forms a first current mirror circuit using a pMOS transistor.
3. The current limiting means comprises a second current mirror circuit formed by an nMOS transistor.
A simultaneous bidirectional input / output buffer as described. 4. The semiconductor device according to claim 3, wherein a current for determining an operation state of said first and second current mirror circuits is supplied from outside through respective terminals of said semiconductor device. Simultaneous bidirectional I / O buffer.